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initialize the clock gating control signal of each modem clock domain

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Li Shuai 2022-12-20 21:25:24 +08:00 committed by wuzhenghui
parent 63af1e9631
commit e9172ddcea
1 changed files with 2 additions and 0 deletions
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2
components/esp_system/port/soc/esp32c6/clk.c
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@ -20,6 +20,7 @@
#include "soc/i2s_reg.h"
#include "esp_cpu.h"
#include "hal/wdt_hal.h"
#include "esp_private/esp_modem_clock.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "esp_rom_uart.h"
@ -178,6 +179,7 @@ void rtc_clk_select_rtc_slow_clk(void)
*/
__attribute__((weak)) void esp_perip_clk_init(void)
{
modem_clock_domain_pmu_state_icg_map_init();
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: IDF-5658
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;