In previous gpio default isr, interrupt status bits get cleared at the exit of the isr.
However, for edge-triggered interrupt type, the interrupt status bit should be cleared before entering the per-pin handlers to avoid any potential interrupt lost.
Closes https://github.com/espressif/esp-idf/pull/6853
Wrap the ledc, i2c source files with the new caps in CMakeLists and linker.lf.
This could avoid potential source file not found warning during linking time.
essl_spi: fix wrong dummy cycle under quad spi mode ant add a test to verify spi quad mod
Closes IDF-5182 and IDF-5181
See merge request espressif/esp-idf!18680
This commit gives basic mmu driver framework. Now it is able to maintain
mmu virtual address usage on esp32, esp32s2 and esp32s3. Usage to
external virtual address should rely on mmu functions to know which
address range is available, instead of hardcoded.
This commit also improves psram memory that is added to the heap
allocator. Now it's added to the heap, according to the memory
alignment.
Closes https://github.com/espressif/esp-idf/issues/8295
sdio_slave: workaround the sdio_slave crash issue with release config + GCC11
Closes IDFCI-1296, IDFCI-1297, and IDFCI-1298
See merge request espressif/esp-idf!19680
This commit fixes gpio_hold_en(pin) function for ESP32, where after wakeup from deep sleep, the pin gets reset to default state and stop holding the pin level.
1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8.
2.Put the spi command the spi defintion in spi_types.h
3.Put the function which get spi command or dummy bits in spi_ll.h
Added a kconfig option. By default, when using ADC oneshot
driver, it will disable
DAC channels:
- ESP32: IO25, IO26
- ESP32S2: IO17, IO18
if ADC2 is in use.
You can disable this option, to measure DAC output, via internal ADC.
This is for test usage.
uart: update console docs about frequency for ESP32-C2, move frequency of clock sources out of HAL
Closes IDF-5424 and IDF-4332
See merge request espressif/esp-idf!19274
Prior to this commit, adc ulp is disabled by setting
adc_oneshot_unit_init_cfg_t::ulp_mode to false.
After this commit, a new enum `ADC_ULP_MODE_DISABLE` is added. So
setting `ulp_mode` to `ADC_ULP_MODE_DISABLE`, instead of `false`, to
disable the ulp mode.
Internally, disable usb serial jtag DP pin's pullup when calling gpio_ll_pullup_dis and rtcio_ll_pullup_disable
At usb serial jtag setup/install, re-enable DP pin's pullup
Closes https://github.com/espressif/esp-idf/issues/9495
Closes: https://github.com/espressif/esp-idf/issues/9208
When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
1. Since the baud rate in the ROM cannot be changed,
set the default baud rate of the 26Mhz version
of esp32c2 to 74800
2. Since the systimer configuration of the 26Mhz
version requires a non-integer systimer frequency
configuration, and this feature is not supported
in the current ROM, this option is disabled for
the 26Mhz version esp32c2
XTAL_CLK_FREQ now depends on the actual XTAL used, remove this macro
and get the XTAL frequency from the RTC register instead.
No uses of XTAL_CLK_FREQ found, other than in the UART LL.
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:
1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.
For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.
This introduced two possible issues:
1. Overflow when multiplying systimer counter by 5
- Should not be an issue, since systimer counter is 52-bit, so
counter * 5 is no more than 55-bit.
2. The code needs to perform:
- divide by 5: when converting from microseconds to ticks
- divide by 52: when converting from ticks to microseconds
The latter potentially introduces a performance issue for the
esp_timer_get_time function.
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
