alex/esp-idf
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21,607 Commits 20 Branches 148 Tags 384 MiB
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70 Commits

Author SHA1 Message Date
morris
ef00bd59dc esp_rom: extract int matrix route and cpu ticks getter 2022-02-09 13:52:20 +08:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Armando
7240ad2b3a psram: refactor spiram.c on esp32s2 2022-01-13 11:07:57 +08:00
Cao Sen Miao
3a4db97cec spi_flash: move patch files to common rom patch folder 2021-12-30 14:05:12 +08:00
Cao Sen Miao
3dd1cfea18 spi_flash: refactor spi_flash.h to decline duplicated code 2021-12-30 14:05:12 +08:00
Sudeep Mohanty
e22b4007d3 esp_hw_support: Removed deprecated CPU util functions 
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h

The following functions are deprecated:
- get_sp()

The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()

The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()

All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2021-12-28 16:58:37 +05:30
Martin Vychodil
dd938eb952 System/Security: Memprot API unified (ESP32C3) 
Unified Memory protection API for all PMS-aware chips (ESP32C3)

Closes JIRA IDF-3849
 2021-12-21 01:50:36 +01:00
Cao Sen Miao
e81841318f CI: Enable ESP8684 build stage CI on master 2021-12-13 19:18:47 +08:00
Cao Sen Miao
7f0a746e6a move brownout trax cache_int_err to private folder 2021-11-26 18:27:53 +08:00
Cao Sen Miao
09487761cf ESP8684: add freertos, hal, esp_system support 2021-11-06 17:33:44 +08:00
Alexey Gerenkov
111ba5bbe6 trax: Adds ESP32-S3 support 2021-10-22 23:36:28 +03:00
Mahavir Jain
81e3eb45ca cpu_start: rename function to add core prefix for more clarity 2021-10-20 15:16:25 +05:30
Mahavir Jain
61820f5b30 cpu_start: let individual core clear its interrupt matrix 
There was race condition where interrupt entries set by APP cpu core
could have been cleared during PRO cpu startup.

This was observed while setting up "cache access error" interrupt in
SMP mode for ESP32-S3.

This fix allows to NOT modify or clear any entries set by other core
(APP or PRO) and thus avoiding any race conditions during startup code.
 2021-10-20 15:16:25 +05:30
Armando
2655a506c9 mspi: support auto detect octal flash vendor 2021-10-08 15:59:57 +08:00
Cao Sen Miao
6c0aebe279 esp_flash: add opi flash support in esp_flash chip driver, for MXIC 2021-09-07 14:44:40 +08:00
gaoxiaojie
191a494e08 support dcache 64Byte and 16k 2021-09-02 02:27:40 +08:00
jiangguangming
f7137254e9 flash_mmap: register flash2spiram info to ROM 2021-09-02 02:27:40 +08:00
Armando
a3dc625da6 mspi: support 120MHz Quad Flash and PSRAM on ESP32S3 2021-08-31 16:06:44 +08:00
Martin Vychodil
58aed7df98 ESP32S2: No assert()/abort() in Memprot API, use esp_err_t instead 
JIRA IDF-3634
 2021-08-26 09:20:00 +02:00
Wu Zheng Hui
3128a2544b Adjust the variable name & 
Add mapping support for different sizes of spi ram
 2021-08-25 16:06:28 +08:00
Armando (Dou Yiwen)
03fb3973a2 Merge branch 'feature/support_quad_flash_octal_psram_on_esp32s3' into 'master' 
mspi: support up-to-80MHz quad flash & up-to-80MHz octal psram on esp32s3

Closes IDF-3603

See merge request espressif/esp-idf!14346
 2021-08-04 03:57:16 +00:00
Armando
0f91a01a46 mspi: support up-to-80MHz quad flash & up-to-80MHz octal psram on esp32s3 2021-08-03 16:54:00 +08:00
Jiang Jiang Jian
aebdaf08a6 Merge branch 'bugfix/esp32s3_app_core_clock_gate_invalid_issue' into 'master' 
fix app cpu core clock gate invalid issue

Closes WIFI-3899

See merge request espressif/esp-idf!14518
 2021-07-31 03:00:58 +00:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
Li Shuai
8a10ba4179 system: fix app cpu core clock gate invalid issue 2021-07-28 11:34:29 +08:00
Angus Gratton
bbbbd5cf0c esp32s2: FPGA can boot to Hello World 2021-07-16 10:50:06 +10:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Shu Chen
5e3689ae0f esp32h2: update esp_system and esp_hw_support to support esp32h2 2021-07-01 19:53:11 +08:00
Ivan Grokhotkov
d7928bf1db Merge branch 'feature/esp32c3_apptrace' into 'master' 
apptrace: refactoring & esp32c3 support

See merge request espressif/esp-idf!11702
 2021-06-28 06:00:24 +00:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Alexey Gerenkov
20fd09728f apptrace: Adds ESP32-C3 support 2021-06-24 13:16:14 +03:00
Martin Vychodil
1e58eb6928 system/security: Memprot bypassing mitigation 
Check Memprot lock bit(s) during the system startup, abort/reset on any Memprot parts found locked during this phase.
There is no legal reason to disallow the Memprot configuration by the system, so it's either a critical bug in the
application or an malicious attempt to bypass the system security.
Error message is printed before digital system reset.

Closes IDF-2700
 2021-06-01 00:07:09 +02:00
Shu Chen
ff3320ca8a esp32c3: fix typos of c3 path 2021-04-23 18:11:39 +08:00
Renz Bagaporo
7d85c42e52 esp32: move brownout and cache err int setup 2021-03-31 19:13:03 +08:00
Renz Bagaporo
8d32232899 esp_system: check early for single core variant 2021-03-29 06:50:47 +00:00
Cao Sen Miao
a8343bc470 esp_system: support gpio wakeup from deep sleep on esp32c3 2021-02-26 12:26:49 +08:00
morris
bf2480f62d efuse: can disable boot ROM log from Kconfig 2021-02-22 20:56:43 +08:00
Angus Gratton
dfda84c2ab esp_system: Fix some ESP_EARLY_LOG lines not being output fully 
At least on ESP32, calling esp_rom_uart_set_clock_baudrate() causes the
contents of the UART FIFO to be discarded.
 2021-02-01 14:24:38 +11:00
Ivan Grokhotkov
9a20283485 Merge branch 'bugfix/scan_test_missing_build_apps_without_tests' into 'master' 
ci: bugfix: scan_test missing build apps without tests

See merge request espressif/esp-idf!12138
 2021-01-28 17:48:24 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0) 
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
 2021-01-27 08:44:03 +01:00
Fu Hanxi
e4e375f488 fix: add spi_flash.h for s2, s3, c3 targets in cpu_start.c 
update s2, s3, c3 ld files spi_flash_attach to esp_rom_spiflash_attach
 2021-01-27 12:35:49 +08:00
Angus Gratton
55155c3f82 esp_system: Rename _init_start symbol to _vector_table 2020-12-24 13:40:01 +11:00
Angus Gratton
cfbded2ea1 esp_system: Add extra MMU config step for ESP32-C3 2020-12-24 13:40:01 +11:00
morris
c39476d699 esp_rom: added esp_rom_install_uart_printf 2020-12-11 11:45:10 +08:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Angus Gratton
420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
 2020-11-13 07:49:11 +11:00
Jeroen Domburg
4b444316ab Psram: Do not initialize spiram cache if no chip is found. 
Closes https://github.com/espressif/esp-idf/issues/6063
 2020-11-06 02:32:39 +00:00
Martin Vychodil
497b730e8f * memprot support for RTC_SLOW 
* API upgrade
JIRA IDF-1636
 2020-10-08 11:19:23 +08:00
jiangguangming
28145e0894 support flash instr and rodata copy to SPIRAM 2020-09-22 15:15:03 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00