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esp32s2: FPGA can boot to Hello World

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This commit is contained in:
Angus Gratton 2020-05-01 18:09:20 +10:00
parent 8cc8c60b45
commit bbbbd5cf0c
4 changed files with 14 additions and 3 deletions
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6
components/esp_hw_support/port/esp32s2/rtc_init.c
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@ -26,7 +26,8 @@
#include "soc_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
static const char *TAG = "rtc_init";
__attribute__((unused)) static const char *TAG = "rtc_init";
static void set_ocode_by_efuse(int calib_version);
static void calibrate_ocode(void);
@ -152,6 +153,8 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
}
#if !CONFIG_IDF_ENV_FPGA
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32);
@ -161,6 +164,7 @@ void rtc_init(rtc_config_t cfg)
calibrate_ocode();
}
}
#endif // !CONFIG_IDF_ENV_FPGA
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);

2
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@ -35,6 +35,7 @@
*/
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
#if !CONFIG_IDF_ENV_FPGA
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
@ -47,6 +48,7 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
#endif
if (cfg.sram_fpu) {
REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
} else {

2
components/esp_system/port/cpu_start.c
View File

@ -484,6 +484,7 @@ void IRAM_ATTR call_start_cpu0(void)
intr_matrix_clear();
#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
#ifdef CONFIG_ESP_CONSOLE_UART
uint32_t clock_hz = rtc_clk_apb_freq_get();
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@ -492,6 +493,7 @@ void IRAM_ATTR call_start_cpu0(void)
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif
#endif
#if SOC_RTCIO_HOLD_SUPPORTED
rtcio_hal_unhold_all();

7
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -83,8 +83,6 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
}
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
@ -145,6 +143,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
{
#ifdef CONFIG_IDF_ENV_FPGA
return;
#endif
rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
uint32_t cal_val = 0;
/* number of times to repeat 32k XTAL calibration
@ -283,11 +284,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;
#ifndef CONFIG_IDF_ENV_FPGA
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
* the current is not reduced when disable I2S clock.
*/
REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
#endif // CONFIG_IDF_ENV_FPGA
/* Disable some peripheral clocks. */
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);