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mspi: support auto detect octal flash vendor

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This commit is contained in:
Armando 2021-09-09 15:34:42 +08:00
parent a5ba1ac395
commit 2655a506c9
16 changed files with 281 additions and 171 deletions
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16
components/esp_hw_support/port/esp32s3/opiram_psram.c
View File

@ -27,7 +27,7 @@
#if CONFIG_SPIRAM_MODE_OCT
#include "soc/rtc.h"
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
#define OPI_PSRAM_SYNC_READ 0x0000
#define OPI_PSRAM_SYNC_WRITE 0x8080
@ -153,7 +153,7 @@ static void IRAM_ATTR s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *ou
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN;
int data_bit_len = 16;
//Read MR0 register
//Read MR0~1 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x0, addr_bit_len,
@ -162,7 +162,7 @@ static void IRAM_ATTR s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *ou
&out_reg->mr0.val, data_bit_len,
BIT(1),
false);
//Read MR2 register
//Read MR2~3 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
0x2, addr_bit_len,
@ -171,6 +171,7 @@ static void IRAM_ATTR s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *ou
&out_reg->mr2.val, data_bit_len,
BIT(1),
false);
data_bit_len = 8;
//Read MR4 register
esp_rom_opiflash_exec_cmd(spi_num, mode,
OPI_PSRAM_REG_READ, cmd_len,
@ -244,9 +245,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
//set to variable dummy mode
SET_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC && CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
esp_rom_spi_set_dtr_swap_mode(1, false, false);
#endif
//Set PSRAM read latency and drive strength
static DRAM_ATTR opi_psram_mode_reg_t mode_reg = {0};
@ -262,12 +261,9 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
mode_reg.mr2.density == 0x5 ? PSRAM_SIZE_128MBITS :
mode_reg.mr2.density == 0x7 ? PSRAM_SIZE_256MBITS : 0;
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC && CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
esp_rom_spi_set_dtr_swap_mode(1, true, true);
#endif
//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
spi_timing_psram_tuning();
////Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
spi_timing_enter_mspi_high_speed_mode(true);
/**
@ -275,6 +271,8 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
* This function is to restore SPI1 init state.
*/
spi_flash_set_rom_required_regs();
//Flash chip requires MSPI specifically, call this function to set them
spi_flash_set_vendor_required_regs();
s_config_psram_spi_phases();
return ESP_OK;

2
components/esp_hw_support/port/esp32s3/spiram_psram.c
View File

@ -39,7 +39,7 @@
#if CONFIG_SPIRAM_MODE_QUAD
#include "soc/rtc.h"
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
static const char* TAG = "psram";

37
components/esp_system/port/cpu_start.c
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@ -1,16 +1,8 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <string.h>
@ -64,7 +56,7 @@
#include "esp32h2/memprot.h"
#endif
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
#include "bootloader_flash_config.h"
#include "bootloader_flash.h"
#include "esp_private/crosscore_int.h"
@ -371,18 +363,25 @@ void IRAM_ATTR call_start_cpu0(void)
Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
esp_mspi_pin_init();
// For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
// So we have to read it here in SPI mode, before entering the OPI mode.
bootloader_flash_update_id();
#if CONFIG_ESPTOOLPY_OCT_FLASH
bool efuse_opflash_en = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA3_REG, EFUSE_FLASH_TYPE);
if (!efuse_opflash_en) {
ESP_EARLY_LOGE(TAG, "Octal Flash option selected, but EFUSE not configured!");
abort();
}
esp_opiflash_init();
#endif
esp_mspi_pin_init();
// For Octal flash, it's hard to implement a read_id function in OPI mode for all vendors.
// So we have to read it here in SPI mode, before entering the OPI mode.
bootloader_flash_update_id();
/**
* This function initialise the Flash chip to the user-defined settings.
*
* In bootloader, we only init Flash (and MSPI) to a preliminary state, for being flexible to
* different chips.
* In this stage, we re-configure the Flash (and MSPI) to required configuration
*/
spi_flash_init_chip_state();
#if CONFIG_IDF_TARGET_ESP32S3
//On other chips, this feature is not provided by HW, or hasn't been tested yet.
spi_timing_flash_tuning();

30
components/esptool_py/Kconfig.projbuild
View File

@ -66,15 +66,6 @@ menu "Serial flasher config"
bool "Enable Octal Flash"
default n
choice ESPTOOLPY_FLASH_VENDOR
depends on ESPTOOLPY_OCT_FLASH
prompt "Select OPI Flash Vendor"
default ESPTOOLPY_FLASH_VENDOR_MXIC
config ESPTOOLPY_FLASH_VENDOR_MXIC
bool "MXIC OPI FLASH(MX25UM25645G)"
endchoice
choice ESPTOOLPY_FLASHMODE
prompt "Flash SPI mode"
default ESPTOOLPY_FLASHMODE_DIO
@ -100,17 +91,16 @@ menu "Serial flasher config"
bool "OPI"
endchoice
choice ESPTOOLPY_FLASHMODE_OCT
depends on ESPTOOLPY_FLASHMODE_OPI
prompt "Flash OPI mode"
default ESPTOOLPY_FLASHMODE_OPI_DTR
choice ESPTOOLPY_FLASH_SAMPLE_MODE
prompt "Flash Sampling Mode"
default ESPTOOLPY_FLASH_SAMPLE_MODE_DTR if ESPTOOLPY_OCT_FLASH
default ESPTOOLPY_FLASH_SAMPLE_MODE_STR if !ESPTOOLPY_OCT_FLASH
config ESPTOOLPY_FLASHMODE_OPI_STR
depends on ESPTOOLPY_FLASH_VENDOR_MXIC
bool "OPI_STR"
config ESPTOOLPY_FLASHMODE_OPI_DTR
depends on ESPTOOLPY_FLASH_VENDOR_MXIC
bool "OPI_DTR"
config ESPTOOLPY_FLASH_SAMPLE_MODE_STR
bool "STR Mode"
config ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
depends on ESPTOOLPY_OCT_FLASH
bool "DTR Mode"
endchoice
# Note: we use esptool.py to flash bootloader in
@ -136,7 +126,7 @@ menu "Serial flasher config"
The SPI flash frequency to be used.
config ESPTOOLPY_FLASHFREQ_120M
depends on ESPTOOLPY_FLASHMODE_OPI_STR || !ESPTOOLPY_OCT_FLASH
depends on ESPTOOLPY_FLASH_SAMPLE_MODE_STR
bool "120 MHz"
config ESPTOOLPY_FLASHFREQ_80M
bool "80 MHz"

14
components/spi_flash/esp32s3/opi_flash_cmd_format_mxic.h
View File

@ -4,9 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC
#if CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR
#define OPI_CMD_FORMAT() { \
#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
#define OPI_CMD_FORMAT_MXIC() { \
.rdid = { \
.mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
.cmd_bit_len = 16, \
@ -93,8 +93,8 @@
} \
}
#elif CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
#define OPI_CMD_FORMAT() { \
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
#define OPI_CMD_FORMAT_MXIC() { \
.rdid = { \
.mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
.cmd_bit_len = 16, \
@ -180,5 +180,5 @@
.var_dummy_en = 1, \
} \
}
#endif
#endif
#endif // DTR / STR
#endif // #if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP

36
components/spi_flash/esp32s3/opi_flash_private.h Normal file
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@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* System level OPI Flash APIs (private)
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Register ROM functions and init flash device registers to make use of octal flash
*
* @param chip_id Full device ID read via RDID command
*/
esp_err_t esp_opiflash_init(uint32_t chip_id);
/**
* @brief Set Octal Flash chip specifically required MSPI register settings here
*/
void esp_opiflash_set_required_regs(void);
#ifdef __cplusplus
}
#endif

116
components/spi_flash/esp32s3/spi_flash_oct_flash_init.c
View File

@ -5,27 +5,33 @@
*/
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_rom_gpio.h"
#include "esp32s3/rom/gpio.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
#include "opi_flash_private.h"
#include "soc/spi_mem_reg.h"
#include "soc/io_mux_reg.h"
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC
#include "opi_flash_cmd_format_mxic.h"
#endif
#define SPI_FLASH_SPI_CMD_WRCR2 0x72
#define SPI_FLASH_SPI_CMD_RDSR 0x05
#define SPI_FLASH_SPI_CMD_RDCR 0x15
#define SPI_FLASH_SPI_CMD_WRSRCR 0x01
/**
* Supported Flash chip vendor id
*/
#define ESP_FLASH_CHIP_MXIC_OCT 0xC2
const static char *TAG = "Octal Flash";
// default value is rom_default_spiflash_legacy_flash_func
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
extern int SPI_write_enable(void *spi);
DRAM_ATTR const esp_rom_opiflash_def_t opiflash_cmd_def = OPI_CMD_FORMAT();
static uint32_t s_vendor_id;
static void s_register_rom_function(void)
@ -46,7 +52,24 @@ static void s_register_rom_function(void)
rom_spiflash_legacy_funcs = &rom_func;
}
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC
#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
/*----------------------------------------------------------------------------------------------------
MXIC Specific Functions
-----------------------------------------------------------------------------------------------------*/
static esp_err_t s_probe_mxic_chip(uint32_t chip_id, uint8_t *out_vendor_id)
{
if (chip_id >> 16 != ESP_FLASH_CHIP_MXIC_OCT) {
return ESP_ERR_NOT_FOUND;
}
if (((chip_id >> 8) & 0xff) != 0x80) {
ESP_EARLY_LOGE(TAG, "Detected MXIC Flash, but memory type is not Octal");
return ESP_ERR_NOT_FOUND;
}
*out_vendor_id = ESP_FLASH_CHIP_MXIC_OCT;
return ESP_OK;
}
// 0x00: SPI; 0x01: STR OPI; 0x02: DTR OPI
static void s_set_flash_dtr_str_opi_mode(int spi_num, uint8_t val)
{
@ -127,7 +150,8 @@ static void s_set_pin_drive_capability(uint8_t drv)
static void s_flash_init_mxic(esp_rom_spiflash_read_mode_t mode)
{
esp_rom_opiflash_legacy_driver_init(&opiflash_cmd_def);
static const esp_rom_opiflash_def_t opiflash_cmd_def_mxic = OPI_CMD_FORMAT_MXIC();
esp_rom_opiflash_legacy_driver_init(&opiflash_cmd_def_mxic);
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
// increase flash output driver strength
@ -135,13 +159,13 @@ static void s_flash_init_mxic(esp_rom_spiflash_read_mode_t mode)
// STR/DTR specific setting
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
#if CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
s_set_pin_drive_capability(3);
s_set_flash_dtr_str_opi_mode(1, 0x1);
esp_rom_opiflash_cache_mode_config(mode, &rom_opiflash_cmd_def->cache_rd_cmd);
esp_rom_spi_set_dtr_swap_mode(0, false, false);
esp_rom_spi_set_dtr_swap_mode(1, false, false);
#else //CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
#else //CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
s_set_pin_drive_capability(3);
s_set_flash_dtr_str_opi_mode(1, 0x2);
esp_rom_opiflash_cache_mode_config(mode, &rom_opiflash_cmd_def->cache_rd_cmd);
@ -149,26 +173,82 @@ static void s_flash_init_mxic(esp_rom_spiflash_read_mode_t mode)
esp_rom_spi_set_dtr_swap_mode(1, true, true);
#endif
s_register_rom_function();
esp_rom_opiflash_wait_idle();
}
#endif // #if CONFIG_FLASH_VENDOR_XXX
#endif // #if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
esp_err_t esp_opiflash_init(void)
/*----------------------------------------------------------------------------------------------------
General Functions
-----------------------------------------------------------------------------------------------------*/
typedef struct opi_flash_func_t {
esp_err_t (*probe)(uint32_t flash_id, uint8_t *out_vendor_id); //Function pointer for detecting Flash chip vendor
void (*init)(esp_rom_spiflash_read_mode_t mode); //Function pointer for initialising certain Flash chips
} opi_flash_func_t;
#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
static const opi_flash_func_t opi_flash_func_mxic = {
.probe = &s_probe_mxic_chip,
.init = &s_flash_init_mxic
};
#endif
static const opi_flash_func_t *registered_chip_funcs[] = {
#if CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
&opi_flash_func_mxic,
#endif
NULL,
};
esp_err_t esp_opiflash_init(uint32_t chip_id)
{
esp_err_t ret = ESP_FAIL;
esp_rom_spiflash_read_mode_t mode;
#if CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
mode = ESP_ROM_SPIFLASH_OPI_STR_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
#else
mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
#endif
#if CONFIG_ESPTOOLPY_FLASH_VENDOR_MXIC
s_flash_init_mxic(mode);
#else
abort();
#endif
//To check which Flash chip is used
const opi_flash_func_t **chip_func = &registered_chip_funcs[0];
uint8_t vendor_id = 0;
while (*chip_func) {
ret = (*chip_func)->probe(chip_id, &vendor_id);
if (ret == ESP_OK) {
// Detect this is the supported chip type
(*chip_func)->init(mode);
s_vendor_id = vendor_id;
s_register_rom_function();
break;
}
chip_func++;
}
if (ret != ESP_OK) {
ESP_EARLY_LOGE(TAG, "No detected Flash chip, please check the menuconfig to see if the chip is supported");
abort();
}
return ESP_OK;
}
/**
* Add Flash chip specifically required MSPI register settings here
*/
void esp_opiflash_set_required_regs(void)
{
bool is_swap = false;
#if CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
if (s_vendor_id == ESP_FLASH_CHIP_MXIC_OCT) {
is_swap = true;
}
#else
//STR mode does not need to enable ddr_swap registers
#endif
esp_rom_spi_set_dtr_swap_mode(0, is_swap, is_swap);
esp_rom_spi_set_dtr_swap_mode(1, is_swap, is_swap);
}

4
components/spi_flash/esp32s3/spi_timing_config.h
View File

@ -44,8 +44,8 @@ extern "C" {
* 2. DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
*/
//--------------------------------------FLASH Sampling Mode --------------------------------------//
#define SPI_TIMING_FLASH_DTR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR || CONFIG_ESPTOOLPY_FLASHMODE_OIO_DTR)
#define SPI_TIMING_FLASH_STR_MODE (CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR || !CONFIG_ESPTOOLPY_OCT_FLASH)
#define SPI_TIMING_FLASH_DTR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
#define SPI_TIMING_FLASH_STR_MODE CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
//--------------------------------------FLASH Module Clock --------------------------------------//
#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
#define SPI_TIMING_FLASH_MODULE_CLOCK 20

24
components/spi_flash/esp_flash_spi_init.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "esp_flash.h"
@ -27,7 +19,7 @@
#include "hal/gpio_hal.h"
#include "esp_flash_internal.h"
#include "esp_rom_gpio.h"
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
@ -71,9 +63,9 @@ esp_flash_t *esp_flash_default_chip = NULL;
#define DEFAULT_FLASH_MODE SPI_FLASH_DIO
#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
#define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR)
#elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR)
#define DEFAULT_FLASH_MODE SPI_FLASH_OPI_STR
#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR)
#elif defined(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR)
#define DEFAULT_FLASH_MODE SPI_FLASH_OPI_DTR
#else
#define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD

40
components/spi_flash/flash_ops.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include <assert.h>
@ -28,6 +20,7 @@
#include "esp_spi_flash.h"
#include "esp_log.h"
#include "esp_private/system_internal.h"
#include "esp_private/spi_flash_os.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h"
@ -43,6 +36,7 @@
#include "esp32s3/rom/cache.h"
#include "esp32s3/clk.h"
#include "esp32s3/clk.h"
#include "esp32s3/opi_flash_private.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/spi_flash.h"
@ -175,6 +169,16 @@ void IRAM_ATTR esp_mspi_pin_init(void)
#endif
}
esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
{
#if CONFIG_ESPTOOLPY_OCT_FLASH
return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
#else
//currently we don't need other setup for initialising Quad Flash
return ESP_OK;
#endif
}
void spi_flash_init(void)
{
spi_flash_init_lock();
@ -906,3 +910,13 @@ void IRAM_ATTR spi_flash_set_rom_required_regs(void)
*/
#endif
}
void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
{
#if CONFIG_ESPTOOLPY_OCT_FLASH
//Flash chip requires MSPI specifically, call this function to set them
esp_opiflash_set_required_regs();
#else
//currently we don't need to set other MSPI registers for Quad Flash
#endif
}

18
components/spi_flash/include/spi_flash_private.h → components/spi_flash/include/esp_private/spi_flash_os.h
View File

@ -4,7 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
/**
* System level MSPI APIs (private)
*/
/**
* Currently the MSPI timing tuning related APIs are designed to be private.
* Because:
@ -17,6 +19,10 @@
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_err.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
@ -34,9 +40,9 @@ extern "C" {
#endif
/**
* @brief Register ROM functions and init flash device registers to make use of octal flash
* @brief To setup Flash chip
*/
esp_err_t esp_opiflash_init(void);
esp_err_t spi_flash_init_chip_state(void);
/**
* @brief Make MSPI work under 20Mhz
@ -88,6 +94,12 @@ void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing
*/
bool spi_timine_config_flash_is_tuned(void);
/**
* @brief Set Flash chip specifically required MSPI register settings here
*/
void spi_flash_set_vendor_required_regs(void);
#ifdef __cplusplus
}
#endif

82
components/spi_flash/sim/Makefile.files
View File

@ -1,43 +1,45 @@
SOURCE_FILES := \
SpiFlash.cpp \
flash_mock.cpp \
flash_mock_util.c \
$(addprefix ../, \
partition.c \
flash_ops.c \
esp32/flash_ops_esp32.c \
) \
SpiFlash.cpp \
flash_mock.cpp \
flash_mock_util.c \
$(addprefix ../, \
partition.c \
flash_ops.c \
esp32/flash_ops_esp32.c \
) \
INCLUDE_DIRS := \
. \
../ \
../include \
../private_include \
$(addprefix stubs/, \
app_update/include \
driver/include \
esp_timer/include \
freertos/include \
log/include \
newlib/include \
sdmmc/include \
vfs/include \
) \
$(addprefix ../../../components/, \
esp_rom/include \
esp_common/include \
esp_hw_support/include \
esp_hw_support/include/soc \
esp_system/include \
xtensa/include \
xtensa/esp32/include \
soc/esp32/include \
heap/include \
soc/include \
esp32/include \
esp_timer/include \
bootloader_support/include \
app_update/include \
hal/include \
spi_flash/include \
)
. \
../ \
../include \
../private_include \
$(addprefix stubs/, \
app_update/include \
driver/include \
esp_timer/include \
freertos/include \
log/include \
newlib/include \
sdmmc/include \
vfs/include \
) \
$(addprefix ../../../components/, \
esp_rom/include \
esp_common/include \
esp_hw_support/include \
esp_hw_support/include/soc \
esp_system/include \
xtensa/include \
xtensa/esp32/include \
soc/esp32/include \
heap/include \
soc/include \
esp32/include \
esp_timer/include \
bootloader_support/include \
app_update/include \
hal/include \
hal/esp32/include \
hal/platform_port/include \
spi_flash/include \
)

6
components/spi_flash/spi_flash_timing_tuning.c
View File

@ -13,7 +13,7 @@
#include "esp_log.h"
#include "soc/spi_mem_reg.h"
#include "soc/io_mux_reg.h"
#include "spi_flash_private.h"
#include "esp_private/spi_flash_os.h"
#include "soc/soc.h"
#if CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/spi_timing_config.h"
@ -235,14 +235,14 @@ static void select_best_tuning_config(spi_timing_config_t *config, uint32_t cons
if (is_flash) {
#if SPI_TIMING_FLASH_DTR_MODE
best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
#else //#if SPI_TIMING_FLASH_STR_MODE
#elif SPI_TIMING_FLASH_STR_MODE
best_point = select_best_tuning_config_str(config, consecutive_length, end);
#endif
s_flash_best_timing_tuning_config = config->tuning_config_table[best_point];
} else {
#if SPI_TIMING_PSRAM_DTR_MODE
best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
#else //#if SPI_TIMING_PSRAM_STR_MODE
#elif SPI_TIMING_PSRAM_STR_MODE
best_point = select_best_tuning_config_str(config, consecutive_length, end);
#endif
s_psram_best_timing_tuning_config = config->tuning_config_table[best_point];

22
components/spi_flash/test/test_read_write.c
View File

@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Test for spi_flash_{read,write}.
@ -197,9 +189,9 @@ static void IRAM_ATTR fix_rom_func(void)
read_mode = ESP_ROM_SPIFLASH_DIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_OPI_STR
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
read_mode = ESP_ROM_SPIFLASH_OPI_STR_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_OPI_DTR
#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
read_mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
#endif

4
tools/ci/check_copyright_ignore.txt
View File

@ -1142,7 +1142,6 @@ components/esp_system/port/arch/xtensa/expression_with_stack.c
components/esp_system/port/arch/xtensa/panic_arch.c
components/esp_system/port/arch/xtensa/trax.c
components/esp_system/port/brownout.c
components/esp_system/port/cpu_start.c
components/esp_system/port/include/esp_clk_internal.h
components/esp_system/port/include/port/panic_funcs.h
components/esp_system/port/include/riscv/eh_frame_parser_impl.h
@ -2785,9 +2784,7 @@ components/spi_flash/esp32s2/flash_ops_esp32s2.c
components/spi_flash/esp32s2/spi_flash_rom_patch.c
components/spi_flash/esp32s3/flash_ops_esp32s3.c
components/spi_flash/esp_flash_api.c
components/spi_flash/esp_flash_spi_init.c
components/spi_flash/flash_mmap.c
components/spi_flash/flash_ops.c
components/spi_flash/include/esp_flash.h
components/spi_flash/include/esp_flash_internal.h
components/spi_flash/include/esp_flash_spi_init.h
@ -2828,7 +2825,6 @@ components/spi_flash/test/test_mmap.c
components/spi_flash/test/test_out_of_bounds_write.c
components/spi_flash/test/test_partition_ext.c
components/spi_flash/test/test_partitions.c
components/spi_flash/test/test_read_write.c
components/spi_flash/test/test_spi_flash.c
components/spiffs/esp_spiffs.c
components/spiffs/include/esp_spiffs.h

1
tools/ci/check_public_headers_exceptions.txt
View File

@ -148,4 +148,3 @@ components/ulp/include/esp32s2/ulp_riscv.h
components/lwip/include/apps/sntp/sntp.h
components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h
components/wifi_provisioning/include/wifi_provisioning/scheme_softap.h
components/spi_flash/include/spi_flash_private.h