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Merge branch 'bugfix/esp32s3_app_core_clock_gate_invalid_issue' into 'master'

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fix app cpu core clock gate invalid issue

Closes WIFI-3899

See merge request espressif/esp-idf!14518
This commit is contained in:
Jiang Jiang Jian 2021-07-31 03:00:58 +00:00
commit aebdaf08a6
2 changed files with 9 additions and 0 deletions
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6
components/esp_system/port/cpu_start.c
View File

@ -414,7 +414,13 @@ void IRAM_ATTR call_start_cpu0(void)
DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
#elif CONFIG_IDF_TARGET_ESP32S3
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
#if SOC_APPCPU_HAS_CLOCK_GATING_BUG
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETING
signals to ensure that the App core stops running in single-core mode. */
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
#endif
#endif // CONFIG_IDF_TARGET_ESP32
#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#endif // SOC_CPU_CORES_NUM > 1

3
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -28,6 +28,9 @@
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_PSRAM_DMA_CAPABLE 1
/*-------------------------- SOC CAPS ----------------------------------------*/
#define SOC_APPCPU_HAS_CLOCK_GATING_BUG (1)
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)