alex/esp-idf
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Code Issues Actions 2 Packages Projects Releases Wiki Activity
29,110 Commits 20 Branches 148 Tags 384 MiB
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81 Commits

Author SHA1 Message Date
Kevin (Lao Kaiyao)
d659991bbb Merge branch 'feature/gpio_runtime_preserve' into 'master' 
gpio: support runtime reserve

Closes IDF-6731

See merge request espressif/esp-idf!22223
 2023-03-18 10:55:44 +08:00
Jiang Jiang Jian
73c06b5039 Merge branch 'bugfix/sleep_current_issue_caused_by_sar_adc' into 'master' 
sleep current issue caused by sar adc

Closes IDF-6111 and WIFI-4370

See merge request espressif/esp-idf!22769
 2023-03-17 17:32:59 +08:00
Li Shuai
a25ce78392 sleep: fix sleep current issue caused by sar adc 2023-03-17 13:06:39 +08:00
laokaiyao
c9f780dc2e gpio: support runtime preserve 2023-03-17 11:59:49 +08:00
Mahavir Jain
fb1ef7c6d6
esp32h2: enable memory protection scheme using PMA and PMP 
Closes IDF-6452
 2023-03-15 13:16:18 +05:30
C.S.M
b0b99a9a1b Merge branch 'feature/flash_support_h2' into 'master' 
spi_flash: Allow clock frequency up to 64M on ESP32H2

See merge request espressif/esp-idf!22476
 2023-03-10 19:13:03 +08:00
Cao Sen Miao
bc655a6890 spi_flash: Allow clock frequency up to 64M, and make it default on ESP32H2 2023-03-10 11:39:53 +08:00
Sachin Parekh
7bd5d93905 esp_hw_support: Move cpu protection in port files 2023-03-09 11:37:29 +05:30
zhangwenxu
c07ec73201 efuse: fix esp_read_mac on esp32h2 2023-03-01 14:14:30 +08:00
Song Ruo Jing
1a66459b44 usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep 
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
   During sleep, BBPLL clock always gets disabled
   esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
   When this option is selected, IDF will constantly monitor USB CDC port connection status.
   As long as it gets connected to a HOST, automatic light-sleep will not happen.

Closes https://github.com/espressif/esp-idf/issues/8507
 2023-02-27 12:10:49 +08:00
Armando (Dou Yiwen)
4452a3cf3e Merge branch 'feature/support_h2_adc' into 'master' 
adc: support adc h2

Closes IDF-6124, IDF-6214, IDF-6543, IDF-6215, IDF-6664, and IDF-6695

See merge request espressif/esp-idf!22205
 2023-02-24 14:28:33 +08:00
Armando
d0e4d36fb6 esp_adc: support h2 oneshot mode and continuous mode 2023-02-23 11:48:31 +08:00
jingli
4c3d1e24d7 codeclean: remove unused sleep related functions 2023-02-23 11:36:13 +08:00
Song Ruo Jing
2c2a62e323 clk_tree: Add basic clock support for esp32h2 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration

Remove FPGA build for esp32h2
 2023-02-20 17:15:02 +08:00
morris
a3f887a1fe gpio: support glitch filter on esp32h2 2023-02-11 23:01:01 +08:00
Song Ruo Jing
b72d759290 uart: Add support for esp32h2 2023-02-06 00:48:04 +08:00
Song Ruo Jing
ad55230b0a ledc: Add support for esp32h2; Refactor ledc driver clock source selection related code 
LEDC examples and test cases are supported on ESP32H2.
   Switch to use general clock IDs for ledc_clk_cfg_t enum values.
   Deprecate LEDC_USE_RTC8M_CLK.
 2023-01-30 19:19:34 +08:00
Mahavir Jain
8203d40fc3
esp32h2: add support for SHA peripheral 
Closes IDF-6275
 2023-01-30 10:08:58 +05:30
morris
d9825f5165 Merge branch 'feature/add_clk_tree_get_frequency_api' into 'master' 
clk_tree: Stage 4 - Add a general API to get the frequency of different clocks

Closes IDF-6569

See merge request espressif/esp-idf!21830
 2023-01-17 17:08:23 +08:00
Song Ruo Jing
2c9aa4559c clk_tree: Add a general API to get the frequency of different clocks 
Add basic clk_tree driver and hal implementation.
 2023-01-17 11:30:24 +08:00
Marius Vikhammer
7100b7d1ff docs: add support for building H2 docs 2023-01-17 10:04:26 +08:00
morris
6c1d98d556 systimer: assign counter and alarm in esp_hw_support 2023-01-10 17:05:49 +08:00
Song Ruo Jing
981d6a67b0 clk: Add basic clock support for esp32h2 2023-01-03 11:00:32 +08:00
morris
cb7e957cc4 Merge branch 'feature/io_mux_use_pll80_c6' into 'master' 
io_mux: support change clock source to PLL_F80M

Closes IDF-6342 and IDF-6345

See merge request espressif/esp-idf!21613
 2022-12-29 22:06:52 +08:00
morris
672ac58ad5 io_mux: can set different clock source 2022-12-29 14:46:16 +08:00
Cao Sen Miao
4713a9a7f2 ESP32H2: Introduce new chip target esp32h2, hello_world example supported 2022-12-29 12:29:14 +08:00
Cao Sen Miao
86aa4df5b5 ESP32-H2: Introduce new target for ESP32H2 2022-11-23 14:38:05 +08:00
laokaiyao
8677216576 esp32h2: renaming esp32h2 to esp32h4 2022-11-08 17:05:33 +08:00
KonstantinKondrashov
1f9260d790 all: Apply new version logic (major * 100 + minor) 2022-11-03 08:36:23 +00:00
Armando
260ee86c37 rtc: united sar peripheral control 2022-10-27 16:51:25 +08:00
Aditya Patwardhan
f9565fd31d soc/esp_ds.h: Unify esp_ds error codes for all targets 2022-10-27 11:09:25 +05:30
Aditya Patwardhan
c8a788ca24 esp_hw_support: Merge HMAC source files into one 2022-10-27 10:59:54 +05:30
jingli
05a2fbe810 esp_hw_support/clk_cali: fix xtal32k error detect 2022-09-21 03:03:25 +00:00
Song Ruo Jing
842efaf753 Merge branch 'bugfix/rtc_fastmem_lpu_c3_h2' into 'master' 
sleep: fix wrong register access to set/clear rtc fast mem low power mode on c3 and h2

Closes IDF-5746

See merge request espressif/esp-idf!19361
 2022-08-03 19:52:24 +08:00
songruojing
e8915e14e7 esp_hw_support: fix wrong register access to set/clear rtc fast mem low power mode on c3 and h2 2022-08-03 14:33:13 +08:00
morris
45524408df coverity: fix uninit variable issue in driver 
Related CID:
389832, 389838, 389880, 286743, 286752, 395156, 291011, 396001, 396002
 2022-08-03 10:46:50 +08:00
morris
5e50ec1d66 systimer: add helper functions to convert between tick and us 2022-07-25 16:08:52 +08:00
Guillaume Souchere
6005cc9163 hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces 
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
 2022-07-22 00:06:06 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
morris
7fd9a91034 dma: move from driver to hw_support 2022-06-28 14:17:12 +08:00
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation 
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
 2022-06-20 11:34:20 +00:00
Martin Vychodil
339fcbf14d System/Security: Memprot API unified (ESP32S3) 
Unified Memory protection API for all PMS-aware chips - ESP32S3 port
 2022-06-20 02:36:44 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API 
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
 2022-06-14 14:30:58 +08:00
Darian Leung
556ec30457 esp_hw_support: Rename cpu_util.c to cpu.c 2022-06-14 14:30:57 +08:00
songruojing
c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00