alex/esp-idf
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500 Commits

Author SHA1 Message Date
Marius Vikhammer
1c73c657c9 Merge branch 'ci/console_test_coverage' into 'master' 
ci(console): improve esp-system console test-coverage

Closes IDFCI-1856, IDF-9576, and IDF-9577

See merge request espressif/esp-idf!29748
 2024-03-28 11:14:57 +08:00
wuzhenghui
621effce5b
fix(esp_system): workaround for CI pass 
1. workaround esp32p4 rev0 wrong deepsleep wakeup cause

2. workaround esp32p4 lightsleep stuck issue with PSRAM enabled
 2024-03-27 13:59:37 +08:00
wuzhenghui
ccaae61fee
feat(esp_hw_support): support esp32p4 deepsleep 2024-03-27 13:59:36 +08:00
Marius Vikhammer
42fc463c81 fix(console): fixed CONSOLE_NONE not working on C2/C3 2024-03-26 13:39:10 +08:00
morris
cf59c00564 change(mpll): clean up mpll clock acquire with ldo driver 2024-03-25 22:03:49 +08:00
Mahavir Jain
cdc1a2551b Merge branch 'feature/enable_rsa_support_for_c5' into 'master' 
feat: enable RSA support for c5

See merge request espressif/esp-idf!29189
 2024-03-22 10:10:47 +08:00
Alexey Lapshin
0e3673a2bd Merge branch 'feature/esp32p4-coredump-support' into 'master' 
esp32p4: panic tests support

Closes IDF-7565, IDF-7861, IDF-9035, and IDF-9075

See merge request espressif/esp-idf!28586
 2024-03-21 21:12:25 +08:00
Alexey Lapshin
13b55386bf feat(system): esp32p4: support hw stack guard 2024-03-21 14:30:21 +04:00
wanlei
a611e91b2f feat(esp32c61): new chip add system and esp_timer support 2024-03-21 11:31:15 +08:00
Darian
53e3833f44 Merge branch 'refactor/usb_fsls_phy_hal' into 'master' 
refactor(hal/usb): Update USB PHY related HAL/LL API

See merge request espressif/esp-idf!29659
 2024-03-20 06:07:29 +08:00
nilesh.kale
b11f286555 feat(esp_system/esp32c5): revised cypto clock to be used 
This commit updated crypto clock to use 160M SPLL clock
 2024-03-19 13:47:04 +05:30
Darian Leung
a77e5cc718
refactor(hal/usb): Remove usb_fsls_phy_ll.h 
For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.

This commit does the following:

- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
 2024-03-18 19:23:43 +08:00
laokaiyao
24d6dcb829 feat(esp32c5mp): add system related components 2024-03-18 17:34:56 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Konstantin Kondrashov
3f89072af1 feat(all): Use PRIx macro in all logs 2024-03-12 11:15:53 +02:00
wuzhenghui
9e8e20227f
feat(system): disable RNG module clock by default for save power 2024-03-12 10:10:41 +08:00
wuzhenghui
2a251982fc
feat(system): add option to allow user disable assist_debug module to save power 2024-03-12 10:10:40 +08:00
wuzhenghui
b0fa4565a1
feat(system): add option to allow user disable USJ module to save power 2024-03-12 10:10:36 +08:00
wuzhenghui
85b246ac88
feat(system): gate the debug clock source by default for esp32c6 and esp32h2 2024-03-07 19:26:39 +08:00
wuzhenghui
f5707c6ab8
feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
wuzhenghui
60e985e7af
feat(system): gate the LP peripheral clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
wuzhenghui
0528c8b4f4
feat(system): gate the HP peripheral clock by default for esp32c6 and esp32h2 2024-03-07 19:26:37 +08:00
nilesh.kale
f6a7fb13cd feat: re enables tests on p4 
This commit re-enables mbedtls and hal/crypto testapos on p4.
 2024-03-05 17:48:05 +08:00
Wan Lei
3459db1bbb Merge branch 'feat/c6lite_c61_introduce_step1_target' into 'master' 
feat(esp32c61): introduce target esp32c61 (1/8) 🌱

See merge request espressif/esp-idf!29238
 2024-03-05 11:36:17 +08:00
Konstantin Kondrashov
43c604f145 Merge branch 'feature/move_efuse_related_inits_into_component' into 'master' 
feat(efuse): Move efuse-related init steps into the component

Closes IDF-8759 and IDF-8761

See merge request espressif/esp-idf!28422
 2024-03-04 17:34:44 +08:00
KonstantinKondrashov
f9800e0726 feat(efuse): Move efuse-related init steps into the component 2024-03-01 21:07:03 +02:00
wanlei
ee02b71f1c feat(esp32c61): introduce target esp32c61 2024-03-01 21:12:25 +08:00
Alexey Lapshin
fdb7a43752 Merge branch 'feature/esp32p4_concontiguous_mem_mvp' into 'master' 
feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000 on P4

See merge request espressif/esp-idf!28783
 2024-02-29 16:28:13 +08:00
Alexey Lapshin
824c8e0593 feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000 
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:

- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
  SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data

If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):

  .dram0.bss (NOLOAD) :
  {
    arrays[dram0_bss]
    mapping[dram0_bss]
  } > sram_low

  .dram1.bss (NOLOAD) :
  {
    /* do not place here arrays[dram0_bss] because it may be splited
     * between segments */
    mapping[dram0_bss]
  } > sram_high
 2024-02-28 19:41:25 +04:00
Marius Vikhammer
c3ecd6d1f7 Merge branch 'bugfix/reset_reasons' into 'master' 
Update reset reasons for C6, H2, P4 and C5

Closes IDF-5719 and IDF-8660

See merge request espressif/esp-idf!28999
 2024-02-22 11:02:29 +08:00
Marius Vikhammer
4ce4af61ad fix(system): update reset reasons for P4 and C5 2024-02-21 11:59:28 +08:00
Marius Vikhammer
c0a2043562 fix(system): update reset reasons for C6 and H2 2024-02-20 12:27:09 +08:00
fl0wl0w
90d1dcfd76 feat(freertos): Introduced new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES 
This commit replaces the use of portNUM_PROCESSORS and configNUM_CORES
macros in all of ESP-IDF. These macros are needed to realize an SMP
scenario by fetching the number of active cores FreeRTOS is running on.
Instead, a new Kconfig option, CONFIG_FREERTOS_NUMBER_OF_CORES, has been
added as a proxy for the FreeRTOS config option, configNUMBER_OF_CORES.
This new commit is now used to realize an SMP scenario in various places
in ESP-IDF.

[Sudeep Mohanty: Added new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES]

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2024-02-09 09:11:28 +01:00
Song Ruo Jing
d556fee5c4 Merge branch 'feature/esp32c5_clock_preliminary_support' into 'master' 
Feature/esp32c5 clock preliminary support

See merge request espressif/esp-idf!28808
 2024-02-08 11:54:35 +08:00
Song Ruo Jing
95133c179f feat(clk): preliminary clock tree support for ESP32C5 2024-02-07 14:38:15 +08:00
liuning
3fa9c578f9 fix(clk): clear all lpclk source at clk init 2024-02-07 13:49:18 +08:00
laokaiyao
c0c6af99e9 fix(esp32c5): fixed the lack of crosscore ll on c5 2024-02-05 12:39:35 +08:00
Marius Vikhammer
06850e0e1e refactor(system): removed esp_system from astyle ignore list and reformated it 2024-01-30 15:17:15 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
 2024-01-25 19:15:33 +08:00
Aditya Patwardhan
4dc2ace0b7
fix(esp_hw_support): Update key manager support 
1) Added new Key Manager APIs
    2) Added crypto locking layer for Key Manager
    3) Remove support for deploying known key
    4) Format key manager support
    5) Fix build header error
    6) Updated the key_mgr_types.h file
    7) Added key manager tests
 2024-01-23 10:24:39 +05:30
Darian Leung
f50d83413e refactor(tools): Tidy up core component files copyright ignore 
Some files that should have their copyrights checked are still placed on the
copyright ignore list.

- These entries have been tidied up
- Copyrights of those files have been updated.
 2024-01-22 18:07:35 +08:00
Darian Leung
06952431a0 refactor(esp_system): Remove intr.c from the esp_system component 
This file is empty and not used anywhere, thus can be removed.
 2024-01-22 18:01:25 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
Cao Sen Miao
6768805d20 fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions, 
Closes https://github.com/espressif/esp-idf/issues/12958
 2024-01-18 10:51:51 +08:00
Ondrej Kosta
ce388a4111 feat(esp_eth): Added support of internal EMAC for ESP32P4 
Refactored internal EMAC DMA access.

Added MPLL acquire to manage access to the MPLL by multiple periphs.
 2024-01-16 14:29:25 +01:00
Xiao Xufeng
c204f418ef fix(rtc): fixed bbpll not calibrated from bootloader issue 2024-01-04 03:23:20 +08:00
laokaiyao
a48f4760d2 feat(esp32c5): add system related supports 2024-01-02 11:17:11 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4 
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
 2023-12-29 00:37:26 +08:00
Armando
71202c701f change(ldo): do vddpst ldo init in early stage 2023-12-26 11:43:33 +08:00
Marius Vikhammer
9f1d001849 Merge branch 'feat/cache_error_c6_h2' into 'master' 
fix(panic): fixed cache error being reported as illegal instruction

Closes IDF-6398, IDF-5657, IDF-7015, and IDF-6733

See merge request espressif/esp-idf!27430
 2023-12-21 10:32:06 +08:00