Merge c87cb854f3 into 46acfdce96

feat(nimble): Set data length after connection

See merge request espressif/esp-idf!32655

components/app_update/test_apps/test_app_update/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/app_update/test_apps/test_app_update/pytest_app_update_ut.py

@@ -24,7 +24,7 @@ def test_app_update(dut: Dut) -> None:
 
 
 @pytest.mark.supported_targets
-# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
+# TODO: [ESP32C61] IDF-9245, IDF-10983
 @pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
 @pytest.mark.generic
 @pytest.mark.parametrize(

components/bootloader_support/src/bootloader_mem.c

@@ -16,12 +16,6 @@
 #include "hal/apm_hal.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-#include "soc/hp_apm_reg.h"
-#include "soc/lp_apm_reg.h"
-#endif
-
-
 void bootloader_init_mem(void)
 {
 
@@ -38,13 +32,6 @@ void bootloader_init_mem(void)
 #endif
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-    // disable apm filter
-    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
-    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
-#endif
-
-
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
     esp_cpu_configure_region_protection();

components/bootloader_support/src/esp32c61/bootloader_sha.c

@@ -13,8 +13,6 @@
 
 static SHA_CTX ctx;
 
-//TODO: [ESP32C61] IDF-9234
-
 bootloader_sha256_handle_t bootloader_sha256_start()
 {
     // Enable SHA hardware

components/bt/CMakeLists.txt

@@ -855,16 +855,17 @@ if(CONFIG_BT_ENABLED)
         target_link_directories(${COMPONENT_LIB} INTERFACE
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
         target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C6)
-        add_prebuilt_library(libble_app
-                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c6/libble_app.a")
-        target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C61)
-        add_prebuilt_library(libble_app
-                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c61/libble_app.a")
-        target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     elseif(CONFIG_BT_CONTROLLER_ENABLED)
-        add_prebuilt_library(libble_app "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        if(CONFIG_IDF_TARGET_ESP32C6)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c6/libble_app.a")
+        elseif(CONFIG_IDF_TARGET_ESP32C61)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c61/libble_app.a")
+        else()
+            add_prebuilt_library(libble_app
+                 "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        endif()
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     endif()
 

components/bt/controller/lib_esp32c3_family

@@ -1 +1 @@
-Subproject commit b8ef2c474d392a88ea7e6626f89acf1fa5f30e4a
+Subproject commit 5c913171361dac0821e15e83cc0cf604149e1b84

components/bt/esp_ble_mesh/lib/lib

@@ -1 +1 @@
-Subproject commit 8312e0e0d5390d04fd282e8005528d2b5c351c08
+Subproject commit cba99c5a2e7f5d4bccb04e8f3f968dc888bb5667

components/bt/host/nimble/nimble

@@ -1 +1 @@
-Subproject commit 7e4f538a23591dfd361b90415eb517c6fc901a40
+Subproject commit 62b04f185717f31c57b802d5059e13b0d4d12b0c

components/bt/porting/npl/freertos/src/npl_os_freertos.c

@@ -21,6 +21,7 @@
 #include "esp_log.h"
 #include "soc/soc_caps.h"
 #include "esp_bt.h"
+#include "bt_osi_mem.h"
 
 portMUX_TYPE ble_port_mutex = portMUX_INITIALIZER_UNLOCKED;
 
@@ -95,7 +96,7 @@ IRAM_ATTR npl_freertos_event_init(struct ble_npl_event *ev, ble_npl_event_fn *fn
     }
 #else
     if(!ev->event) {
-        ev->event = malloc(sizeof(struct ble_npl_event_freertos));
+        ev->event = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_event_freertos));
     }
 #endif
     event = (struct ble_npl_event_freertos *)ev->event;
@@ -113,7 +114,7 @@ IRAM_ATTR npl_freertos_event_deinit(struct ble_npl_event *ev)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_ev_pool,ev->event);
 #else
-    free(ev->event);
+    bt_osi_mem_free(ev->event);
 #endif
     ev->event = NULL;
 }
@@ -144,7 +145,7 @@ npl_freertos_eventq_init(struct ble_npl_eventq *evq)
     }
 #else
     if(!evq->eventq) {
-        evq->eventq = malloc(sizeof(struct ble_npl_eventq_freertos));
+        evq->eventq = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_eventq_freertos));
         eventq = (struct ble_npl_eventq_freertos*)evq->eventq;
         BLE_LL_ASSERT(eventq);
         memset(eventq, 0, sizeof(*eventq));
@@ -167,7 +168,7 @@ npl_freertos_eventq_deinit(struct ble_npl_eventq *evq)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_evq_pool,eventq);
 #else
-    free((void *)eventq);
+    bt_osi_mem_free((void *)eventq);
 #endif
     evq->eventq = NULL;
 }
@@ -357,7 +358,7 @@ npl_freertos_mutex_init(struct ble_npl_mutex *mu)
     }
 #else
     if(!mu->mutex) {
-        mu->mutex = malloc(sizeof(struct ble_npl_mutex_freertos));
+        mu->mutex = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_mutex_freertos));
         mutex = (struct ble_npl_mutex_freertos *)mu->mutex;
 
         if (!mutex) {
@@ -388,7 +389,7 @@ npl_freertos_mutex_deinit(struct ble_npl_mutex *mu)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_mutex_pool,mutex);
 #else
-    free((void *)mutex);
+    bt_osi_mem_free((void *)mutex);
 #endif
     mu->mutex = NULL;
 
@@ -494,7 +495,7 @@ npl_freertos_sem_init(struct ble_npl_sem *sem, uint16_t tokens)
     }
 #else
     if(!sem->sem) {
-        sem->sem = malloc(sizeof(struct ble_npl_sem_freertos));
+        sem->sem = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_sem_freertos));
         semaphore = (struct ble_npl_sem_freertos *)sem->sem;
 
         if (!semaphore) {
@@ -525,7 +526,7 @@ npl_freertos_sem_deinit(struct ble_npl_sem *sem)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_sem_pool,semaphore);
 #else
-    free((void *)semaphore);
+    bt_osi_mem_free((void *)semaphore);
 #endif
     sem->sem = NULL;
 
@@ -684,7 +685,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 #else
 
     if(!co->co) {
-        co->co = malloc(sizeof(struct ble_npl_callout_freertos));
+        co->co = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_callout_freertos));
         callout = (struct ble_npl_callout_freertos *)co->co;
         if (!callout) {
             return -1;
@@ -704,7 +705,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (esp_timer_create(&create_args, &callout->handle) != ESP_OK) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -713,7 +714,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (!callout->handle) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -761,7 +762,7 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_co_pool,callout);
 #else
-    free((void *)callout);
+    bt_osi_mem_free((void *)callout);
 #endif // OS_MEM_ALLOC
     co->co = NULL;
     memset(co, 0, sizeof(struct ble_npl_callout));
@@ -1089,7 +1090,7 @@ struct npl_funcs_t * npl_freertos_funcs_get(void)
 
 void npl_freertos_funcs_init(void)
 {
-    npl_funcs = (struct npl_funcs_t *)malloc(sizeof(struct npl_funcs_t));
+    npl_funcs = (struct npl_funcs_t *)bt_osi_mem_malloc_internal(sizeof(struct npl_funcs_t));
     if(!npl_funcs) {
         printf("npl funcs init failed\n");
         assert(0);
@@ -1123,7 +1124,7 @@ int npl_freertos_mempool_init(void)
     ble_freertos_total_event_cnt = ble_total_evt_count;
 
     if (ble_total_evt_count) {
-        ble_freertos_ev_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evt_count,
+        ble_freertos_ev_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evt_count,
                                       sizeof (struct ble_npl_event_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_ev_buf) {
@@ -1138,7 +1139,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_evtq_count) {
-        ble_freertos_evq_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evtq_count,
+        ble_freertos_evq_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evtq_count,
                                        sizeof (struct ble_npl_eventq_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_evq_buf) {
@@ -1153,7 +1154,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_co_count) {
-        ble_freertos_co_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_co_count,
+        ble_freertos_co_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_co_count,
                                       sizeof (struct ble_npl_callout_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_co_buf) {
@@ -1168,7 +1169,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_sem_count) {
-        ble_freertos_sem_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_sem_count,
+        ble_freertos_sem_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_sem_count,
                                        sizeof (struct ble_npl_sem_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_sem_buf) {
@@ -1183,7 +1184,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_mutex_count) {
-        ble_freertos_mutex_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_mutex_count,
+        ble_freertos_mutex_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_mutex_count,
                                          sizeof (struct ble_npl_mutex_freertos)) *
                                          sizeof(os_membuf_t));
         if (!ble_freertos_mutex_buf) {
@@ -1200,27 +1201,27 @@ int npl_freertos_mempool_init(void)
     return 0;
 _error:
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
 
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
 
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
 
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
 
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
     return -1;
@@ -1229,23 +1230,23 @@ _error:
 void npl_freertos_mempool_deinit(void)
 {
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
 }
@@ -1253,7 +1254,7 @@ void npl_freertos_mempool_deinit(void)
 void npl_freertos_funcs_deinit(void)
 {
     if (npl_funcs) {
-        free(npl_funcs);
+        bt_osi_mem_free(npl_funcs);
     }
     npl_funcs = NULL;
 }

components/esp_common/src/esp_err_to_name.c

@@ -469,6 +469,11 @@ static const esp_err_msg_t esp_err_msg_table[] = {
 #   endif
 #   ifdef      ESP_ERR_DPP_AUTH_TIMEOUT
     ERR_TBL_IT(ESP_ERR_DPP_AUTH_TIMEOUT),                       /* 12442 0x309a DPP Auth response was not received in time */
+#   endif
+#   ifdef      ESP_ERR_DPP_INVALID_LIST
+    ERR_TBL_IT(ESP_ERR_DPP_INVALID_LIST),                       /* 12443 0x309b Channel list given in
+                                                                                esp_supp_dpp_bootstrap_gen() is not
+                                                                                valid or too big */
 #   endif
     // components/esp_common/include/esp_err.h
 #   ifdef      ESP_ERR_MESH_BASE

components/esp_hw_support/Kconfig

@@ -273,4 +273,13 @@ menu "Hardware Settings"
     config ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM
         bool
         default n
+
+    config ESP_CLK_RC32K_NOT_TO_USE
+        bool
+        default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
+        default n
+        help
+            Due to the poor low-temperature characteristics of
+            RC32K (it cannot operate below -40 degrees Celsius),
+            please avoid using it whenever possible
 endmenu

components/esp_hw_support/include/esp_crypto_lock.h

@@ -44,7 +44,7 @@ void esp_crypto_ds_lock_acquire(void);
 void esp_crypto_ds_lock_release(void);
 #endif /* SOC_DIG_SIGN_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 /**
  * @brief Acquire lock for the SHA and AES cryptography peripheral.
  *
@@ -56,9 +56,9 @@ void esp_crypto_sha_aes_lock_acquire(void);
  *
  */
 void esp_crypto_sha_aes_lock_release(void);
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
-#if defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA)
+#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
 /**
  * This API should be used by all components which use the SHA, AES, HMAC and DS crypto hardware on the ESP32S2.
  * They can not be used in parallel because they use the same DMA or are calling each other.
@@ -76,7 +76,7 @@ void esp_crypto_dma_lock_acquire(void);
  * Release lock for the AES and SHA cryptography peripherals, which both use the crypto DMA.
  */
 void esp_crypto_dma_lock_release(void);
-#endif /* defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA) */
+#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
 
 #ifdef SOC_MPI_SUPPORTED
 /**

components/esp_hw_support/include/esp_private/sleep_modem.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,7 +120,7 @@ bool modem_domain_pd_allowed(void);
 uint32_t sleep_modem_reject_triggers(void);
 
 /**
- * @brief Configure the parameters of the modem subsytem during the sleep process
+ * @brief Configure the parameters of the modem subsystem during the sleep process
  *
  * In light sleep mode, the wake-up early time of the WiFi module and the TBTT
  * interrupt early time (trigger enabling RF) are determined by the maximum and
@@ -132,7 +132,7 @@ uint32_t sleep_modem_reject_triggers(void);
  *
  * @param max_freq_mhz       the maximum frequency of system
  * @param min_freq_mhz       the minimum frequency of system
- * @param light_sleep_enable ture or false for enable or disable light sleep mode, respectively
+ * @param light_sleep_enable true or false for enable or disable light sleep mode, respectively
  *
  * @return
  *  - ESP_OK on success
@@ -225,6 +225,27 @@ void sleep_modem_wifi_modem_state_deinit(void);
   *   - false not skip light sleep
  */
 bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
+
+/**
+ * @brief Function to initialize and create the modem state phy link
+ * @param link_head the pointer that point to the head of the created phy link
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_NO_MEM if no memory for link
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_init(void **link_head);
+
+/**
+ * @brief Function to destroy and de-initialize modem state phy link
+ * @param link_head the phy link head will be destroyed
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
 #endif
 
 #ifdef __cplusplus

components/esp_hw_support/lowpower/CMakeLists.txt

@@ -24,6 +24,10 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S
     list(APPEND srcs "port/${target}/sleep_clock.c")
 endif()
 
+if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
+    list(APPEND srcs "port/${target}/sleep_modem_state.c")
+endif()
+
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -6,6 +6,7 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/rtc.h"
 #include "modem/modem_syscon_reg.h"
 #include "modem/modem_lpcon_reg.h"
 #include "soc/i2c_ana_mst_reg.h"
@@ -14,13 +15,43 @@ static const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG,  0,               PCR_AHB_DIV_NUM,      1, 0),                                     .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1,               PCR_BUS_CLOCK_UPDATE, 1, 0),                                     .owner = ENTRY(0) | ENTRY(1) },
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+        [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE,        DR_REG_PCR_BASE, 75,                   0, 0, 0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+#endif
     };
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+
+    const static sleep_retention_entries_config_t modem_ahb_config[] = {
+        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
+    };
+    err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
+    uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+    if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
+
+        /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
+         * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
+         * command memory */
+        sleep_retention_entries_config_t bbpll_config[] = {
+            [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
+            [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                          0xffffffff,                   1, 0), .owner = ENTRY(1) },
+            [2] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,     0x1,                          1, 0), .owner = ENTRY(1) },
+            [3] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG,         0,                          MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
+        };
+        extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+        bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config();
+        err = sleep_retention_entries_create(bbpll_config, ARRAY_SIZE(bbpll_config), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+        ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for bbpll configure, 0 level priority");
+    }
 #endif
+
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
 }

components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c

@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0158)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
+#define FECOEX_SET_CHAN_EN              (BIT(17))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+static __attribute__((unused)) const char *TAG = "sleep";
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
+{
+    #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
+
+    static sleep_retention_entries_config_t wifi_modem_config[] = {
+        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
+        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xf3800000,                0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = WIFIMAC_ENTRY() },
+        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = WIFIMAC_ENTRY() },
+        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU to trigger enable RXBLOCK */
+        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU or software to trigger disable RF PHY */
+        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = WIFIMAC_ENTRY() },
+        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1), .owner = WIFIMAC_ENTRY() },
+        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
+        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 1), .owner = WIFIMAC_ENTRY() },
+        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = WIFIMAC_ENTRY() },
+        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
+
+        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+
+        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
+    return ESP_OK;
+}
+#endif
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
+    err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
+    if (err == ESP_OK) {
+        err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
+        if (err == ESP_OK) {
+            *link_head = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00));
+        }
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+    esp_err_t err = ESP_OK;
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    if (err == ESP_OK) {
+        sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    }
+#endif
+    return err;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c

@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/esp_pau.h"
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0154)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
+#define FECOEX_SET_CHAN_EN              (BIT(14))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    static regdma_link_config_t wifi_modem_config[] = {
+        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
+        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
+
+        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
+        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
+        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
+        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
+        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
+        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [9]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
+        [11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
+        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
+        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
+        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
+        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
+
+        /* PMU to trigger enable RXBLOCK */
+        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
+
+        /* PMU or software to trigger disable RF PHY */
+        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
+        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
+        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
+        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
+        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
+        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
+        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
+        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
+
+        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
+        [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+
+        [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
+        [38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[7].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+
+    void *link = NULL;
+    for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
+        void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
+        if (next) {
+            link = next;
+        } else {
+            regdma_link_destroy(link, 0);
+            err = ESP_ERR_NO_MEM;
+        }
+    }
+    if (err == ESP_OK) {
+        pau_regdma_set_modem_link_addr(link);
+        *link_head = link;
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    regdma_link_destroy(link_head, 0);
+#endif
+    return ESP_OK;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/sleep_clock.h"
+#include "soc/pcr_reg.h"
+#include "modem/modem_syscon_reg.h"
+
+static const char *TAG = "sleep_clock";
+
+esp_err_t sleep_clock_system_retention_init(void *arg)
+{
+    const static sleep_retention_entries_config_t pcr_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0),   DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+    };
+
+    esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+    ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+}
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+esp_err_t sleep_clock_modem_retention_init(void *arg)
+{
+    #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
+
+    const static sleep_retention_entries_config_t modem_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
+    };
+
+    esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
+    ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+}
+#endif
+
+bool clock_domain_pd_allowed(void)
+{
+    const uint32_t inited_modules = sleep_retention_get_inited_modules();
+    const uint32_t created_modules = sleep_retention_get_created_modules();
+    const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
+
+    /* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
+     * through MODEM_SYSCON, when one or more MODEMs are initialized, it is
+     * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
+     * or off. The clock and reset of digital peripherals are managed through
+     * PCR, with TOP domain similar to MODEM domain. */
+    uint32_t modem_clk_dep_modules = 0;
+#if SOC_WIFI_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
+#endif
+#if SOC_BT_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+#if SOC_IEEE802154_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+
+    uint32_t mask = 0;
+    if (inited_modules & sys_clk_dep_modules) {
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    }
+    if (inited_modules & modem_clk_dep_modules) {
+#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+#endif
+    }
+    return ((inited_modules & mask) == (created_modules & mask));
+}
+
+ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
+{
+    sleep_retention_module_init_param_t init_param = {
+        .cbs       = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+    init_param = (sleep_retention_module_init_param_t) {
+        .cbs       = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
+#endif
+    return ESP_OK;
+}

components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c

@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "esp_attr.h"
+#include "esp_check.h"
+#include "esp_sleep.h"
+#include "esp_log.h"
+#include "esp_heap_caps.h"
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#include "soc/spi_mem_reg.h"
+#include "esp_private/startup_internal.h"
+
+static const char *TAG = "sleep_mmu";
+
+typedef struct {
+    uint32_t start;
+    uint32_t end;
+} mmu_domain_dev_regs_region_t;
+
+typedef struct {
+    mmu_domain_dev_regs_region_t *region;
+    int region_num;
+    uint32_t *regs_frame;
+} mmu_domain_dev_sleep_frame_t;
+
+/**
+ * Internal structure which holds all requested light sleep mmu retention parameters
+ */
+typedef struct {
+    struct {
+        mmu_domain_dev_sleep_frame_t *mmu_table_frame;
+    } retent;
+} sleep_mmu_retention_t;
+
+static DRAM_ATTR __attribute__((unused)) sleep_mmu_retention_t s_mmu_retention;
+
+static void * mmu_domain_dev_sleep_frame_alloc_and_init(const mmu_domain_dev_regs_region_t *regions, const int region_num)
+{
+    const int region_sz = sizeof(mmu_domain_dev_regs_region_t) * region_num;
+    int regs_frame_sz = 0;
+    for (int num = 0; num < region_num; num++) {
+        regs_frame_sz += regions[num].end - regions[num].start;
+    }
+    void *frame = heap_caps_malloc(sizeof(mmu_domain_dev_sleep_frame_t) + region_sz + regs_frame_sz, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL);
+    if (frame) {
+        mmu_domain_dev_regs_region_t *region = (mmu_domain_dev_regs_region_t *)(frame + sizeof(mmu_domain_dev_sleep_frame_t));
+        memcpy(region, regions, region_num * sizeof(mmu_domain_dev_regs_region_t));
+        void *regs_frame = frame + sizeof(mmu_domain_dev_sleep_frame_t) + region_sz;
+        memset(regs_frame, 0, regs_frame_sz);
+        *(mmu_domain_dev_sleep_frame_t *)frame = (mmu_domain_dev_sleep_frame_t) {
+            .region = region,
+            .region_num = region_num,
+            .regs_frame = (uint32_t *)regs_frame
+        };
+    }
+    return frame;
+}
+
+static inline void * mmu_domain_mmu_table_sleep_frame_alloc_and_init(void)
+{
+    #define MMU_TABLE_SIZE (512 * 4)
+    const static mmu_domain_dev_regs_region_t regions[] = {
+        { .start = SPI_MEM_MMU_ITEM_CONTENT_REG(0), .end = SPI_MEM_MMU_ITEM_CONTENT_REG(0) + MMU_TABLE_SIZE}
+    };
+    return mmu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
+}
+
+static IRAM_ATTR void mmu_domain_dev_regs_save(mmu_domain_dev_sleep_frame_t *frame)
+{
+    assert(frame);
+    mmu_domain_dev_regs_region_t *region = frame->region;
+    uint32_t *regs_frame = frame->regs_frame;
+
+    int offset = 0;
+    for (int i = 0; i < frame->region_num; i++) {
+        for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
+            REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
+            regs_frame[offset++] = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+        }
+    }
+}
+
+static IRAM_ATTR void mmu_domain_dev_regs_restore(mmu_domain_dev_sleep_frame_t *frame)
+{
+    assert(frame);
+    mmu_domain_dev_regs_region_t *region = frame->region;
+    uint32_t *regs_frame = frame->regs_frame;
+
+    int offset = 0;
+    for (int i = 0; i < frame->region_num; i++) {
+        for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
+            REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
+            REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0),regs_frame[offset++]);
+        }
+    }
+}
+
+IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore)
+{
+    if (backup_or_restore) {
+        mmu_domain_dev_regs_save(s_mmu_retention.retent.mmu_table_frame);
+    } else {
+        mmu_domain_dev_regs_restore(s_mmu_retention.retent.mmu_table_frame);
+    }
+}
+
+static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
+{
+    if (s_mmu_retention.retent.mmu_table_frame) {
+        heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame);
+        s_mmu_retention.retent.mmu_table_frame = NULL;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t esp_sleep_mmu_retention_init_impl(void)
+{
+    if (s_mmu_retention.retent.mmu_table_frame == NULL) {
+        void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init();
+        if (frame == NULL) {
+            goto err;
+        }
+        s_mmu_retention.retent.mmu_table_frame = (mmu_domain_dev_sleep_frame_t *)frame;
+    }
+    return ESP_OK;
+err:
+    esp_sleep_mmu_retention_deinit();
+    return ESP_ERR_NO_MEM;
+}
+
+esp_err_t esp_sleep_mmu_retention_init(void)
+{
+    return esp_sleep_mmu_retention_init_impl();
+}
+
+esp_err_t esp_sleep_mmu_retention_deinit(void)
+{
+    return esp_sleep_mmu_retention_deinit_impl();
+}
+
+bool mmu_domain_pd_allowed(void)
+{
+    return (s_mmu_retention.retent.mmu_table_frame != NULL);
+}
+
+ESP_SYSTEM_INIT_FN(sleep_mmu_startup_init, SECONDARY, BIT(0), 108)
+{
+    esp_err_t ret;
+    ret = esp_sleep_mmu_retention_init();
+    if (ret != ESP_OK) {
+        ESP_EARLY_LOGW(TAG, "Failed to enable TOP power down during light sleep.");
+    }
+    return ESP_OK;
+}

components/esp_hw_support/modem_clock.c

@@ -423,7 +423,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
     esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :
@@ -431,7 +431,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
     esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) (
               (src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :
@@ -486,7 +486,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module)
     esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :

components/esp_hw_support/port/esp32c5/Kconfig.rtc

@@ -35,3 +35,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 48 MHz external crystal clock (XTAL) can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 48 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "48 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp32c5/cpu_region_protect.c

@@ -34,44 +34,44 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between debug region & IROM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 2. ROM has configured the ROM region to be cacheable, so we just need to lock the configuration
-    PMA_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX);
 
     // 3. Gap between ROM & RAM
-    PMA_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between DRAM and I_Cache
-    PMA_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration
     // This function sets invalid regions but this is a valid memory region configuration that could have
     // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA.
     // This entry is also required to be set using PMA because the region needs to be configured as cacheable.
-    PMA_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
 
     // 6. Gap between D_Cache & LP_RAM
-    PMA_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 7. Gap between LP memory & peripheral addresses
-    PMA_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
 
     // 8. End of address space
-    PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
-
-    PMA_ENTRY_CFG_RESET(15);
-    PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp32c61/CMakeLists.txt

@@ -17,7 +17,7 @@ if(NOT BOOTLOADER_BUILD)
 
 endif()
 
-# TODO: [ESP32C61] IDF-9250
+# TODO: [ESP32C61] IDF-9304
 if(CONFIG_IDF_TARGET_ESP32C61)
     list(REMOVE_ITEM srcs
         "sar_periph_ctrl.c"

components/esp_hw_support/port/esp32c61/cpu_region_protect.c

@@ -35,34 +35,41 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between debug region & IROM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 3. Gap between ROM & RAM
-    PMA_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between DRAM and I_Cache
-    PMA_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration
     // This function sets invalid regions but this is a valid memory region configuration that could have
     // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA.
     // This entry is also required to be set using PMA because the region needs to be configured as cacheable.
-    PMA_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
 
     // 6. Gap between D_Cache & peripheral addresses
-    PMA_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
 
     // 7. End of address space
-    PMA_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE);
+
+    PMA_ENTRY_CFG_RESET(12);
+    PMA_ENTRY_CFG_RESET(13);
+    PMA_ENTRY_CFG_RESET(14);
+    PMA_ENTRY_CFG_RESET(15);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h

@@ -10,8 +10,6 @@
 extern "C" {
 #endif
 
-// TODO: IDF-9247
-
 #define PMU_EXT0_WAKEUP_EN          BIT(0)
 #define PMU_EXT1_WAKEUP_EN          BIT(1)
 #define PMU_GPIO_WAKEUP_EN          BIT(2)

components/esp_hw_support/port/esp32c61/private_include/pmu_param.h

@@ -476,12 +476,12 @@ typedef struct pmu_sleep_machine_constant {
         .reset_wait_time_us             = 1,    \
         .power_supply_wait_time_us      = 20,   \
         .power_up_wait_time_us          = 2,    \
-        .regdma_s2m_work_time_us        = 172,  \
-        .regdma_s2a_work_time_us        = 480,  \
-        .regdma_m2a_work_time_us        = 278,  \
-        .regdma_a2s_work_time_us        = 382,  \
-        .regdma_rf_on_work_time_us      = 70,   \
-        .regdma_rf_off_work_time_us     = 23,   \
+        .regdma_s2m_work_time_us        = 270,  \
+        .regdma_s2a_work_time_us        = 666,  \
+        .regdma_m2a_work_time_us        = 296,  \
+        .regdma_a2s_work_time_us        = 586,  \
+        .regdma_rf_on_work_time_us      = 138,  \
+        .regdma_rf_off_work_time_us     = 28,   \
         .xtal_wait_stable_time_us       = 250,  \
         .pll_wait_stable_time_us        = 1     \
     }                                           \

components/esp_hw_support/port/esp32p4/Kconfig.rtc

@@ -37,3 +37,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 40 MHz XTAL can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 40 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "40 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp32p4/cpu_region_protect.c

@@ -38,42 +38,44 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between CPU subsystem region & HP TCM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
 
     // 2. Gap between HP TCM and CPU Peripherals
-    PMA_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
 
     // 3. Gap between CPU Peripherals and I_Cache
-    PMA_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between I_Cache and external memory range
-    PMA_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE);
 
     // 5. Gap between external memory and ROM
-    PMA_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 6. Gap between ROM and internal memory
-    PMA_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 7. Gap between internal memory and HP peripherals
-    PMA_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE);
 
     // 8. Special case - This whitelists the External flash/RAM, HP ROM and HP L2MEM regions and make them cacheable.
     // At the startup, this is done using PMA entry 15 by the ROM code.
-    PMA_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX);
 
     // 9. Gap between Uncacheable L2 Mem and end of address space
-    PMA_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE);
-    PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp_clk_tree_common.c

@@ -191,7 +191,7 @@ uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
     case SOC_RTC_FAST_CLK_SRC_LP_PLL:
         return clk_ll_lp_pll_get_freq_mhz() * MHZ;
 #endif
-#if SOC_CLK_LP_FAST_SUPPORT_XTAL
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
     case SOC_RTC_FAST_CLK_SRC_XTAL:
         return clk_hal_xtal_get_freq_mhz() * MHZ;
 #endif

components/esp_hw_support/sleep_modem.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,24 +12,19 @@
 #include "esp_log.h"
 #include "esp_attr.h"
 #include "esp_sleep.h"
+#include "esp_check.h"
 #include "soc/soc_caps.h"
 #include "esp_private/pm_impl.h"
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 #include "sdkconfig.h"
 
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA
-#include "modem/modem_syscon_reg.h"
-#include "modem/modem_lpcon_reg.h"
-#include "soc/i2c_ana_mst_reg.h"
-#include "esp_pau.h"
-#endif
-
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
-#include "soc/pmu_reg.h"
-#include "esp_private/esp_pau.h"
 #include "esp_private/esp_pmu.h"
 #endif
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA
+#include "esp_pau.h"
+#endif
 
 static __attribute__((unused)) const char *TAG = "sleep_modem";
 
@@ -136,29 +131,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void)
 
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
 
-#define PMU_RF_PWR_REG                  (0x600b0154)
-#define SARADC_TSENS_REG                (0x6000e058)
-#define SARADC_TSENS_PU                 (BIT(22))
-#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
-#define FECOEX_SET_CHAN_EN              (BIT(14))
-#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
-#define FECOEX_SET_CHAN_DONE            (BIT(8))
-#define FECOEX_AGC_CONF_REG             (0x600a7030)
-#define FECOEX_AGC_DIS                  (BIT(29))
-#define WDEVTXQ_BLOCK                   (0x600A4ca8)
-#define WDEV_RXBLOCK                    (BIT(12))
-#define MODEM_FE_DATA_BASE              (0x600a0400)
-#define MODEM_FE_CTRL_BASE              (0x600a0800)
-
-#define I2C_BURST_VAL(host, start, end) (((host) << 31) | ((end) << 22) | ((start) << 16))
-
-typedef struct {
-    struct {
-        uint8_t start, end; /* the start and end index of phy i2c master command memory */
-        uint8_t host_id;    /* phy i2c master host id */
-    } config[2];
-} phy_i2c_master_command_attribute_t;
-
 typedef struct sleep_modem_config {
     struct {
         void    *phy_link;
@@ -174,76 +146,15 @@ typedef struct sleep_modem_config {
 
 static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 };
 
+
 esp_err_t sleep_modem_wifi_modem_state_init(void)
 {
     esp_err_t err = ESP_OK;
-    phy_i2c_master_command_attribute_t cmd;
-
-    /* get RF on or off configuration info of i2c master command memory */
-    extern void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *);
-    phy_i2c_master_mem_cfg(&cmd);
-
-    ESP_LOGD(TAG, "Modem link i2c master configuration: (%d,%d,%d), (%d,%d,%d)", cmd.config[0].host_id, cmd.config[0].start,
-            cmd.config[0].end, cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-
-    static regdma_link_config_t wifi_modem_config[] = {
-        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
-        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
-
-        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
-        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
-
-        /* PMU or software to trigger enable RF PHY */
-        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
-        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
-        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
-        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
-        [8]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
-        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
-        [10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
-        [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
-        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
-        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
-
-        /* PMU to trigger enable RXBLOCK */
-        [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
-
-        /* PMU or software to trigger disable RF PHY */
-        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
-        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
-        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
-        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
-        [19] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x11), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
-        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
-        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
-        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
-
-        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
-
-        /* PMU to trigger disable RXBLOCK */
-        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
-        [26] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-
-        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
-        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
-    };
-    wifi_modem_config[7].write_wait.value  = I2C_BURST_VAL(cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-    wifi_modem_config[18].write_wait.value = I2C_BURST_VAL(cmd.config[0].host_id, cmd.config[0].start, cmd.config[0].end);
 
     void *link = NULL;
     if (s_sleep_modem.wifi.phy_link == NULL) {
-        for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
-            void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
-            if (next) {
-                link = next;
-            } else {
-                regdma_link_destroy(link, 0);
-                err = ESP_ERR_NO_MEM;
-            }
-        }
+        err = sleep_modem_state_phy_link_init(&link);
         if (err == ESP_OK) {
-            pau_regdma_set_modem_link_addr(link);
             s_sleep_modem.wifi.phy_link = link;
             s_sleep_modem.wifi.flags = 0;
         }
@@ -254,7 +165,7 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
 __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
 {
     if (s_sleep_modem.wifi.phy_link) {
-        regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0);
+        sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link);
         s_sleep_modem.wifi.phy_link = NULL;
         s_sleep_modem.wifi.flags = 0;
     }

components/esp_hw_support/sleep_modes.c

@@ -157,8 +157,8 @@
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
 #elif CONFIG_IDF_TARGET_ESP32C61
-#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
-#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (1148) //TODO: PM-231
+#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (107)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
@@ -189,8 +189,12 @@
 #endif
 
 #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+#if CONFIG_IDF_TARGET_ESP32C61
+#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US  (1232)
+#elif CONFIG_IDF_TARGET_ESP32C5
 #define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US  (1220)
 #endif
+#endif
 
 // Minimal amount of time we can sleep for
 #define LIGHT_SLEEP_MIN_TIME_US     200
@@ -705,7 +709,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
 #endif
-#if !CONFIG_IDF_TARGET_ESP32C61
+#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9304
     sar_periph_ctrl_power_enable();
 #endif
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
@@ -2359,7 +2363,7 @@ static uint32_t get_power_down_flags(void)
     }
 #endif
 #if SOC_PM_SUPPORT_RC32K_PD
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
     if (s_config.domain[ESP_PD_DOMAIN_RC32K].pd_option != ESP_PD_OPTION_ON) {
         pd_flags |= PMU_SLEEP_PD_RC32K;
     }

components/esp_lcd/test_apps/.build-test-rules.yml

@@ -52,7 +52,3 @@ components/esp_lcd/test_apps/spi_lcd:
     - esp_driver_spi
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: test failed # TODO: ESP32C61 IDF-10953

components/esp_lcd/test_apps/spi_lcd/main/test_spi_board.h

@@ -28,6 +28,13 @@ extern "C" {
 #define TEST_LCD_DC_GPIO        1
 #define TEST_LCD_PCLK_GPIO      2
 #define TEST_LCD_DATA0_GPIO     4
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define TEST_LCD_BK_LIGHT_GPIO  3
+#define TEST_LCD_RST_GPIO       5
+#define TEST_LCD_CS_GPIO        0
+#define TEST_LCD_DC_GPIO        1
+#define TEST_LCD_PCLK_GPIO      2
+#define TEST_LCD_DATA0_GPIO     4
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TEST_LCD_BK_LIGHT_GPIO  23
 #define TEST_LCD_RST_GPIO       6

components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py

@@ -5,7 +5,6 @@ from pytest_embedded import Dut
 
 
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail')    # TODO: [ESP32C61] IDF-10953
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',

components/esp_phy/include/esp_private/phy.h

@@ -13,17 +13,12 @@ extern "C" {
 
 #define ESP_CAL_DATA_CHECK_FAIL 1
 
-typedef enum {
-    PHY_I2C_MST_CMD_TYPE_OFF = 0,
-    PHY_I2C_MST_CMD_TYPE_ON,
-    PHY_I2C_MST_CMD_TYPE_MAX
-} phy_i2c_master_command_type_t;
-
 typedef struct {
+    uint8_t cmd_type;   /* the command type of the current phy i2c master command memory config */
     struct {
         uint8_t start, end; /* the start and end index of phy i2c master command memory */
         uint8_t host_id;    /* phy i2c master host id */
-    } config[PHY_I2C_MST_CMD_TYPE_MAX];
+    } config;
 } phy_i2c_master_command_attribute_t;
 
 /**
@@ -88,13 +83,14 @@ void phy_xpd_tsens(void);
 void phy_init_flag(void);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C6
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
 /**
  * @brief Get the configuration info of PHY i2c master command memory.
  *
- * @param   attr the configuration info of PHY i2c master command memory
+ * @param[out] attr  the configuration info of PHY i2c master command memory
+ * @param[out] size  the count of PHY i2c master command memory configuration
  */
-void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *attr);
+void phy_i2c_master_command_mem_cfg(phy_i2c_master_command_attribute_t *attr, int *size);
 #endif
 
 /**
@@ -217,6 +213,23 @@ void phy_ant_clr_update_flag(void);
  */
 void phy_ant_update(void);
 
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+/**
+ * @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode
+ *
+ * @return  the BBPLL REGDMA configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+
+/**
+ * @brief Get the REGDMA config value of the RF PHY on or off in analog i2c master burst mode
+ *
+ * @param[in] on true for enable RF PHY, false for disable RF PHY.
+ *
+ * @return  the RF on or off configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+#endif
 
 #ifdef __cplusplus
 }

components/esp_phy/lib

@@ -1 +1 @@
-Subproject commit 8608fcf54d51e81f2e74ebf335fa33f61953f7c8
+Subproject commit 1f551c5367daa87a29e0c4f724d6cf809a1841ad

components/esp_phy/src/phy_common.c

@@ -294,3 +294,57 @@ esp_err_t esp_phy_get_ant(esp_phy_ant_config_t *config)
     memcpy(config, &s_phy_ant_config, sizeof(esp_phy_ant_config_t));
     return ESP_OK;
 }
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+typedef enum {
+    PHY_I2C_MST_CMD_TYPE_RF_OFF = 0,
+    PHY_I2C_MST_CMD_TYPE_RF_ON,
+    PHY_I2C_MST_CMD_TYPE_BBPLL_CFG,
+    PHY_I2C_MST_CMD_TYPE_MAX
+} phy_i2c_master_command_type_t;
+
+static uint32_t phy_ana_i2c_master_burst_config(phy_i2c_master_command_attribute_t *attr, int size, phy_i2c_master_command_type_t type)
+{
+    #define I2C1_BURST_VAL(en, start, end) (((en) << 31) | ((end) << 22) | ((start) << 16))
+    #define I2C0_BURST_VAL(en, start, end) (((en) << 15) | ((end) <<  6) | ((start) <<  0))
+
+    uint32_t brust = 0;
+    for (int i = 0; i < size; i++) {
+        if (attr[i].config.start == 0xff || attr[i].config.end == 0xff) /* ignore invalid configure */
+            continue;
+
+        if (attr[i].cmd_type == type) {
+            if (attr[i].config.host_id) {
+                brust |= I2C1_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
+            } else {
+                brust |= I2C0_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
+            }
+        }
+    }
+    return brust;
+}
+
+uint32_t phy_ana_i2c_master_burst_bbpll_config(void)
+{
+    /* PHY supports 2 I2C masters, and the maximum number of configurations
+     * supported by the I2C master command memory is the command type
+     * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
+    phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
+    int size = sizeof(cmd) / sizeof(cmd[0]);
+    phy_i2c_master_command_mem_cfg(cmd, &size);
+
+    return phy_ana_i2c_master_burst_config(cmd, size, PHY_I2C_MST_CMD_TYPE_BBPLL_CFG);
+}
+
+uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on)
+{
+    /* PHY supports 2 I2C masters, and the maximum number of configurations
+     * supported by the I2C master command memory is the command type
+     * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
+    phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
+    int size = sizeof(cmd) / sizeof(cmd[0]);
+    phy_i2c_master_command_mem_cfg(cmd, &size);
+
+    return phy_ana_i2c_master_burst_config(cmd, size, on ? PHY_I2C_MST_CMD_TYPE_RF_ON : PHY_I2C_MST_CMD_TYPE_RF_OFF);
+}
+#endif

components/esp_phy/src/phy_init.c

@@ -45,7 +45,7 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
+#elif SOC_PM_SUPPORT_PMU_MODEM_STATE
 #include "esp_private/sleep_modem.h"
 #endif
 #include "hal/efuse_hal.h"
@@ -383,7 +383,7 @@ void esp_phy_modem_init(void)
         s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
     }
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     sleep_modem_wifi_modem_state_init();
 #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     _lock_release(&s_phy_access_lock);
@@ -408,7 +408,7 @@ void esp_phy_modem_deinit(void)
         phy_init_flag();
 #endif // CONFIG_IDF_TARGET_ESP32C3
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
         sleep_modem_wifi_modem_state_deinit();
 #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     }
@@ -431,7 +431,12 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14,  0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53,  0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58,  0, 0), .owner = BIT(0) | BIT(1) }  /* FE COEX */
+        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58,  0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG
+        [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39,  0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
+        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41,  0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
+        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87,  0, 0), .owner = BIT(0) | BIT(1) }  /* FE CTRL */
+#endif
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");

components/esp_ringbuf/test_apps/pytest_esp_ringbuf.py

@@ -5,9 +5,10 @@ from pytest_embedded import Dut
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
-@pytest.mark.esp32c3
-@pytest.mark.esp32s2
+@pytest.mark.parametrize('target', [
+    'esp32',
+    'esp32s2',
+])
 @pytest.mark.parametrize('config', [
     'default',
     'ringbuf_flash',

components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld

@@ -35,18 +35,18 @@ ic_ebuf_alloc = 0x40000b4c;
 ic_reset_extra_softap_rx_ba = 0x40000b50;
 ieee80211_align_eb = 0x40000b54;
 ieee80211_ampdu_reorder = 0x40000b58;
-ieee80211_ampdu_start_age_timer = 0x40000b5c;
-ieee80211_encap_esfbuf = 0x40000b60;
+/*ieee80211_ampdu_start_age_timer = 0x40000b5c;*/
+/*ieee80211_encap_esfbuf = 0x40000b60;*/
 ieee80211_is_tx_allowed = 0x40000b64;
-ieee80211_output_pending_eb = 0x40000b68;
-ieee80211_output_process = 0x40000b6c;
+/*ieee80211_output_pending_eb = 0x40000b68;*/
+/*ieee80211_output_process = 0x40000b6c;*/
 /*ieee80211_set_tx_desc = 0x40000b70;*/
 ieee80211_classify = 0x40000b74;
 ieee80211_copy_eb_header = 0x40000b78;
 ieee80211_recycle_cache_eb = 0x40000b7c;
 ieee80211_search_node = 0x40000b80;
-ieee80211_crypto_encap = 0x40000b84;
-ieee80211_crypto_decap = 0x40000b88;
+/*ieee80211_crypto_encap = 0x40000b84;*/
+/*ieee80211_crypto_decap = 0x40000b88;*/
 ieee80211_decap = 0x40000b8c;
 ieee80211_set_tx_pti = 0x40000b90;
 ieee80211_gettid = 0x40000b94;
@@ -61,12 +61,12 @@ ieee80211_find_ie = 0x40000bb4;
 ieee80211_find_ext_ie = 0x40000bb8;
 ieee80211_merge_mbssid_profile = 0x40000bbc;
 ieee80211_encap_esfbuf_htc = 0x40000bc0;
-wifi_get_macaddr = 0x40000bc4;
-wifi_rf_phy_disable = 0x40000bc8;
-wifi_rf_phy_enable = 0x40000bcc;
-wifi_is_started = 0x40000bd0;
+/*wifi_get_macaddr = 0x40000bc4;*/
+/*wifi_rf_phy_disable = 0x40000bc8;*/
+/*wifi_rf_phy_enable = 0x40000bcc;*/
+/*wifi_is_started = 0x40000bd0;*/
 /*sta_input = 0x40000bd4;*/
-sta_rx_eapol = 0x40000bd8;
+/*sta_rx_eapol = 0x40000bd8;*/
 sta_reset_beacon_timeout = 0x40000bdc;
 sta_get_beacon_timeout = 0x40000be0;
 ampdu_process_multicast_address_qos_frame = 0x40000be4;

components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld

@@ -55,7 +55,7 @@ dbg_hal_check_clr_mplen_bitmap = 0x40000c6c;
 dbg_hal_check_set_mplen_bitmap = 0x40000c70;
 ic_get_trc = 0x40000c74;
 ic_mac_deinit = 0x40000c78;
-ic_mac_init = 0x40000c7c;
+/* ic_mac_init = 0x40000c7c; */
 ic_interface_enabled = 0x40000c80;
 is_lmac_idle = 0x40000c84;
 ic_get_he_rts_threshold_bytes = 0x40000c88;

components/esp_rom/patches/esp_rom_tlsf.c

@@ -20,91 +20,12 @@
 #include "esp_rom_caps.h"
 #include "esp_rom_tlsf.h"
 
-/*!
- * @brief Opaque types for TLSF implementation
- */
+#include "tlsf_block_functions.h"
+#include "tlsf_control_functions.h"
+
+/* Definition of types used in TLSF */
 typedef void* tlsf_t;
 typedef void* pool_t;
-typedef ptrdiff_t tlsfptr_t;
-
-/* ----------------------------------------------------------------
- * Bring certain inline functions, macro and structures from the
- * tlsf ROM implementation to be able to compile the patch.
- * ---------------------------------------------------------------- */
-
-#if !defined (tlsf_assert)
-#define tlsf_assert assert
-#endif
-
-#define tlsf_cast(t, exp)	((t) (exp))
-
-#define block_header_free_bit  (1 << 0)
-#define block_header_prev_free_bit  (1 << 1)
-#define block_header_overhead  (sizeof(size_t))
-#define block_start_offset (offsetof(block_header_t, size) + sizeof(size_t))
-
-typedef struct block_header_t
-{
-    /* Points to the previous physical block. */
-    struct block_header_t* prev_phys_block;
-
-    /* The size of this block, excluding the block header. */
-    size_t size;
-
-    /* Next and previous free blocks. */
-    struct block_header_t* next_free;
-    struct block_header_t* prev_free;
-} block_header_t;
-
-static inline __attribute__((__always_inline__)) size_t block_size(const block_header_t* block)
-{
-    return block->size & ~(block_header_free_bit | block_header_prev_free_bit);
-}
-
-static inline __attribute__((__always_inline__)) int block_is_free(const block_header_t* block)
-{
-    return tlsf_cast(int, block->size & block_header_free_bit);
-}
-
-static inline __attribute__((__always_inline__)) int block_is_prev_free(const block_header_t* block)
-{
-    return tlsf_cast(int, block->size & block_header_prev_free_bit);
-}
-
-static inline __attribute__((always_inline)) block_header_t* block_from_ptr(const void* ptr)
-{
-	return tlsf_cast(block_header_t*,
-		tlsf_cast(unsigned char*, ptr) - block_start_offset);
-}
-
-static inline __attribute__((always_inline)) block_header_t* offset_to_block(const void* ptr, size_t size)
-{
-	return tlsf_cast(block_header_t*, tlsf_cast(tlsfptr_t, ptr) + size);
-}
-
-static inline __attribute__((always_inline)) int block_is_last(const block_header_t* block)
-{
-	return block_size(block) == 0;
-}
-
-static inline __attribute__((always_inline)) void* block_to_ptr(const block_header_t* block)
-{
-	return tlsf_cast(void*,
-		tlsf_cast(unsigned char*, block) + block_start_offset);
-}
-
-static inline __attribute__((always_inline)) block_header_t* block_next(const block_header_t* block)
-{
-	block_header_t* next = offset_to_block(block_to_ptr(block),
-		block_size(block) - block_header_overhead);
-	tlsf_assert(!block_is_last(block));
-	return next;
-}
-
-/* ----------------------------------------------------------------
- * End of the environment necessary to compile and link the patch
- * defined below
- * ---------------------------------------------------------------- */
 
 static poison_check_pfunc_t s_poison_check_region = NULL;
 
@@ -237,6 +158,7 @@ struct heap_tlsf_stub_table_t {
 extern struct heap_tlsf_stub_table_t* heap_tlsf_table_ptr;
 
 /* We will copy the ROM table and modify the functions we patch */
+
 struct heap_tlsf_stub_table_t heap_tlsf_patch_table_ptr;
 
 /*!

components/esp_security/src/esp_crypto_lock.c

@@ -33,10 +33,10 @@ static _lock_t s_crypto_hmac_lock;
 static _lock_t s_crypto_mpi_lock;
 #endif /* SOC_MPI_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 /* Single lock for SHA and AES, sharing a reserved GDMA channel */
 static _lock_t s_crypto_sha_aes_lock;
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
 #ifdef SOC_ECC_SUPPORTED
 /* Lock for ECC peripheral */
@@ -83,7 +83,7 @@ void esp_crypto_ds_lock_release(void)
 }
 #endif /* SOC_DIG_SIGN_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 void esp_crypto_sha_aes_lock_acquire(void)
 {
     _lock_acquire(&s_crypto_sha_aes_lock);
@@ -93,9 +93,9 @@ void esp_crypto_sha_aes_lock_release(void)
 {
     _lock_release(&s_crypto_sha_aes_lock);
 }
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
-#if defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA)
+#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
 void esp_crypto_dma_lock_acquire(void)
 {
     _lock_acquire(&s_crypto_sha_aes_lock);
@@ -105,7 +105,7 @@ void esp_crypto_dma_lock_release(void)
 {
     _lock_release(&s_crypto_sha_aes_lock);
 }
-#endif /* defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA) */
+#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
 
 #ifdef SOC_MPI_SUPPORTED
 void esp_crypto_mpi_lock_acquire(void)

components/esp_system/port/cpu_start.c

@@ -751,7 +751,7 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif
 #endif
 
-#if SOC_DEEP_SLEEP_SUPPORTED //TODO: IDF-9245
+#if SOC_DEEP_SLEEP_SUPPORTED
     // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
     if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
         esp_deep_sleep_wakeup_io_reset();

components/esp_system/port/soc/esp32c5/clk.c

@@ -56,8 +56,14 @@ __attribute__((weak)) void esp_clk_init(void)
     assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M));
 
     rtc_clk_8m_enable(true);
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
     rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+    rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
+#else
+#error "No RTC fast clock source configured"
 #endif
+#endif //!CONFIG_IDF_ENV_FPGA
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.

components/esp_system/port/soc/esp32p4/clk.c

@@ -86,7 +86,13 @@ __attribute__((weak)) void esp_clk_init(void)
     assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
 
     rtc_clk_8m_enable(true);
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
     rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+    rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
+#else
+#error "No RTC fast clock source configured"
+#endif
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.

components/esp_system/system_init_fn.txt

@@ -82,10 +82,12 @@ SECONDARY: 103: esp_security_init in components/esp_security/src/init.c on BIT(0
 SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0)
 SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c on BIT(0)
 SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c on BIT(0)
+SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c on BIT(0)
 SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c on BIT(0)
 SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0)
 SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0)
 SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c on BIT(0)
+SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c on BIT(0)
 
 # app_trace has to be initialized before systemview
 SECONDARY: 115: esp_apptrace_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES

components/esp_wifi/Kconfig

@@ -657,28 +657,28 @@ menu "Wi-Fi"
 
         config ESP_WIFI_ENABLE_DUMP_HESIGB
             bool "Enable Wi-Fi dump HE-SIGB which is contained in DL HE MU PPDUs"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump HE-SIGB which is contained in DL HE MU PPDUs.
 
         config ESP_WIFI_ENABLE_DUMP_MU_CFO
             bool "Enable Wi-Fi dump MU CFO"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump MU CFO.
 
         config ESP_WIFI_ENABLE_DUMP_CTRL_NDPA
             bool "Enable Wi-Fi dump NDPA frames"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump NDPA frames.
 
         config ESP_WIFI_ENABLE_DUMP_CTRL_BFRP
             bool "Enable Wi-Fi dump BFRP frames"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump BFRP frames.

components/esp_wifi/include/esp_wifi.h

@@ -677,7 +677,7 @@ esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
   * @brief     Set protocol type of specified interface
   *            The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N).
   *            if CONFIG_SOC_WIFI_HE_SUPPORT and band mode is 2.4G, the default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AX).
-  *            if CONFIG_SOC_WIFI_HE_SUPPORT_5G and band mode is 5G, the default protocol is (WIFI_PROTOCOL_11A|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AC|WIFI_PROTOCOL_11AX).
+  *            if CONFIG_SOC_WIFI_SUPPORT_5G and band mode is 5G, the default protocol is (WIFI_PROTOCOL_11A|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AC|WIFI_PROTOCOL_11AX).
   *
   * @attention 1. When WiFi band mode is 2.4G only, support 802.11b or 802.11bg or 802.11bgn or 802.11bgnax or LR mode
   * @attention 2. When WiFi band mode is 5G only, support 802.11a or 802.11an or 802.11anac or 802.11anacax
@@ -1653,8 +1653,8 @@ esp_err_t esp_wifi_get_band(wifi_band_t* band);
   * @attention 1. When the WiFi band mode is set to 2.4G only, it operates exclusively on the 2.4GHz channels.
   * @attention 2. When the WiFi band mode is set to 5G only, it operates exclusively on the 5GHz channels.
   * @attention 3. When the WiFi band mode is set to 2.4G + 5G (WIFI_BAND_MODE_AUTO), it can operate on both the 2.4GHz and 5GHz channels.
-  * @attention 4. WiFi band mode can be set to 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO) if CONFIG_SOC_WIFI_HE_SUPPORT_5G is supported.
-  * @attention 5. If CONFIG_SOC_WIFI_HE_SUPPORT_5G is not supported, the API will return ESP_ERR_INVALID_ARG when the band mode is set to either 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO).
+  * @attention 4. WiFi band mode can be set to 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO) if CONFIG_SOC_WIFI_SUPPORT_5G is supported.
+  * @attention 5. If CONFIG_SOC_WIFI_SUPPORT_5G is not supported, the API will return ESP_ERR_INVALID_ARG when the band mode is set to either 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO).
   * @attention 6. When a WiFi band mode change triggers a band change, if no channel is set for the current band, a default channel will be assigned: channel 1 for 2.4G band and channel 36 for 5G band.
   *
   * @param[in]    band_mode store the band mode of WiFi
@@ -1717,7 +1717,7 @@ esp_err_t esp_wifi_set_protocols(wifi_interface_t ifx, wifi_protocols_t *protoco
 /**
   * @brief     Get the current protocol of the specified interface and specified band
   *
-  * @attention 1. The 5G protocol can only be read when CONFIG_SOC_WIFI_HE_SUPPORT_5G is enabled.
+  * @attention 1. The 5G protocol can only be read when CONFIG_SOC_WIFI_SUPPORT_5G is enabled.
   * @attention 2. When the WiFi band mode is set to 2.4G only, it will not get 5G protocol
   * @attention 3. When the WiFi band mode is set to 5G only, it will not get 2.4G protocol
   *
@@ -1756,7 +1756,7 @@ esp_err_t esp_wifi_set_bandwidths(wifi_interface_t ifx, wifi_bandwidths_t* bw);
 /**
   * @brief     Get the bandwidth of specified interface and specified band
   *
-  * @attention 1. The 5G bandwidth can only be read when CONFIG_SOC_WIFI_HE_SUPPORT_5G is enabled.
+  * @attention 1. The 5G bandwidth can only be read when CONFIG_SOC_WIFI_SUPPORT_5G is enabled.
   * @attention 2. When the WiFi band mode is set to 2.4G only, it will not get 5G bandwidth
   * @attention 3. When the WiFi band mode is set to 5G only, it will not get 2.4G bandwidth
   *

components/esp_wifi/include/esp_wifi_types_generic.h

@@ -49,10 +49,16 @@ typedef enum {
 /** @brief Structure describing WiFi country-based regional restrictions. */
 typedef struct {
     char                  cc[3];   /**< country code string */
-    uint8_t               schan;   /**< start channel */
-    uint8_t               nchan;   /**< total channel number */
+    uint8_t               schan;   /**< start channel of the allowed 2.4GHz WiFi channels */
+    uint8_t               nchan;   /**< total channel number of the allowed 2.4GHz WiFi channels */
     int8_t                max_tx_power;   /**< This field is used for getting WiFi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
     wifi_country_policy_t policy;  /**< country policy */
+#if SOC_WIFI_SUPPORT_5G
+    uint32_t              wifi_5g_channel_mask;  /**< A bitmask representing the allowed 5GHz WiFi channels.
+                                                      Each bit in the mask corresponds to a specific channel as wifi_5g_channel_bit_t shown.
+                                                      Bitmask set to 0 indicates 5GHz channels are allowed according to local regulatory rules.
+                                                      Please note that configured bitmask takes effect only when policy is manual. */
+#endif
 } wifi_country_t;
 
 /* Strength of authmodes */
@@ -178,8 +184,8 @@ typedef struct {
 } wifi_scan_time_t;
 
 typedef struct {
-    uint16_t ghz_2_channels;     /**< Represents 2.4 GHz channels */
-    uint32_t ghz_5_channels;     /**< Represents 5 GHz channels */
+    uint16_t ghz_2_channels;     /**< Represents 2.4 GHz channels, that bits can be set as wifi_2g_channel_bit_t shown. */
+    uint32_t ghz_5_channels;     /**< Represents 5 GHz channels, that bits can be set as wifi_5g_channel_bit_t shown. */
 } wifi_scan_channel_bitmap_t;
 
 /** @brief Parameters for an SSID scan. */
@@ -191,7 +197,9 @@ typedef struct {
     wifi_scan_type_t scan_type;                        /**< scan type, active or passive */
     wifi_scan_time_t scan_time;                        /**< scan time per channel */
     uint8_t home_chan_dwell_time;                      /**< time spent at home channel between scanning consecutive channels. */
-    wifi_scan_channel_bitmap_t channel_bitmap;         /**< Channel bitmap for setting specific channels to be scanned. For 2.4ghz channels set ghz_2_channels from BIT(1) to BIT(14) from LSB to MSB order to indicate channels to be scanned. Currently scanning in 5ghz channels is not supported. Please note that the 'channel' parameter above needs to be set to 0 to allow scanning by bitmap. */
+    wifi_scan_channel_bitmap_t channel_bitmap;         /**< Channel bitmap for setting specific channels to be scanned.
+                                                            Please note that the 'channel' parameter above needs to be set to 0 to allow scanning by bitmap.
+                                                            Also, note that only allowed channels configured by wifi_country_t can be scaned. */
 } wifi_scan_config_t;
 
 /** @brief Parameters default scan configurations. */
@@ -305,6 +313,72 @@ typedef enum {
     WIFI_BAND_MODE_AUTO = 3,            /* WiFi band mode is 2.4G + 5G */
 } wifi_band_mode_t;
 
+#ifndef BIT
+#define BIT(nr)  (1 << (nr))
+#endif
+
+#define CHANNEL_TO_BIT_NUMBER(channel) ((channel >= 1 && channel <= 14) ? (channel) : \
+    ((channel >= 36 && channel <= 64 && (channel - 36) % 4 == 0) ? ((channel - 36) / 4 + 1) : \
+    ((channel >= 100 && channel <= 144 && (channel - 100) % 4 == 0) ? ((channel - 100) / 4 + 9) : \
+    ((channel >= 149 && channel <= 177 && (channel - 149) % 4 == 0) ? ((channel - 149) / 4 + 21) : 0))))
+
+#define BIT_NUMBER_TO_CHANNEL(bit_number, band) ((band == WIFI_BAND_2G) ? (bit_number) : \
+    ((bit_number >= 1 && bit_number <= 8) ? ((bit_number - 1) * 4 + 36) : \
+    ((bit_number >= 9 && bit_number <= 20) ? ((bit_number - 9) * 4 + 100) : \
+    ((bit_number >= 21 && bit_number <= 28) ? ((bit_number - 21) * 4 + 149) : 0))))
+
+#define CHANNEL_TO_BIT(channel) (BIT(CHANNEL_TO_BIT_NUMBER(channel)))
+
+/** Argument structure for 2.4G channels */
+typedef enum {
+    WIFI_CHANNEL_1 = BIT(1),   /**< wifi channel 1 */
+    WIFI_CHANNEL_2 = BIT(2),   /**< wifi channel 2 */
+    WIFI_CHANNEL_3 = BIT(3),   /**< wifi channel 3 */
+    WIFI_CHANNEL_4 = BIT(4),   /**< wifi channel 4 */
+    WIFI_CHANNEL_5 = BIT(5),   /**< wifi channel 5 */
+    WIFI_CHANNEL_6 = BIT(6),   /**< wifi channel 6 */
+    WIFI_CHANNEL_7 = BIT(7),   /**< wifi channel 7 */
+    WIFI_CHANNEL_8 = BIT(8),   /**< wifi channel 8 */
+    WIFI_CHANNEL_9 = BIT(9),   /**< wifi channel 9 */
+    WIFI_CHANNEL_10 = BIT(10), /**< wifi channel 10 */
+    WIFI_CHANNEL_11 = BIT(11), /**< wifi channel 11 */
+    WIFI_CHANNEL_12 = BIT(12), /**< wifi channel 12 */
+    WIFI_CHANNEL_13 = BIT(13), /**< wifi channel 13 */
+    WIFI_CHANNEL_14 = BIT(14), /**< wifi channel 14 */
+} wifi_2g_channel_bit_t;
+
+/** Argument structure for 5G channels */
+typedef enum {
+    WIFI_CHANNEL_36 = BIT(1),   /**< wifi channel 36 */
+    WIFI_CHANNEL_40 = BIT(2),   /**< wifi channel 40 */
+    WIFI_CHANNEL_44 = BIT(3),   /**< wifi channel 44 */
+    WIFI_CHANNEL_48 = BIT(4),   /**< wifi channel 48 */
+    WIFI_CHANNEL_52 = BIT(5),   /**< wifi channel 52 */
+    WIFI_CHANNEL_56 = BIT(6),   /**< wifi channel 56 */
+    WIFI_CHANNEL_60 = BIT(7),   /**< wifi channel 60 */
+    WIFI_CHANNEL_64 = BIT(8),   /**< wifi channel 64 */
+    WIFI_CHANNEL_100 = BIT(9),  /**< wifi channel 100 */
+    WIFI_CHANNEL_104 = BIT(10), /**< wifi channel 104 */
+    WIFI_CHANNEL_108 = BIT(11), /**< wifi channel 108 */
+    WIFI_CHANNEL_112 = BIT(12), /**< wifi channel 112 */
+    WIFI_CHANNEL_116 = BIT(13), /**< wifi channel 116 */
+    WIFI_CHANNEL_120 = BIT(14), /**< wifi channel 120 */
+    WIFI_CHANNEL_124 = BIT(15), /**< wifi channel 124 */
+    WIFI_CHANNEL_128 = BIT(16), /**< wifi channel 128 */
+    WIFI_CHANNEL_132 = BIT(17), /**< wifi channel 132 */
+    WIFI_CHANNEL_136 = BIT(18), /**< wifi channel 136 */
+    WIFI_CHANNEL_140 = BIT(19), /**< wifi channel 140 */
+    WIFI_CHANNEL_144 = BIT(20), /**< wifi channel 144 */
+    WIFI_CHANNEL_149 = BIT(21), /**< wifi channel 149 */
+    WIFI_CHANNEL_153 = BIT(22), /**< wifi channel 153 */
+    WIFI_CHANNEL_157 = BIT(23), /**< wifi channel 157 */
+    WIFI_CHANNEL_161 = BIT(24), /**< wifi channel 161 */
+    WIFI_CHANNEL_165 = BIT(25), /**< wifi channel 165 */
+    WIFI_CHANNEL_169 = BIT(26), /**< wifi channel 169 */
+    WIFI_CHANNEL_173 = BIT(27), /**< wifi channel 173 */
+    WIFI_CHANNEL_177 = BIT(28), /**< wifi channel 177 */
+} wifi_5g_channel_bit_t;
+
 #define WIFI_PROTOCOL_11B         0x1
 #define WIFI_PROTOCOL_11G         0x2
 #define WIFI_PROTOCOL_11N         0x4

components/esp_wifi/lib

@@ -1 +1 @@
-Subproject commit efa80057b04ade8b1412a0dedcb5572d6ccd1fcc
+Subproject commit ad8411567dc96a9d7fd13d275e6657c223287388

components/esptool_py/Kconfig.projbuild

@@ -4,7 +4,7 @@ menu "Serial flasher config"
     config ESPTOOLPY_NO_STUB
         bool "Disable download stub"
         default y if IDF_ENV_FPGA || IDF_ENV_BRINGUP
-        default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 # TODO: IDF-8631, IDF-9241 to be removed
+        default y if IDF_TARGET_ESP32C61 # TODO: IDF-9241 to be removed
         default n
 
         help

components/freertos/esp_additions/idf_additions.c

@@ -81,15 +81,44 @@ err:
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
+    static void prvTaskDeleteWithCaps( TaskHandle_t xTaskToDelete )
+    {
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
+        StaticTask_t * pxTaskBuffer;
+        StackType_t * puxStackBuffer;
+
+        /* The task to be deleted must not be running.
+         * So we suspend the task before deleting it. */
+        vTaskSuspend( xTaskToDelete );
+
+        /* Wait for the task to be suspended */
+        while( eRunning == eTaskGetState( xTaskToDelete ) )
+        {
+            taskYIELD();
+        }
+
+        configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
+
+        xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
+        configASSERT( xResult == pdTRUE );
+        configASSERT( puxStackBuffer != NULL );
+        configASSERT( pxTaskBuffer != NULL );
+
+        /* We can delete the task and free the memory buffers. */
+        vTaskDelete( xTaskToDelete );
+
+        /* Free the memory buffers */
+        heap_caps_free( puxStackBuffer );
+        vPortFree( pxTaskBuffer );
+    }
+
     static void prvTaskDeleteWithCapsTask( void * pvParameters )
     {
         TaskHandle_t xTaskToDelete = ( TaskHandle_t ) pvParameters;
 
-        /* The task to be deleted must not be running */
-        configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
-
         /* Delete the WithCaps task */
-        vTaskDeleteWithCaps( xTaskToDelete );
+        prvTaskDeleteWithCaps( xTaskToDelete );
 
         /* Delete the temporary clean up task */
         vTaskDelete( NULL );
@@ -98,7 +127,7 @@ err:
     void vTaskDeleteWithCaps( TaskHandle_t xTaskToDelete )
     {
         /* THIS FUNCTION SHOULD NOT BE CALLED FROM AN INTERRUPT CONTEXT. */
-        /*TODO: Update it to use portASSERT_IF_IN_ISR() instead. (IDF-10540) */
+        /* TODO: Update it to use portASSERT_IF_IN_ISR() instead. (IDF-10540) */
         vPortAssertIfInISR();
 
         TaskHandle_t xCurrentTaskHandle = xTaskGetCurrentTaskHandle();
@@ -151,60 +180,8 @@ err:
             }
         }
 
-        #if ( configNUM_CORES > 1 )
-            else if( eRunning == eTaskGetState( xTaskToDelete ) )
-            {
-                /* The WithCaps task is running on another core.
-                 * We suspend the task first and then delete it. */
-                vTaskSuspend( xTaskToDelete );
-
-                /* Wait for the task to be suspended */
-                while( eRunning == eTaskGetState( xTaskToDelete ) )
-                {
-                    portYIELD_WITHIN_API();
-                }
-
-                // Return value unused if asserts are disabled
-                BaseType_t __attribute__((unused)) xResult;
-                StaticTask_t * pxTaskBuffer;
-                StackType_t * puxStackBuffer;
-
-                xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
-                configASSERT( xResult == pdTRUE );
-                configASSERT( puxStackBuffer != NULL );
-                configASSERT( pxTaskBuffer != NULL );
-
-                /* Delete the task */
-                vTaskDelete( xTaskToDelete );
-
-                /* Free the memory buffers */
-                heap_caps_free( puxStackBuffer );
-                vPortFree( pxTaskBuffer );
-            }
-        #endif /* if ( configNUM_CORES > 1 ) */
-        else
-        {
-            /* The WithCaps task is not running and is being deleted
-             * from another task's context. */
-            configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
-
-            // Return value unused if asserts are disabled
-            BaseType_t __attribute__((unused)) xResult;
-            StaticTask_t * pxTaskBuffer;
-            StackType_t * puxStackBuffer;
-
-            xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
-            configASSERT( xResult == pdTRUE );
-            configASSERT( puxStackBuffer != NULL );
-            configASSERT( pxTaskBuffer != NULL );
-
-            /* We can delete the task and free the memory buffers. */
-            vTaskDelete( xTaskToDelete );
-
-            /* Free the memory buffers */
-            heap_caps_free( puxStackBuffer );
-            vPortFree( pxTaskBuffer );
-        } /* if( ( xTaskToDelete == NULL ) || ( xTaskToDelete == xCurrentTaskHandle ) ) */
+        /* Delete the WithCaps task */
+        prvTaskDeleteWithCaps( xTaskToDelete );
     }
 
 #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
@@ -262,8 +239,8 @@ err:
 
     void vQueueDeleteWithCaps( QueueHandle_t xQueue )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticQueue_t * pxQueueBuffer;
         uint8_t * pucQueueStorageBuffer;
 
@@ -335,8 +312,8 @@ err:
 
     void vSemaphoreDeleteWithCaps( SemaphoreHandle_t xSemaphore )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticSemaphore_t * pxSemaphoreBuffer;
 
         /* Retrieve the buffer used to create the semaphore before deleting it
@@ -408,8 +385,8 @@ err:
     void vStreamBufferGenericDeleteWithCaps( StreamBufferHandle_t xStreamBuffer,
                                              BaseType_t xIsMessageBuffer )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticStreamBuffer_t * pxStaticStreamBuffer;
         uint8_t * pucStreamBufferStorageArea;
 

components/freertos/test_apps/freertos/misc/test_idf_additions.c

@@ -89,6 +89,34 @@ TEST_CASE("IDF additions: Task creation with memory caps and self deletion", "[f
     xTaskNotifyGive(task_handle);
 }
 
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+
+TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletion stress test", "[freertos]")
+{
+#define TEST_NUM_TASKS      5
+#define TEST_NUM_ITERATIONS 1000
+    TaskHandle_t task_handle[TEST_NUM_TASKS];
+    StackType_t *puxStackBuffer;
+    StaticTask_t *pxTaskBuffer;
+
+    for (int j = 0; j < TEST_NUM_ITERATIONS; j++) {
+        for (int i = 0; i < TEST_NUM_TASKS; i++) {
+            // Create a task with caps
+            TEST_ASSERT_EQUAL(pdPASS, xTaskCreateWithCaps(task_with_caps_self_delete, "task", 4096, NULL, UNITY_FREERTOS_PRIORITY, &task_handle[i], MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT));
+            TEST_ASSERT_NOT_EQUAL(NULL, task_handle);
+            // Get the task's memory
+            TEST_ASSERT_EQUAL(pdTRUE, xTaskGetStaticBuffers(task_handle[i], &puxStackBuffer, &pxTaskBuffer));
+        }
+
+        for (int i = 0; i < TEST_NUM_TASKS; i++) {
+            // Notify the task to delete itself
+            xTaskNotifyGive(task_handle[i]);
+        }
+    }
+}
+
+#endif /* CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
+
 #if ( CONFIG_FREERTOS_NUMBER_OF_CORES > 1 )
 
 static void task_with_caps_running_on_other_core(void *arg)

components/freertos/test_apps/freertos/sdkconfig.ci.psram

@@ -5,6 +5,7 @@ CONFIG_IDF_TARGET="esp32"
 # Enable SPIRAM
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_OCCUPY_NO_HOST=y
+CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
 
 # Disable encrypted flash reads/writes to save IRAM in this build configuration
 CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=n

components/hal/esp32c61/include/hal/apm_ll.h

@@ -0,0 +1,407 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/pcr_reg.h"
+#include "soc/tee_reg.h"
+#include "soc/hp_apm_reg.h"
+#include "soc/lp_apm_reg.h"
+#include "soc/interrupts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APM_LL_CTRL_EXCEPTION_ID        0x0000001FU
+#define APM_LL_CTRL_EXCEPTION_ID_S      18
+#define APM_LL_CTRL_EXCEPTION_ID_V      0x0000001FU
+#define APM_LL_CTRL_EXCEPTION_MODE      0x00000003U
+#define APM_LL_CTRL_EXCEPTION_MODE_S    16
+#define APM_LL_CTRL_EXCEPTION_MODE_V    0x00000003U
+#define APM_LL_CTRL_EXCEPTION_REGION    0x0000FFFFU
+#define APM_LL_CTRL_EXCEPTION_REGION_S  0
+#define APM_LL_CTRL_EXCEPTION_REGION_V  0x0000FFFFU
+
+#define APM_LL_HP_MAX_REGION_NUM 15
+#define APM_LL_LP_MAX_REGION_NUM 3
+#define APM_LL_MASTER_MAX        32
+
+#define  HP_APM_MAX_ACCESS_PATH  0x4
+#define  LP_APM_MAX_ACCESS_PATH  0x1
+
+#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : \
+                                    (HP_APM_REGION_FILTER_EN_REG);  \
+    })
+
+#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
+
+#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ATTR_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) :  \
+                                    (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_CTRL_M_REGION_STATUS_CLR    (BIT(0))
+#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
+#define APM_LL_SEC_MODE_REGION_ATTR_V  0x00000003U
+#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
+
+#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) :  \
+                                    (HP_APM_INT_EN_REG);  \
+    })
+
+#define APM_CTRL_CLK_EN    (BIT(0))
+#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : \
+                                    (HP_APM_CLOCK_GATE_REG);  \
+    })
+
+#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : \
+                                    (HP_APM_FUNC_CTRL_REG);  \
+    })
+
+/**
+ * @brief APM Master ID
+ */
+typedef enum {
+    APM_LL_MASTER_HPCORE       = 0,
+    APM_LL_MASTER_LPCORE       = 1,
+    APM_LL_MASTER_REGDMA       = 2,
+    APM_LL_MASTER_SDIOSLV      = 3,
+    APM_LL_MASTER_MODEM        = 4,
+    APM_LL_MASTER_MEM_MONITOR  = 5,
+    APM_LL_MASTER_TRACE        = 6,
+    APM_LL_MASTER_GDMA         = 16, // The beginning of GDMA master ID
+    APM_LL_MASTER_GDMA_SPI2    = 16,
+    APM_LL_MASTER_GDMA_UHCI0   = 18,
+    APM_LL_MASTER_GDMA_I2S0    = 19,
+    APM_LL_MASTER_GDMA_AES     = 22,
+    APM_LL_MASTER_GDMA_SHA     = 23,
+    APM_LL_MASTER_GDMA_ADC     = 24,
+    APM_LL_MASTER_GDMA_PARLIO  = 25,
+} apm_ll_master_id_t;
+
+/**
+ * @brief APM Controller
+ */
+typedef enum {
+    LP_APM_CTRL = 0,
+    HP_APM_CTRL  = 1,
+} apm_ll_apm_ctrl_t;
+
+/**
+ * @brief APM Secure Mode
+ */
+typedef enum {
+    APM_LL_SECURE_MODE_TEE  = 0, /* Trusted execution environment mode */
+    APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */
+    APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */
+    APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */
+} apm_ll_secure_mode_t;
+
+/**
+ * @brief APM Ctrl access path
+ */
+typedef enum {
+    APM_CTRL_ACCESS_PATH_M0 = 0x0,
+    APM_CTRL_ACCESS_PATH_M1 = 0x1,
+    APM_CTRL_ACCESS_PATH_M2 = 0x2,
+    APM_CTRL_ACCESS_PATH_M3 = 0x3,
+} apm_ll_ctrl_access_path_t;
+
+/**
+ * @brief APM Ctrl path.
+ */
+typedef struct {
+    apm_ll_apm_ctrl_t apm_ctrl;           /* APM Ctrl: LP APM/HP APM. */
+    apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */
+} apm_ctrl_path_t;
+
+/**
+ * @brief APM exception information
+ */
+typedef struct {
+    apm_ctrl_path_t apm_path;
+    uint8_t  excp_regn;
+    uint8_t  excp_mode;
+    uint8_t  excp_id;
+    uint8_t  excp_type;
+    uint32_t excp_addr;
+} apm_ctrl_exception_info_t;
+
+/**
+ * @brief Set secure mode
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param master_id APM master ID
+ * @param sec_mode Secure mode
+ */
+static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
+                                                     apm_ll_secure_mode_t sec_mode)
+{
+    if (apm_ctrl == HP_APM_CTRL) {
+        REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
+    }
+}
+
+/**
+ * @brief TEE controller clock auto gating enable
+ *
+ * @param enable Flag for HP clock auto gating enable/disable
+ */
+static inline void apm_tee_ll_clk_gating_enable(bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
+    } else {
+        REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
+    }
+}
+
+/**
+ * @brief enable/disable APM Ctrl Region access permission filter
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Memory Region number
+ * @param enable Flag for Region access filter enable/disable
+ */
+static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                        uint32_t regn_num, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
+    } else {
+        REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
+    }
+}
+
+/**
+ * @brief enable/disable APM Ctrl access path(M[0:n])
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access path
+ * @param enable     Flag for APM Ctrl M path filter enable/disable
+ */
+static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                 apm_ll_ctrl_access_path_t apm_m_path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
+    }
+}
+
+/**
+ * @brief APM Ctrl Region start address configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param addr     Region start address
+ */
+static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl,
+                                                            uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr);
+}
+
+/**
+ * @brief APM Ctrl Region end address configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param addr     Region end address
+ */
+static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl,
+                                                          uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr);
+}
+
+/**
+ * @brief HP Region pms attributes configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param sec_mode Secure mode of the Master
+ * @param regn_pms XWR permissions for the given secure mode and Region number
+ */
+static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl,
+                                                               uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
+{
+    uint32_t val = 0;
+    val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num));
+    val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode);
+    val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
+    REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val);
+}
+
+/**
+ * @brief Get APM Ctrl access path(M[0:n]) exception status
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access path
+ */
+static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl,
+                                                       apm_ll_ctrl_access_path_t apm_m_path)
+{
+    return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path));
+}
+
+/**
+ * @brief Clear APM Ctrl access path(M[0:n]) exception
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param amp_m_path APM Ctrl access path
+ */
+static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl,
+                                                   apm_ll_ctrl_access_path_t apm_m_path)
+{
+    REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path),
+                APM_CTRL_M_REGION_STATUS_CLR);
+}
+
+/**
+ * @brief Get APM Ctrl access path(M[0:n]) exception information
+ *
+ * @param excp_info  Exception related information like addr,
+ * region, apm_ctrl, apm_m_path, sec_mode and master id
+ */
+static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
+{
+    excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                       APM_LL_CTRL_EXCEPTION_ID);
+    excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                         APM_LL_CTRL_EXCEPTION_MODE);
+    excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                         APM_LL_CTRL_EXCEPTION_REGION);
+    excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path);
+    excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path));
+}
+
+/**
+ * @brief Interrupt enable for APM Ctrl at access path(M[0:n])
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access patch(M[0:n])
+ * @param enable     Flag for access path interrupt enable/disable
+ */
+static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                    apm_ll_ctrl_access_path_t apm_m_path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
+    }
+}
+
+/**
+ * @brief APM Ctrl clock auto gating enable
+ *
+ * @param apm_ctrl  APM Ctrl (LP_APM/HP_APM)
+ * @param enable    Flag for HP clock auto gating enable/disable
+ */
+static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
+    }
+}
+
+/**
+ * @brief APM/TEE/HP System Reg reset event bypass enable
+ *
+ * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
+ * but also some reset events.
+ * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
+ * Some reset events will be bypassed.
+ *
+ * @param enable   Flag for event bypass enable/disable
+ */
+static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
+    } else {
+        REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
+    }
+}
+
+/**
+ * @brief Fetch the APM Ctrl interrupt source number.
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM0/HP_APM/LP_APM)
+ * @param apm_m_path APM Ctrl access patch(M[0:n])
+ */
+static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path)
+{
+    switch (apm_ctrl) {
+        case HP_APM_CTRL :
+            return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path);
+        case LP_APM_CTRL :
+            return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path);
+    }
+
+    return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c61/include/hal/pau_ll.h

@@ -0,0 +1,172 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-C61 PAU(Power Assist Unit) register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/pau_reg.h"
+#include "soc/pau_struct.h"
+#include "soc/pcr_struct.h"
+#include "hal/pau_types.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void pau_ll_enable_bus_clock(bool enable)
+{
+    if (enable) {
+        PCR.regdma_conf.regdma_clk_en = 1;
+        PCR.regdma_conf.regdma_rst_en = 0;
+    } else {
+        PCR.regdma_conf.regdma_clk_en = 0;
+        PCR.regdma_conf.regdma_rst_en = 1;
+    }
+}
+
+static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
+{
+    return dev->regdma_conf.flow_err;
+}
+
+static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
+{
+    dev->regdma_conf.link_sel = link;
+}
+
+static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
+{
+    dev->regdma_conf.to_mem = to_mem ? 1 : 0;
+}
+
+static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
+{
+    dev->regdma_conf.start = 1;
+}
+
+static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
+{
+    dev->regdma_conf.start = 0;
+}
+
+static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
+{
+    dev->regdma_conf.sel_mac = 1;
+}
+
+static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
+{
+    dev->regdma_conf.sel_mac = 0;
+}
+
+static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
+{
+    dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
+}
+
+static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
+{
+    dev->regdma_conf.start_mac = 1;
+}
+
+static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
+{
+    dev->regdma_conf.start_mac = 0;
+}
+
+static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
+{
+    dev->regdma_link_0_addr.val = (uint32_t)link_addr;
+}
+
+static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
+{
+    dev->regdma_link_1_addr.val = (uint32_t)link_addr;
+}
+
+static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
+{
+    dev->regdma_link_2_addr.val = (uint32_t)link_addr;
+}
+
+static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
+{
+    dev->regdma_link_3_addr.val = (uint32_t)link_addr;
+}
+
+static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
+{
+    dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
+}
+
+static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
+{
+    return dev->regdma_current_link_addr.val;
+}
+
+static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
+{
+    return dev->regdma_backup_addr.val;
+}
+
+static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
+{
+    return dev->regdma_mem_addr.val;
+}
+
+static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
+{
+    return dev->int_raw.val;
+}
+
+static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
+{
+    return dev->int_st.val;
+}
+
+static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
+{
+    dev->int_ena.done_int_ena = 1;
+}
+
+static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
+{
+    dev->int_ena.done_int_ena = 0;
+}
+
+static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
+{
+    dev->int_ena.error_int_ena = enable;
+}
+
+static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
+{
+    dev->int_clr.done_int_clr = 1;
+}
+
+static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
+{
+    dev->int_clr.error_int_clr = 1;
+}
+
+static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
+{
+    dev->regdma_bkp_conf.link_tout_thres = count;
+}
+
+static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
+{
+    dev->regdma_bkp_conf.read_interval = interval;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c61/include/hal/sha_ll.h

@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include "soc/hwcrypto_reg.h"
+#include "soc/pcr_struct.h"
+#include "hal/sha_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Enable the bus clock for SHA peripheral module
+ *
+ * @param enable true to enable the module, false to disable the module
+ */
+static inline void sha_ll_enable_bus_clock(bool enable)
+{
+    PCR.sha_conf.sha_clk_en = enable;
+}
+
+/**
+ * @brief Reset the SHA peripheral module
+ */
+static inline void sha_ll_reset_register(void)
+{
+    PCR.sha_conf.sha_rst_en = 1;
+    PCR.sha_conf.sha_rst_en = 0;
+
+    // Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset
+    PCR.ds_conf.ds_rst_en = 0;
+    PCR.hmac_conf.hmac_rst_en = 0;
+    PCR.ecdsa_conf.ecdsa_rst_en = 0;
+}
+
+/**
+ * @brief Start a new SHA block conversions (no initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_start_block(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_START_REG, 1);
+}
+
+/**
+ * @brief Continue a SHA block conversion (initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_continue_block(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_CONTINUE_REG, 1);
+}
+
+/**
+ * @brief Start a new SHA message conversion using DMA (no initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_start_dma(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_DMA_START_REG, 1);
+}
+
+/**
+ * @brief Continue a SHA message conversion using DMA (initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_continue_dma(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
+}
+
+/**
+ * @brief Load the current hash digest to digest register
+ *
+ * @note Happens automatically on ESP32C6
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_load(esp_sha_type sha_type)
+{
+}
+
+/**
+ * @brief Sets the number of message blocks to be hashed
+ *
+ * @note DMA operation only
+ *
+ * @param num_blocks Number of message blocks to process
+ */
+static inline void sha_ll_set_block_num(size_t num_blocks)
+{
+    REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks);
+}
+
+/**
+ * @brief Checks if the SHA engine is currently busy hashing a block
+ *
+ * @return true SHA engine busy
+ * @return false SHA engine idle
+ */
+static inline bool sha_ll_busy(void)
+{
+    return REG_READ(SHA_BUSY_REG);
+}
+
+/**
+ * @brief Write a text (message) block to the SHA engine
+ *
+ * @param input_text Input buffer to be written to the SHA engine
+ * @param block_word_len Number of words in block
+ */
+static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
+{
+    uint32_t *data_words = (uint32_t *)input_text;
+    uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM);
+
+    for (int i = 0; i < block_word_len; i++) {
+        REG_WRITE(&reg_addr_buf[i], data_words[i]);
+    }
+}
+
+/**
+ * @brief Read the message digest from the SHA engine
+ *
+ * @param sha_type The SHA algorithm type
+ * @param digest_state Buffer that message digest will be written to
+ * @param digest_word_len Length of the message digest
+ */
+static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
+{
+    uint32_t *digest_state_words = (uint32_t *)digest_state;
+    const size_t REG_WIDTH = sizeof(uint32_t);
+
+    for (size_t i = 0; i < digest_word_len; i++) {
+        digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH));
+    }
+
+}
+
+/**
+ * @brief Write the message digest to the SHA engine
+ *
+ * @param sha_type The SHA algorithm type
+ * @param digest_state Message digest to be written to SHA engine
+ * @param digest_word_len Length of the message digest
+ */
+static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
+{
+    uint32_t *digest_state_words = (uint32_t *)digest_state;
+    uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM);
+
+    for (int i = 0; i < digest_word_len; i++) {
+        REG_WRITE(&reg_addr_buf[i], digest_state_words[i]);
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c61/include/hal/timer_ll.h

@@ -24,6 +24,7 @@ extern "C" {
 // Get timer group register base address with giving group number
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
+#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER)
 
 #define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                                        \
     (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{                                             \

components/hal/esp32c61/include/hal/uart_ll.h

@@ -64,6 +64,10 @@ extern "C" {
     ((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \
     PCR.uart2_##reg_suffix.uart2_##field_suffix)
 
+// UART sleep retention module
+#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
+                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
+
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),

components/hal/esp32c61/modem_clock_hal.c

@@ -59,7 +59,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte
     }
 }
 
-uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
+uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
 {
     HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
     uint32_t bitmap = 0;

components/hal/esp32c61/pau_hal.c

@@ -4,8 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// The HAL layer for PAU (ESP32-C61 specific part)
-
 #include "soc/soc.h"
 #include "esp_attr.h"
 #include "hal/pau_hal.h"
@@ -59,3 +57,14 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
     pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
 }
+
+void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
+{
+}
+
+void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
+{
+    HAL_ASSERT(count > 0 && interval > 0);
+    pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
+    pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
+}

components/hal/esp32p4/include/hal/pau_ll.h

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// The LL layer for ESP32-C6 PAU(Power Assist Unit) register operations
+// The LL layer for ESP32-P4 PAU(Power Assist Unit) register operations
 
 #pragma once
 

components/hal/test_apps/crypto/main/sha/test_sha.c

@@ -205,7 +205,7 @@ TEST_GROUP(sha);
 TEST_SETUP(sha)
 {
     test_utils_record_free_mem();
-    TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL));
+    TEST_ESP_OK(test_utils_set_leak_level(400, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL));
 }
 
 TEST_TEAR_DOWN(sha)

components/heap/CMakeLists.txt

@@ -7,16 +7,24 @@ if(${target} STREQUAL "linux")
     return()
 endif()
 
-set(srcs
-    "heap_caps_base.c"
-    "heap_caps.c"
-    "heap_caps_init.c"
-    "multi_heap.c")
+set(srcs "heap_caps_base.c"
+         "heap_caps.c"
+         "heap_caps_init.c"
+         "multi_heap.c")
 
-set(includes "include")
+# the root dir of TLSF submodule contains headers with static inline
+# functions used in the esp_rom component for TLSF patches. Therefore,
+# the tlsf/ dir must be included in the list of public includes.
+set(includes "include"
+             "tlsf")
+
+# The TLSF "public" includes should only be used
+# inside the heap component and are therefore added
+# to the list of the private includes from the heap
+# component perspective
+set(priv_includes "tlsf/include")
 
 if(NOT CONFIG_HEAP_TLSF_USE_ROM_IMPL)
-    set(priv_includes "tlsf")
     list(APPEND srcs "tlsf/tlsf.c")
 endif()
 

components/heap/linker.lf

@@ -5,9 +5,6 @@ entries:
         if HEAP_TLSF_USE_ROM_IMPL = n:
             tlsf:tlsf_block_size (noflash)
             tlsf:tlsf_size (noflash)
-            tlsf:tlsf_align_size (noflash)
-            tlsf:tlsf_block_size_min (noflash)
-            tlsf:tlsf_block_size_max (noflash)
             tlsf:tlsf_alloc_overhead (noflash)
             tlsf:tlsf_get_pool (noflash)
             tlsf:tlsf_malloc (noflash)

components/heap/multi_heap.c

@@ -15,10 +15,8 @@
 #include "multi_heap.h"
 #include "multi_heap_internal.h"
 
-#if !CONFIG_HEAP_TLSF_USE_ROM_IMPL
 #include "tlsf.h"
 #include "tlsf_block_functions.h"
-#endif
 
 /* Note: Keep platform-specific parts in this header, this source
    file should depend on libc only */
@@ -110,7 +108,7 @@ void multi_heap_in_rom_init(void)
 #else // CONFIG_HEAP_TLSF_USE_ROM_IMPL
 
 /* Check a block is valid for this heap. Used to verify parameters. */
-__attribute__((noinline)) NOCLONE_ATTR static void assert_valid_block(const heap_t *heap, const block_header_t *block)
+__attribute__((noinline)) NOCLONE_ATTR static void assert_valid_block(const heap_t *heap, const multi_heap_block_handle_t block)
 {
     pool_t pool = tlsf_get_pool(heap->heap_data);
     void *ptr = block_to_ptr(block);
@@ -175,22 +173,22 @@ multi_heap_block_handle_t multi_heap_get_first_block(multi_heap_handle_t heap)
 {
     assert(heap != NULL);
     pool_t pool = tlsf_get_pool(heap->heap_data);
-    block_header_t* block = offset_to_block(pool, -(int)block_header_overhead);
+    multi_heap_block_handle_t block = offset_to_block(pool, -(int)block_header_overhead);
 
-    return (multi_heap_block_handle_t)block;
+    return block;
 }
 
 multi_heap_block_handle_t multi_heap_get_next_block(multi_heap_handle_t heap, multi_heap_block_handle_t block)
 {
     assert(heap != NULL);
     assert_valid_block(heap, block);
-    block_header_t* next = block_next(block);
+    multi_heap_block_handle_t next = block_next(block);
 
     if(block_size(next) == 0) {
         //Last block:
         return NULL;
     } else {
-        return (multi_heap_block_handle_t)next;
+        return next;
     }
 
 }

components/heap/port/esp32c61/memory_layout.c

@@ -12,6 +12,11 @@
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
 
+/* Memory layout for ESP32C61 SoC
+ * Note that the external memory is not represented in this file since
+ * it is handled by the esp_psram component
+ */
+
 /**
  * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
  * Each type of memory map consists of one or more regions in the address space.
@@ -27,16 +32,14 @@
 
 /* Index of memory in `soc_memory_types[]` */
 enum {
-    SOC_MEMORY_TYPE_RAM     = 0,
-    SOC_MEMORY_TYPE_RTCRAM  = 1,
-    SOC_MEMORY_TYPE_NUM,
+    SOC_MEMORY_TYPE_RAM,
 };
 
 /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
-#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
+#define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
 #else
-#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
+#define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
 #endif
 
 /**
@@ -45,10 +48,9 @@ enum {
  * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
  * in turn to continue matching.
  */
-const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
+const soc_memory_type_desc_t soc_memory_types[] = {
     /*                           Mem Type Name   High Priority Matching                      Medium Priority Matching    Low Priority Matching */
-    [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
-    [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM",       { MALLOC_CAP_RTCRAM,                        ESP32C6_MEM_COMMON_CAPS,   0 }},
+    [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C61_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
 };
 
 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@@ -64,19 +66,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 /**
  * Register the shared buffer area of the last memory block into the heap during heap initialization
  */
-#define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
+#define APP_USABLE_DIRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
 const soc_memory_region_t soc_memory_regions[] = {
-    { 0x40800000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40800000,             false}, //D/IRAM level0, can be used as trace memory
-    { 0x40820000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40820000,             false}, //D/IRAM level1, can be used as trace memory
-    { 0x40840000,           (APP_USABLE_DRAM_END-0x40840000),          SOC_MEMORY_TYPE_RAM, 0x40840000,             false}, //D/IRAM level2, can be used as trace memory
-    { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END,    true},  //D/IRAM level3, can be used as trace memory (ROM reserved area)
+    { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW),  SOC_MEMORY_TYPE_RAM,     SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
+    { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM,     APP_USABLE_DIRAM_END,    true}, //D/IRAM, can be used as trace memory (ROM reserved area)
 };
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
 
 
-extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+extern int _data_start, _heap_start, _iram_start, _iram_end;
 
 /**
  * Reserved memory regions.

components/heap/test_apps/.build-test-rules.yml

@@ -3,9 +3,6 @@
 components/heap/test_apps/heap_tests:
   disable:
     - if: IDF_TARGET == "linux"
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: not support yet  # TODO: [esp32c61] IDF-9858
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
     - if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1
     # These 3 configs are build only for non-nightly, buildig for a single target is sufficient

components/heap/test_apps/heap_tests/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/heap/test_apps/heap_tests/main/test_malloc.c

@@ -176,7 +176,7 @@ TEST_CASE("test get allocated size", "[heap]")
         const size_t aligned_size = (alloc_sizes[i] + 3) & ~3;
         const size_t real_size = heap_caps_get_allocated_size(ptr_array[i]);
         printf("initial size: %d, requested size : %d, allocated size: %d\n", alloc_sizes[i], aligned_size, real_size);
-        TEST_ASSERT_EQUAL(aligned_size, real_size);
+        TEST_ASSERT(aligned_size <= real_size);
 
         heap_caps_free(ptr_array[i]);
     }

components/heap/test_apps/heap_tests/pytest_heap.py

@@ -6,7 +6,6 @@ from pytest_embedded import Dut
 
 @pytest.mark.generic
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD')  # TODO [ESP32C61] IDF-9858 IDF-10989
 @pytest.mark.nightly_run
 @pytest.mark.parametrize(
     'config',
@@ -40,7 +39,6 @@ def test_heap_poisoning_qemu(dut: Dut) -> None:
 
 @pytest.mark.generic
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD')  # TODO [ESP32C61] IDF-9858 IDF-10989
 @pytest.mark.parametrize(
     'config',
     [
@@ -52,9 +50,14 @@ def test_heap_in_flash(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
-@pytest.mark.esp32s2
-@pytest.mark.esp32s3
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+        'esp32s2',
+        'esp32s3',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [
@@ -67,7 +70,12 @@ def test_heap(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [
@@ -86,7 +94,12 @@ def test_heap_misc_options(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [

components/heap/test_multi_heap_host/Makefile

@@ -13,7 +13,7 @@ SOURCE_FILES = $(abspath \
 	main.cpp \
 	)
 
-INCLUDE_FLAGS = -I../include -I../../../tools/catch -I../tlsf
+INCLUDE_FLAGS = -I../include -I../../../tools/catch -I../tlsf -I../tlsf/include
 
 GCOV ?= gcov
 

components/heap/test_multi_heap_host/test_multi_heap.cpp

@@ -8,9 +8,9 @@
 #include "multi_heap.h"
 
 #include "../multi_heap_config.h"
-#include "../tlsf/tlsf.h"
-#include "../tlsf/tlsf_common.h"
+#include "../tlsf/include/tlsf.h"
 #include "../tlsf/tlsf_block_functions.h"
+#include "../tlsf/tlsf_control_functions.h"
 
 #include <string.h>
 #include <assert.h>
@@ -19,7 +19,7 @@
  * malloc and free and allocate memory from the host heap. Since the test
  * `TEST_CASE("multi_heap many random allocations", "[multi_heap]")`
  * calls multi_heap_allocation_impl() with sizes that can go up to 8MB,
- * an allocatation on the heap will be prefered rather than the stack which
+ * an allocatation on the heap will be preferred rather than the stack which
  * might not have the necessary memory.
  */
 static void *__malloc__(size_t bytes)
@@ -62,7 +62,7 @@ TEST_CASE("multi_heap simple allocations", "[multi_heap]")
     REQUIRE( (intptr_t)buf < (intptr_t)(small_heap + sizeof(small_heap)));
 
     REQUIRE( multi_heap_get_allocated_size(heap, buf) >= test_alloc_size );
-    REQUIRE( multi_heap_get_allocated_size(heap, buf) < test_alloc_size + 16);
+    printf("test alloc size %d\n", test_alloc_size);
 
     memset(buf, 0xEE, test_alloc_size);
 
@@ -482,7 +482,7 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
 {
     uint8_t test_heap[4 * 1024];
     multi_heap_handle_t heap = multi_heap_register(test_heap, sizeof(test_heap));
-    uint32_t aligments = 0; // starts from alignment by 4-byte boundary
+    uint32_t alignments = 0; // starts from alignment by 4-byte boundary
     size_t old_size = multi_heap_free_size(heap);
     size_t leakage = 1024;
     printf("[ALIGNED_ALLOC] heap_size before: %d \n", old_size);
@@ -491,26 +491,26 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
     multi_heap_dump(heap);
     printf("*********************\n");
 
-    for(;aligments <= 256; aligments++) {
+    for(;alignments <= 256; alignments++) {
 
         //Use some stupid size value to test correct alignment even in strange
         //memory layout objects:
-        uint8_t *buf = (uint8_t *)multi_heap_aligned_alloc(heap, (aligments + 137), aligments );
-        if(((aligments & (aligments - 1)) != 0) || (!aligments)) {
+        uint8_t *buf = (uint8_t *)multi_heap_aligned_alloc(heap, (alignments + 137), alignments );
+        if(((alignments & (alignments - 1)) != 0) || (!alignments)) {
             REQUIRE( buf == NULL );
         } else {
             REQUIRE( buf != NULL );
             REQUIRE((intptr_t)buf >= (intptr_t)test_heap);
             REQUIRE((intptr_t)buf < (intptr_t)(test_heap + sizeof(test_heap)));
 
-            printf("[ALIGNED_ALLOC] alignment required: %u \n", aligments);
+            printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments);
             printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf);
             //Address of obtained block must be aligned with selected value
-            REQUIRE(((intptr_t)buf & (aligments - 1)) == 0);
+            REQUIRE(((intptr_t)buf & (alignments - 1)) == 0);
 
             //Write some data, if it corrupts memory probably the heap
             //canary verification will fail:
-            memset(buf, 0xA5, (aligments + 137));
+            memset(buf, 0xA5, (alignments + 137));
 
             multi_heap_free(heap, buf);
         }
@@ -519,7 +519,7 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
     /* Check that TLSF doesn't allocate a memory space smaller than required.
      * In any case, TLSF will write data in the previous block than the one
      * allocated. Thus, we should try to get/allocate this previous block. If
-     * the poisoned filled pattern has beeen overwritten by TLSF, then this
+     * the poisoned filled pattern has been overwritten by TLSF, then this
      * previous block will trigger an exception.
      * More info on this bug in !16296. */
     const size_t size = 50; /* TLSF will round the size up */

components/heap/tlsf

@@ -1 +1 @@
-Subproject commit 8fc595fe223cd0b3b5d7b29eb86825e4bd38e6e8
+Subproject commit ba64d198a845df70b481e2c55004521ca643dea6

components/lwip/Kconfig

@@ -1355,11 +1355,15 @@ menu "LWIP"
         choice LWIP_HOOK_IP6_INPUT
             prompt "IPv6 packet input"
             depends on LWIP_IPV6
-            default LWIP_HOOK_IP6_INPUT_NONE
+            default LWIP_HOOK_IP6_INPUT_DEFAULT
             help
                 Enables custom IPv6 packet input.
-                Setting this to "default" provides weak implementation
-                stub that could be overwritten in application code.
+                Setting this to "default" provides weak IDF implementation,
+                which drops all incoming IPv6 traffic if the interface has no link local address.
+                (this default implementation is "weak" and could be still overwritten
+                in the application if some additional IPv6 input packet filtering is needed)
+                Setting this to "none" removes this default filter and conforms to the lwIP
+                implementation (which accepts multicasts even if the interface has no link local address)
                 Setting this to "custom" provides hook's declaration
                 only and expects the application to implement it.
 

components/lwip/port/hooks/lwip_default_hooks.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -56,11 +56,25 @@ const ip_addr_t *__weak lwip_hook_ip6_select_source_address(struct netif *netif,
 #endif
 
 #ifdef CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT
+/**
+ * @brief The default IPv6 input hook checks if we already have an IPv6 address (netif->ip6_addr[0] is link local),
+ * so we drop all incoming IPv6 packets if the input netif has no LL address.
+ *
+ * LWIP accepts IPv6 multicast packets even if the ip6_addr[] for the given address wasn't set,
+ * this may cause trouble if we enable IPv6 SLAAC (LWIP_IPV6_AUTOCONFIG), but have not created any LL address.
+ * If the router sends a packet to all nodes 0xff01::1 with RDNSS servers, it would be accepted and rewrite
+ * DNS server info with IPv6 values (which won't be routable without any IPv6 address assigned)
+ */
 int __weak lwip_hook_ip6_input(struct pbuf *p, struct netif *inp)
 {
-    LWIP_UNUSED_ARG(p);
-    LWIP_UNUSED_ARG(inp);
-
+    /* Check if the first IPv6 address (link-local) is unassigned (all zeros).
+     * If the address is empty, it indicates that no link-local address has been configured,
+     * and the interface should not accept incoming IPv6 traffic. */
+    if (ip6_addr_isany(ip_2_ip6(&inp->ip6_addr[0]))) {
+        /* We don't have an LL address -> eat this packet here, so it won't get accepted on the input netif */
+        pbuf_free(p);
+        return 1;
+    }
     return 0;
 }
 #endif

components/mbedtls/CMakeLists.txt

@@ -292,6 +292,9 @@ if(CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN OR CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY)
 
     if(CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY)
         target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_verify")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_verify_restartable")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_read_signature")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_read_signature_restartable")
     endif()
 endif()
 

components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c

@@ -92,8 +92,12 @@ static esp_err_t crypto_shared_gdma_init(void)
     transfer_cfg.max_data_burst_size = 0;
     gdma_config_transfer(rx_channel, &transfer_cfg);
 
+#ifdef SOC_AES_SUPPORTED
     gdma_connect(rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
     gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
+#elif SOC_SHA_SUPPORTED
+    gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
+#endif
 
     return ESP_OK;
 
@@ -123,11 +127,17 @@ esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *ou
     /* Tx channel is shared between AES and SHA, need to connect to peripheral every time */
     gdma_disconnect(tx_channel);
 
+#ifdef SOC_SHA_SUPPORTED
     if (peripheral == GDMA_TRIG_PERIPH_SHA) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
-    } else if (peripheral == GDMA_TRIG_PERIPH_AES) {
+    } else
+#endif // SOC_SHA_SUPPORTED
+#ifdef SOC_AES_SUPPORTED
+    if (peripheral == GDMA_TRIG_PERIPH_AES) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
-    } else {
+    } else
+#endif // SOC_AES_SUPPORTED
+    {
         return ESP_ERR_INVALID_ARG;
     }
 
@@ -176,11 +186,17 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
     /* Tx channel is shared between AES and SHA, need to connect to peripheral every time */
     gdma_disconnect(tx_channel);
 
+#ifdef SOC_SHA_SUPPORTED
     if (peripheral == GDMA_TRIG_PERIPH_SHA) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
-    } else if (peripheral == GDMA_TRIG_PERIPH_AES) {
+    } else
+#endif // SOC_SHA_SUPPORTED
+#ifdef SOC_AES_SUPPORTED
+    if (peripheral == GDMA_TRIG_PERIPH_AES) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
-    } else {
+    } else
+#endif // SOC_AES_SUPPORTED
+    {
         return ESP_ERR_INVALID_ARG;
     }
 

components/mbedtls/port/ecdsa/ecdsa_alt.c

@@ -15,6 +15,7 @@
 #include "esp_private/esp_crypto_lock_internal.h"
 #include "mbedtls/error.h"
 #include "mbedtls/ecdsa.h"
+#include "mbedtls/asn1.h"
 #include "mbedtls/asn1write.h"
 #include "mbedtls/platform_util.h"
 #include "ecdsa/ecdsa_alt.h"
@@ -653,6 +654,37 @@ static int esp_ecdsa_verify(mbedtls_ecp_group *grp,
     return ret;
 }
 
+/*
+ * Verify ECDSA signature of hashed message
+ */
+extern int __real_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx)
+{
+    if ((grp->id == MBEDTLS_ECP_DP_SECP192R1 || grp->id == MBEDTLS_ECP_DP_SECP256R1) && blen == ECDSA_SHA_LEN) {
+        return esp_ecdsa_verify(grp, buf, blen, Q, r, s);
+    } else {
+        return __real_mbedtls_ecdsa_verify_restartable(grp, buf, blen, Q, r, s, rs_ctx);
+    }
+}
+
 /*
  * Verify ECDSA signature of hashed message
  */
@@ -674,10 +706,84 @@ int __wrap_mbedtls_ecdsa_verify(mbedtls_ecp_group *grp,
                          const mbedtls_mpi *r,
                          const mbedtls_mpi *s)
 {
-    if (grp->id == MBEDTLS_ECP_DP_SECP192R1 || grp->id == MBEDTLS_ECP_DP_SECP256R1) {
-        return esp_ecdsa_verify(grp, buf, blen, Q, r, s);
-    } else {
-        return __real_mbedtls_ecdsa_verify(grp, buf, blen, Q, r, s);
+    return __wrap_mbedtls_ecdsa_verify_restartable(grp, buf, blen, Q, r, s, NULL);
+}
+
+
+int __real_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx)
+{
+    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
+    unsigned char *p = (unsigned char *) sig;
+    const unsigned char *end = sig + slen;
+    size_t len;
+    mbedtls_mpi r, s;
+    mbedtls_mpi_init(&r);
+    mbedtls_mpi_init(&s);
+
+    if ((ret = mbedtls_asn1_get_tag(&p, end, &len,
+                                    MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) != 0) {
+        ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
+        goto cleanup;
     }
+
+    if (p + len != end) {
+        ret = MBEDTLS_ERROR_ADD(MBEDTLS_ERR_ECP_BAD_INPUT_DATA,
+                                MBEDTLS_ERR_ASN1_LENGTH_MISMATCH);
+        goto cleanup;
+    }
+
+    if ((ret = mbedtls_asn1_get_mpi(&p, end, &r)) != 0 ||
+        (ret = mbedtls_asn1_get_mpi(&p, end, &s)) != 0) {
+        ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
+        goto cleanup;
+    }
+
+    if ((ret = __wrap_mbedtls_ecdsa_verify_restartable(&ctx->MBEDTLS_PRIVATE(grp), hash, hlen,
+                                                    &ctx->MBEDTLS_PRIVATE(Q), &r, &s, NULL)) != 0) {
+        goto cleanup;
+    }
+
+    /* At this point we know that the buffer starts with a valid signature.
+     * Return 0 if the buffer just contains the signature, and a specific
+     * error code if the valid signature is followed by more data. */
+    if (p != end) {
+        ret = MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH;
+    }
+
+cleanup:
+    mbedtls_mpi_free(&r);
+    mbedtls_mpi_free(&s);
+
+    return ret;
+}
+
+
+int __real_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen);
+
+int __wrap_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen);
+
+int __wrap_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen)
+{
+    return __wrap_mbedtls_ecdsa_read_signature_restartable(
+            ctx, hash, hlen, sig, slen, NULL);
 }
 #endif /* CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY */

components/riscv/include/riscv/csr.h

@@ -142,6 +142,18 @@ extern "C" {
     RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY) , 0); \
     } while(0)
 
+/* Reset and set the configuration of a particular TOR PMACFG entry */
+#define PMA_RESET_AND_ENTRY_SET_TOR(ENTRY, ADDR, CFG) do {\
+    PMA_ENTRY_CFG_RESET(ENTRY); \
+    PMA_ENTRY_SET_TOR(ENTRY, ADDR, CFG); \
+    } while(0)
+
+/* Reset and set the configuration of a particular NAPOT PMACFG entry */
+#define PMA_RESET_AND_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG) do {\
+    PMA_ENTRY_CFG_RESET(ENTRY); \
+    PMA_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG); \
+    } while(0)
+
 /********************************************************
    Trigger Module register fields (Debug specification)
  ********************************************************/

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1239,6 +1239,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
     int
     default 12
 
+config SOC_PM_SUPPORT_WIFI_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_BEACON_WAKEUP
+    bool
+    default y
+
 config SOC_PM_SUPPORT_BT_WAKEUP
     bool
     default y
@@ -1283,10 +1291,18 @@ config SOC_PM_SUPPORT_HP_AON_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_MAC_BB_PD
+    bool
+    default y
+
 config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_PMU_MODEM_STATE
+    bool
+    default y
+
 config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     bool
     default y
@@ -1315,6 +1331,10 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
     bool
     default y
 
+config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    int
+    default 4
+
 config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
@@ -1339,10 +1359,6 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
     bool
     default y
 
-config SOC_CLK_RC32K_NOT_TO_USE
-    bool
-    default y
-
 config SOC_RCC_IS_INDEPENDENT
     bool
     default y
@@ -1387,7 +1403,7 @@ config SOC_WIFI_HE_SUPPORT
     bool
     default y
 
-config SOC_WIFI_HE_SUPPORT_5G
+config SOC_WIFI_SUPPORT_5G
     bool
     default y
 

components/soc/esp32c5/include/soc/retention_periph_defs.h

@@ -43,6 +43,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
     SLEEP_RETENTION_MODULE_BT_BB        = 29,
     SLEEP_RETENTION_MODULE_802154_MAC   = 30,
+    SLEEP_RETENTION_MODULE_MODEM_PHY    = 31,
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
 
@@ -57,6 +58,7 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
     SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
     SLEEP_RETENTION_MODULE_BM_802154_MAC   = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
+    SLEEP_RETENTION_MODULE_BM_MODEM_PHY    = BIT(SLEEP_RETENTION_MODULE_MODEM_PHY),
 
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
      * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */

components/soc/esp32c5/include/soc/soc_caps.h

@@ -539,8 +539,8 @@
 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
 
 /*-------------------------- Power Management CAPS ----------------------------*/
-// #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
+#define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+#define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
 #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
 #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
@@ -552,12 +552,12 @@
 #define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
 #define SOC_PM_SUPPORT_TOP_PD           (1)
 #define SOC_PM_SUPPORT_HP_AON_PD        (1)
-// #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
+#define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 
-// #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
+#define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
 /* macro redefine for pass esp_wifi headers md5sum check */
-// #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
 
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
@@ -568,6 +568,7 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (5)
 #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
+#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC  (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 
@@ -578,7 +579,6 @@
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
-#define SOC_CLK_RC32K_NOT_TO_USE                  (1)     /*!< Due to the poor low-temperature characteristics of RC32K (it cannot operate below -40 degrees Celsius), please avoid using it whenever possible. */
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
@@ -594,7 +594,7 @@
 #define SOC_WIFI_CSI_SUPPORT                (1)    /*!< Support CSI */
 #define SOC_WIFI_MESH_SUPPORT               (1)    /*!< Support WIFI MESH */
 #define SOC_WIFI_HE_SUPPORT                 (1)    /*!< Support Wi-Fi 6 */
-#define SOC_WIFI_HE_SUPPORT_5G              (1)    /*!< Support Wi-Fi 6 in 5G */
+#define SOC_WIFI_SUPPORT_5G                 (1)    /*!< Support 5G */
 #define SOC_WIFI_MAC_VERSION_NUM            (3)    /*!< Wi-Fi MAC version num is 3 */
 
 /*---------------------------------- Bluetooth CAPS ----------------------------------*/

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -71,6 +71,10 @@ config SOC_SYSTIMER_SUPPORTED
     bool
     default y
 
+config SOC_SHA_SUPPORTED
+    bool
+    default y
+
 config SOC_ECC_SUPPORTED
     bool
     default y
@@ -91,6 +95,10 @@ config SOC_BOD_SUPPORTED
     bool
     default y
 
+config SOC_APM_SUPPORTED
+    bool
+    default y
+
 config SOC_PMU_SUPPORTED
     bool
     default y
@@ -99,6 +107,10 @@ config SOC_LP_TIMER_SUPPORTED
     bool
     default y
 
+config SOC_LP_AON_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_TREE_SUPPORTED
     bool
     default y
@@ -119,10 +131,18 @@ config SOC_REG_I2C_SUPPORTED
     bool
     default y
 
+config SOC_PAU_SUPPORTED
+    bool
+    default y
+
 config SOC_LIGHT_SLEEP_SUPPORTED
     bool
     default y
 
+config SOC_DEEP_SLEEP_SUPPORTED
+    bool
+    default y
+
 config SOC_PM_SUPPORTED
     bool
     default y
@@ -287,6 +307,10 @@ config SOC_GPIO_OUT_RANGE_MAX
     int
     default 21
 
+config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+    bool
+    default y
+
 config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
     int
     default 0
@@ -467,6 +491,34 @@ config SOC_MPU_REGION_WO_SUPPORTED
     bool
     default n
 
+config SOC_SHA_DMA_MAX_BUFFER_SIZE
+    int
+    default 3968
+
+config SOC_SHA_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_RESUME
+    bool
+    default y
+
+config SOC_SHA_GDMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA1
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA224
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA256
+    bool
+    default y
+
 config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
     bool
     default y
@@ -623,6 +675,14 @@ config SOC_TIMER_GROUP_SUPPORT_RC_FAST
     bool
     default y
 
+config SOC_TIMER_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_MWDT_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     bool
     default n
@@ -683,6 +743,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
     bool
     default y
 
+config SOC_APM_CTRL_FILTER_SUPPORTED
+    bool
+    default y
+
 config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
     bool
     default y
@@ -719,6 +783,10 @@ config SOC_UART_SUPPORT_WAKEUP_INT
     bool
     default y
 
+config SOC_UART_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
     bool
     default y
@@ -743,6 +811,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
     int
     default 12
 
+config SOC_PM_SUPPORT_EXT1_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
+    bool
+    default y
+
 config SOC_PM_SUPPORT_CPU_PD
     bool
     default y
@@ -767,6 +843,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_TOP_PD
+    bool
+    default y
+
 config SOC_PM_SUPPORT_HP_AON_PD
     bool
     default y
@@ -789,16 +869,32 @@ config SOC_PM_CPU_RETENTION_BY_SW
 
 config SOC_PM_MODEM_RETENTION_BY_REGDMA
     bool
-    default n
+    default y
 
 config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN
     bool
     default y
 
+config SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+    bool
+    default y
+
 config SOC_PM_PAU_LINK_NUM
     int
     default 4
 
+config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
+    bool
+    default y
+
+config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    bool
+    default y
+
+config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
+    bool
+    default y
+
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y
@@ -819,10 +915,6 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
     bool
     default y
 
-config SOC_CLK_RC32K_NOT_TO_USE
-    bool
-    default y
-
 config SOC_RCC_IS_INDEPENDENT
     bool
     default y

components/soc/esp32c61/include/soc/hwcrypto_reg.h

@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/sha_reg.h"

components/soc/esp32c61/include/soc/reg_base.h

@@ -35,7 +35,7 @@
 #define DR_REG_PAU_BASE                         0x60093000
 #define DR_REG_HP_SYSTEM_BASE                   0x60095000
 #define DR_REG_PCR_BASE                         0x60096000
-#define DR_REG_TEE_REG_BASE                     0x60098000
+#define DR_REG_TEE_BASE                         0x60098000
 #define DR_REG_HP_APM_BASE                      0x60099000
 #define DR_REG_MISC_BASE                        0x6009F000
 #define DR_REG_MODEM0_BASE                      0x600A0000

components/soc/esp32c61/include/soc/retention_periph_defs.h

@@ -18,23 +18,29 @@ typedef enum periph_retention_module {
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
-
-    /* modem module, which includes WiFi, BLE and 802.15.4 */
-    SLEEP_RETENTION_MODULE_WIFI_MAC     = 10,
-    SLEEP_RETENTION_MODULE_WIFI_BB      = 11,
-    SLEEP_RETENTION_MODULE_BLE_MAC      = 12,
-    SLEEP_RETENTION_MODULE_BT_BB        = 13,
-    SLEEP_RETENTION_MODULE_802154_MAC   = 14,
-
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
-    SLEEP_RETENTION_MODULE_SYS_PERIPH   = 16,
-
-    SLEEP_RETENTION_MODULE_GDMA_CH0     = 24,
-    SLEEP_RETENTION_MODULE_GDMA_CH1     = 25,
-    SLEEP_RETENTION_MODULE_GDMA_CH2     = 26,
-    SLEEP_RETENTION_MODULE_I2C0         = 27,
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
+    SLEEP_RETENTION_MODULE_SYS_PERIPH   = 3,
+    /* Timer Group by target */
+    SLEEP_RETENTION_MODULE_TG0_WDT      = 4,
+    SLEEP_RETENTION_MODULE_TG1_WDT      = 5,
+    SLEEP_RETENTION_MODULE_TG0_TIMER    = 6,
+    SLEEP_RETENTION_MODULE_TG1_TIMER    = 7,
+    /* GDMA by channel */
+    SLEEP_RETENTION_MODULE_GDMA_CH0     = 8,
+    SLEEP_RETENTION_MODULE_GDMA_CH1     = 9,
+    SLEEP_RETENTION_MODULE_GDMA_CH2     = 10,
+    /* MISC Peripherals */
+    SLEEP_RETENTION_MODULE_I2C0         = 12,
+    SLEEP_RETENTION_MODULE_UART0        = 14,
+    SLEEP_RETENTION_MODULE_UART1        = 15,
 
+    /* Modem module, which includes WiFi, BLE and 802.15.4 */
+    SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
+    SLEEP_RETENTION_MODULE_WIFI_BB      = 27,
+    SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
+    SLEEP_RETENTION_MODULE_BT_BB        = 29,
+    SLEEP_RETENTION_MODULE_802154_MAC   = 30,
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
 
@@ -42,26 +48,44 @@ typedef enum periph_retention_module_bitmap {
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
-
+    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
+     * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
+    SLEEP_RETENTION_MODULE_BM_SYS_PERIPH   = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
+    /* Timer Group by target*/
+    SLEEP_RETENTION_MODULE_BM_TASK_WDT     = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
+    SLEEP_RETENTION_MODULE_BM_INT_WDT      = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
+    SLEEP_RETENTION_MODULE_BM_TG0_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
+    SLEEP_RETENTION_MODULE_BM_TG1_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
+    /* GDMA by channel */
+    SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
+    SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
+    SLEEP_RETENTION_MODULE_BM_GDMA_CH2     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
+    /* MISC Peripherals */
+    SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
+    SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
+    SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
     SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
     SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
     SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
     SLEEP_RETENTION_MODULE_BM_802154_MAC   = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
-
-    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
-    SLEEP_RETENTION_MODULE_BM_SYS_PERIPH   = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
-
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH2     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
-    SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
-
     SLEEP_RETENTION_MODULE_BM_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 
+#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
+                                  | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
+                                  | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
+                                  | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
+                                  | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C0        \
+                                  | SLEEP_RETENTION_MODULE_BM_UART0       \
+                                  | SLEEP_RETENTION_MODULE_BM_UART1       \
+                                  )
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c61/include/soc/soc.h

@@ -146,20 +146,21 @@
  * should be defined statically!
  */
 
-#define SOC_IROM_LOW    0x42000000
-#define SOC_IROM_HIGH   0x44000000
-#define SOC_EXTRAM_DATA_LOW 0x42000000
-#define SOC_EXTRAM_DATA_HIGH 0x44000000
-#define SOC_DROM_LOW    SOC_IROM_LOW
-#define SOC_DROM_HIGH   SOC_IROM_HIGH
-#define SOC_IROM_MASK_LOW  0x40000000
-#define SOC_IROM_MASK_HIGH 0x40040000
-#define SOC_DROM_MASK_LOW  0x40000000
-#define SOC_DROM_MASK_HIGH 0x40040000
-#define SOC_IRAM_LOW    0x40800000
-#define SOC_IRAM_HIGH   0x40850000
-#define SOC_DRAM_LOW    0x40800000
-#define SOC_DRAM_HIGH   0x40850000
+#define SOC_IROM_LOW            0x42000000
+#define SOC_IROM_HIGH           0x44000000
+#define SOC_EXTRAM_DATA_LOW     0x42000000
+#define SOC_EXTRAM_DATA_HIGH    0x44000000
+#define SOC_EXTRAM_DATA_SIZE    (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
+#define SOC_DROM_LOW            SOC_IROM_LOW
+#define SOC_DROM_HIGH           SOC_IROM_HIGH
+#define SOC_IROM_MASK_LOW       0x40000000
+#define SOC_IROM_MASK_HIGH      0x40040000
+#define SOC_DROM_MASK_LOW       0x40000000
+#define SOC_DROM_MASK_HIGH      0x40040000
+#define SOC_IRAM_LOW            0x40800000
+#define SOC_IRAM_HIGH           0x40850000
+#define SOC_DRAM_LOW            0x40800000
+#define SOC_DRAM_HIGH           0x40850000
 
 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
 #define SOC_DIRAM_IRAM_LOW    0x40800000
@@ -196,7 +197,7 @@
 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
-#define SOC_ROM_STACK_START         0x4084c9f0
+#define SOC_ROM_STACK_START         0x4084ea70
 #define SOC_ROM_STACK_SIZE          0x2000
 
 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.

components/soc/esp32c61/include/soc/soc_caps.h

@@ -39,16 +39,16 @@
 #define SOC_LEDC_SUPPORTED              1
 #define SOC_SYSTIMER_SUPPORTED          1
 //  \#define SOC_SUPPORT_COEXISTENCE         1
-//  \#define SOC_SHA_SUPPORTED               1    //TODO: [ESP32C61] IDF-9234
+#define SOC_SHA_SUPPORTED               1
 #define SOC_ECC_SUPPORTED               1
 #define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
 #define SOC_FLASH_ENC_SUPPORTED         1
 #define SOC_SECURE_BOOT_SUPPORTED       1
 #define SOC_BOD_SUPPORTED               1
-//  \#define SOC_APM_SUPPORTED               1    //TODO: [ESP32C61] IDF-9230
+#define SOC_APM_SUPPORTED               1 /*!< Support for APM peripheral */
 #define SOC_PMU_SUPPORTED               1
 #define SOC_LP_TIMER_SUPPORTED          1
-//  \#define SOC_LP_AON_SUPPORTED            1
+#define SOC_LP_AON_SUPPORTED            1
 //  \#define SOC_LP_PERIPHERALS_SUPPORTED    1
  #define SOC_CLK_TREE_SUPPORTED          1
 //  \#define SOC_ASSIST_DEBUG_SUPPORTED      1    //TODO: [ESP32C61] IDF-9269
@@ -59,8 +59,9 @@
 #define SOC_REG_I2C_SUPPORTED           1
 //  \#define SOC_ETM_SUPPORTED               0
 //  \#define SOC_SDIO_SLAVE_SUPPORTED        0
-//  \#define SOC_PAU_SUPPORTED               0
+#define SOC_PAU_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
+#define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_PM_SUPPORTED                1
 #define SOC_ECDSA_SUPPORTED             1
 #define SOC_SPIRAM_SUPPORTED            1
@@ -179,7 +180,7 @@
 #define SOC_GPIO_OUT_RANGE_MAX          21
 
 // GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
-//  \#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  //TODO: IDF-9245
+#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT      (7)
 
@@ -274,19 +275,19 @@
    for SHA this means that the biggest safe amount of bytes is
    31 blocks of 128 bytes = 3968
 */
-// #define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
-// #define SOC_SHA_SUPPORT_DMA             (1)
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
 
 // /* The SHA engine is able to resume hashing from a user */
-// #define SOC_SHA_SUPPORT_RESUME          (1)
+#define SOC_SHA_SUPPORT_RESUME          (1)
 
 // /* Has a centralized DMA, which is shared with all peripherals */
-// #define SOC_SHA_GDMA             (1)
+#define SOC_SHA_GDMA             (1)
 
 // /* Supported HW algorithms */
-// #define SOC_SHA_SUPPORT_SHA1            (1)
-// #define SOC_SHA_SUPPORT_SHA224          (1)
-// #define SOC_SHA_SUPPORT_SHA256          (1)
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
 
 /*--------------------------- ECDSA CAPS ---------------------------------------*/
 #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY     (1)
@@ -348,10 +349,12 @@
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
+#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
 // #define SOC_TIMER_SUPPORT_ETM             (1)
 
 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
 // #define SOC_MWDT_SUPPORT_XTAL              (1)
+#define SOC_MWDT_SUPPORT_SLEEP_RETENTION   (1)
 
 /*-------------------------- eFuse CAPS----------------------------*/
 #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 0
@@ -374,6 +377,9 @@
 #define SOC_FLASH_ENCRYPTION_XTS_AES        1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
 
+/*-------------------------- APM CAPS ----------------------------------------*/
+#define SOC_APM_CTRL_FILTER_SUPPORTED   1 /*!< Support for APM control filter */
+
 /*------------------------ Anti DPA (Security) CAPS --------------------------*/
 #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
 
@@ -387,7 +393,7 @@
 #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
 #define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
-
+#define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)
 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
 
@@ -411,15 +417,15 @@
 // #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
 // #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
 // #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
+#define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
+#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
 #define SOC_PM_SUPPORT_CPU_PD           (1)
 #define SOC_PM_SUPPORT_MODEM_PD         (1)
 #define SOC_PM_SUPPORT_XTAL32K_PD       (1)
 #define SOC_PM_SUPPORT_RC32K_PD         (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 #define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
-//  \#define SOC_PM_SUPPORT_TOP_PD           (1)
+#define SOC_PM_SUPPORT_TOP_PD           (1)
 #define SOC_PM_SUPPORT_HP_AON_PD        (1)
 #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
@@ -428,12 +434,16 @@
 /* macro redefine for pass esp_wifi headers md5sum check */
 #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
 
-// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
-
 #define SOC_PM_CPU_RETENTION_BY_SW          (1)
-#define SOC_PM_MODEM_RETENTION_BY_REGDMA    (0)
+#define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
 #define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1)
-#define SOC_PM_PAU_LINK_NUM             (4)
+#define SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD   (1)
+
+#define SOC_PM_PAU_LINK_NUM                 (4)
+#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR   (1)
+#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC      (1)
+
+#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
@@ -442,7 +452,6 @@
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
-#define SOC_CLK_RC32K_NOT_TO_USE                  (1)     /*!< Due to the poor low-temperature characteristics of RC32K (it cannot operate below -40 degrees Celsius), please avoid using it whenever possible. */
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/

components/soc/esp32c61/include/soc/system_periph_retention.h

@@ -0,0 +1,82 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+#include "soc/regdma.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @brief Provide access to interrupt matrix configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define INT_MTX_RETENTION_LINK_LEN   1
+extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to hp_system configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define HP_SYSTEM_RETENTION_LINK_LEN 1
+extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to TEE_APM configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define TEE_APM_RETENTION_LINK_LEN   2
+extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN];
+#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN   1
+extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to IOMUX configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define IOMUX_RETENTION_LINK_LEN    7
+extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to spimem configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define SPIMEM_RETENTION_LINK_LEN   8
+extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN];
+
+/**
+ * @brief Provide access to systimer configuration registers retention
+ * context definition.
+ *
+ * This is an internal function of the sleep retention driver, and is not
+ * useful for external use.
+ */
+#define SYSTIMER_RETENTION_LINK_LEN   19
+extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c61/include/soc/tee_reg.h

@@ -768,10 +768,10 @@ extern "C" {
 /** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
  *  Version control register
  */
-#define TEE_DATE_REG    0x0FFFFFFFU
-#define TEE_DATE_REG_M  (TEE_DATE_REG_V << TEE_DATE_REG_S)
-#define TEE_DATE_REG_V  0x0FFFFFFFU
-#define TEE_DATE_REG_S  0
+#define TEE_DATE    0x0FFFFFFFU
+#define TEE_DATE_M  (TEE_DATE_REG_V << TEE_DATE_REG_S)
+#define TEE_DATE_V  0x0FFFFFFFU
+#define TEE_DATE_S  0
 
 #ifdef __cplusplus
 }

components/soc/esp32c61/system_retention_periph.c

@@ -0,0 +1,121 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/regdma.h"
+#include "soc/system_periph_retention.h"
+#include "soc/timer_periph.h"
+#include "soc/uart_reg.h"
+#include "soc/systimer_reg.h"
+#include "soc/timer_group_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/hp_system_reg.h"
+#include "soc/tee_reg.h"
+#include "soc/hp_apm_reg.h"
+#include "soc/gpio_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/interrupt_matrix_reg.h"
+
+/* Interrupt Matrix Registers Context */
+#define N_REGS_INTR_MATRIX()    (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
+const regdma_entries_config_t intr_matrix_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* intr matrix */
+};
+_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
+
+/* HP System Registers Context */
+#define N_REGS_HP_SYSTEM()      (((HP_SYSTEM_CLOCK_GATE_REG - DR_REG_HP_SYSTEM_BASE) / 4) + 1)
+const regdma_entries_config_t hp_system_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYSTEM_BASE, DR_REG_HP_SYSTEM_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* hp system */
+};
+_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
+
+/* TEE/APM Registers Context */
+#define N_REGS_TEE()    (((TEE_CLOCK_GATE_REG - DR_REG_TEE_BASE) / 4) + 1)
+#define N_REGS_APM()    (((HP_APM_CLOCK_GATE_REG - DR_REG_HP_APM_BASE) / 4) + 1)
+const regdma_entries_config_t tee_apm_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0), DR_REG_HP_APM_BASE, DR_REG_HP_APM_BASE, N_REGS_APM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* apm */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(1), DR_REG_TEE_BASE,    DR_REG_TEE_BASE,    N_REGS_TEE(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* tee */
+};
+const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xffffffff, 1, 0), .owner = ENTRY(2) }
+};
+_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
+
+/* IO MUX Registers Context */
+#define N_REGS_IOMUX_0()    (((PERIPHS_IO_MUX_U_PAD_SPID - REG_IO_MUX_BASE) / 4) + 1)
+#define N_REGS_IOMUX_1()    (((GPIO_FUNC21_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
+#define N_REGS_IOMUX_2()    (((GPIO_FUNC121_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
+#define N_REGS_IOMUX_3()    (((GPIO_PIN21_REG - GPIO_PIN0_REG) / 4) + 1)
+#define N_REGS_IOMUX_4()    (1)
+#define N_REGS_IOMUX_5()    (1)
+#define N_REGS_IOMUX_6()    (1)
+
+const regdma_entries_config_t iomux_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE,            REG_IO_MUX_BASE,            N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG,  GPIO_FUNC0_IN_SEL_CFG_REG,  N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG,              GPIO_PIN0_REG,              N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_STATUS_REG,            GPIO_STATUS_REG,            N_REGS_IOMUX_4(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x05), GPIO_ENABLE_REG,            GPIO_ENABLE_REG,            N_REGS_IOMUX_5(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x06), GPIO_OUT_REG,               GPIO_OUT_REG,               N_REGS_IOMUX_6(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
+};
+_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");
+
+/* Memory SPI Registers Context */
+#define N_REGS_SPI1_MEM_0()     (((SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
+#define N_REGS_SPI1_MEM_1()     (1)
+#define N_REGS_SPI1_MEM_2()     (1)
+#define N_REGS_SPI0_MEM_0()     (((SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
+#define N_REGS_SPI0_MEM_1()     (((SPI_SMEM_AC_REG(0)  - SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
+#define N_REGS_SPI0_MEM_2()     (1)
+#define N_REGS_SPI0_MEM_3()     (((SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
+const regdma_entries_config_t flash_spimem_regs_retention[] = {
+    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
+    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1),               REG_SPI_MEM_BASE(1),               N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_TIMING_CALI_REG(1),        SPI_MEM_TIMING_CALI_REG(1),        N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1),         SPI_MEM_CLOCK_GATE_REG(1),         N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
+    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), REG_SPI_MEM_BASE(0),               REG_SPI_MEM_BASE(0),               N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI_FMEM_PMS0_ATTR_REG(0),         SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_CLOCK_GATE_REG(0),         SPI_MEM_CLOCK_GATE_REG(0),         N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_MMU_POWER_CTRL_REG(0),     SPI_MEM_MMU_POWER_CTRL_REG(0),     N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    /* Note: spimem register should set update reg to make the configuration take effect */
+    [7] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0),        SPI_MEM_TIMING_CALI_UPDATE,        SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }
+};
+_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions");
+
+/* Systimer Registers Context */
+#define N_REGS_SYSTIMER_0()     (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1)
+const regdma_entries_config_t systimer_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_UPDATE_M,    SYSTIMER_TIMER_UNIT0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */
+    [1]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [2]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG,     SYSTIMER_TIMER_UNIT0_LOAD_M,      SYSTIMER_TIMER_UNIT0_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [4]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_UPDATE_M,    SYSTIMER_TIMER_UNIT1_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [5]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
+    [6]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [7]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG,     SYSTIMER_TIMER_UNIT1_LOAD_M,      SYSTIMER_TIMER_UNIT1_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [8]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG,     SYSTIMER_TARGET0_HI_REG,          N_REGS_SYSTIMER_0(),              0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */
+
+    [9]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG,     SYSTIMER_TIMER_COMP0_LOAD,        SYSTIMER_TIMER_COMP0_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [10] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG,     SYSTIMER_TIMER_COMP1_LOAD,        SYSTIMER_TIMER_COMP1_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [11] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG,     SYSTIMER_TIMER_COMP2_LOAD,        SYSTIMER_TIMER_COMP2_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [12] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG,   0,                                SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [13] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG,   SYSTIMER_TARGET0_PERIOD_MODE_M,   SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [14] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG,   0,                                SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [15] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG,   SYSTIMER_TARGET1_PERIOD_MODE_M,   SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [16] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG,   0,                                SYSTIMER_TARGET2_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
+
+    [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG,           SYSTIMER_CONF_REG,                1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */
+    [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG,        SYSTIMER_INT_ENA_REG,             1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* Systimer intr enable */
+};
+_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");

components/soc/esp32c61/timer_periph.c

@@ -22,3 +22,112 @@ const timer_group_signal_conn_t timer_group_periph_signals = {
         }
     }
 };
+
+/*  Registers in retention context:
+ *      TIMG_T0CONFIG_REG
+ *      TIMG_T0ALARMLO_REG
+ *      TIMG_T0ALARMHI_REG
+ *      TIMG_T0LOADLO_REG
+ *      TIMG_T0LOADHI_REG
+ *      TIMG_INT_ENA_TIMERS_REG
+ *      TIMG_REGCLK_REG
+ */
+#define TG_TIMER_RETENTION_REGS_CNT 7
+static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
+
+const regdma_entries_config_t tg0_timer_regdma_entries[] = {
+    // backup stage: trigger a soft capture
+    [0] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
+        TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: wait for the capture done
+    [1] = {
+        .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
+        TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: save the captured counter value
+    // restore stage: store the captured counter value to the loader register
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
+        TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    [3] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03),
+        TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // restore stage: trigger a soft reload, so the timer can continue from where it was backed up
+    [4] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x04),
+        TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: save other configuration and status registers
+    // restore stage: restore the configuration and status registers
+    [5] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x05),
+        TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0),
+        TG_TIMER_RETENTION_REGS_CNT, 0, 0,
+        tg_timer_regs_map[0], tg_timer_regs_map[1],
+        tg_timer_regs_map[2], tg_timer_regs_map[3]),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+};
+
+const regdma_entries_config_t tg1_timer_regdma_entries[] = {
+    // backup stage: trigger a soft capture
+    [0] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
+        TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: wait for the capture done
+    [1] = {
+        .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
+        TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: save the captured counter value
+    // restore stage: store the captured counter value to the loader register
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
+        TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    [3] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03),
+        TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // restore stage: trigger a soft reload, so the timer can continue from where it was backed up
+    [4] = {
+        .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x04),
+        TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+    // backup stage: save other configuration and status registers
+    // restore stage: restore the configuration and status registers
+    [5] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x05),
+        TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1),
+        TG_TIMER_RETENTION_REGS_CNT, 0, 0,
+        tg_timer_regs_map[0], tg_timer_regs_map[1],
+        tg_timer_regs_map[2], tg_timer_regs_map[3]),
+        .owner = TIMG_RETENTION_ENTRY
+    },
+};
+
+const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = tg0_timer_regdma_entries,
+        .array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
+    },
+    [1] = {
+        .regdma_entry_array = tg1_timer_regdma_entries,
+        .array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
+    },
+};

components/soc/esp32c61/uart_periph.c

@@ -5,6 +5,7 @@
  */
 
 #include "soc/uart_periph.h"
+#include "soc/uart_reg.h"
 
 /*
  Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
@@ -108,3 +109,52 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
         .irq = ETS_UART2_INTR_SOURCE,
     },
 };
+
+/**
+ * UART registers to be saved during sleep retention
+ *
+ * Reset TXFIFO and RXFIFO
+ * UART registers require set the reg_update bit to make the configuration take effect
+ *
+ * UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG,
+ * UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
+ * UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
+ * UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
+ * UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
+ */
+#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
+#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
+static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
+#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
+                                               UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
+                                               UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \
+                                               uart_regs_map[0], uart_regs_map[1], \
+                                               uart_regs_map[2], uart_regs_map[3] \
+                                              ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
+                                            UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
+                                            UART_REG_UPDATE_M, 1, 0 \
+                                           ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
+                                           UART_REG_UPDATE_REG(uart_num), 0x0, \
+                                           UART_REG_UPDATE_M, 1, 0 \
+                                          ), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
+
+const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
+    [0] = {
+        .regdma_entry_array = uart0_regdma_entries,
+        .array_size = ARRAY_SIZE(uart0_regdma_entries),
+    },
+    [1] = {
+        .regdma_entry_array = uart1_regdma_entries,
+        .array_size = ARRAY_SIZE(uart1_regdma_entries),
+    },
+};

components/soc/esp32c61/wdt_periph.c

@@ -5,3 +5,28 @@
  */
 
 #include "soc/wdt_periph.h"
+
+#define N_REGS_TGWDT          6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
+
+static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0),    TIMG_WDTCONFIG0_REG(0),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+
+static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
+    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1),    TIMG_WDTCONFIG0_REG(1),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [4] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
+    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
+    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
+};

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1863,6 +1863,10 @@ config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL
+    bool
+    default y
+
 config SOC_PERIPH_CLK_CTRL_SHARED
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -709,6 +709,8 @@
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
 #define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
+
 
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
 

components/ulp/CMakeLists.txt

@@ -52,7 +52,8 @@ endif()
 if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
     list(APPEND srcs
         "lp_core/lp_core.c"
-        "lp_core/shared/ulp_lp_core_memory_shared.c")
+        "lp_core/shared/ulp_lp_core_memory_shared.c"
+        "lp_core/shared/ulp_lp_core_critical_section_shared.c")
 
     if(CONFIG_SOC_ULP_LP_UART_SUPPORTED)
         list(APPEND srcs "lp_core/lp_core_uart.c")

components/ulp/cmake/IDFULPProject.cmake

@@ -125,7 +125,8 @@ function(ulp_apply_default_sources ulp_app_name)
         "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c"
         "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_spi.c"
         "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_ubsan.c"
-        "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_adc_shared.c")
+        "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_adc_shared.c"
+        "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_critical_section_shared.c")
 
         set(target_folder ${IDF_TARGET})