mirror of
https://github.com/espressif/esp-idf.git
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feat(pm): support top retention for esp32c61
This commit is contained in:
Lou Tianhao
parent
180bc4bd8c
commit
a30ed69f69
@ -0,0 +1,91 @@
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/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_private/sleep_clock.h"
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#include "soc/pcr_reg.h"
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#include "modem/modem_syscon_reg.h"
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static const char *TAG = "sleep_clock";
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esp_err_t sleep_clock_system_retention_init(void *arg)
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{
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const static sleep_retention_entries_config_t pcr_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 62, 0, 0, 0xfd73ffff, 0xfdffffff, 0xc001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
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};
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esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
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ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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}
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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esp_err_t sleep_clock_modem_retention_init(void *arg)
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{
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#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
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const static sleep_retention_entries_config_t modem_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
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};
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esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
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ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
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return ESP_OK;
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}
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#endif
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bool clock_domain_pd_allowed(void)
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{
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const uint32_t inited_modules = sleep_retention_get_inited_modules();
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const uint32_t created_modules = sleep_retention_get_created_modules();
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const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
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/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
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* through MODEM_SYSCON, when one or more MODEMs are initialized, it is
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* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
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* or off. The clock and reset of digital peripherals are managed through
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* PCR, with TOP domain similar to MODEM domain. */
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uint32_t modem_clk_dep_modules = 0;
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#if SOC_WIFI_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
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#endif
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#if SOC_BT_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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#if SOC_IEEE802154_SUPPORTED
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modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
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#endif
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uint32_t mask = 0;
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if (inited_modules & sys_clk_dep_modules) {
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
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}
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if (inited_modules & modem_clk_dep_modules) {
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#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
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#endif
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}
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return ((inited_modules & mask) == (created_modules & mask));
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}
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ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
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{
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sleep_retention_module_init_param_t init_param = {
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.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
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#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
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init_param = (sleep_retention_module_init_param_t) {
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.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
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.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
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};
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sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
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#endif
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return ESP_OK;
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}
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@ -476,12 +476,12 @@ typedef struct pmu_sleep_machine_constant {
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.reset_wait_time_us = 1, \
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.power_supply_wait_time_us = 20, \
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.power_up_wait_time_us = 2, \
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.regdma_s2m_work_time_us = 172, \
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.regdma_s2a_work_time_us = 480, \
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.regdma_m2a_work_time_us = 278, \
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.regdma_a2s_work_time_us = 382, \
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.regdma_rf_on_work_time_us = 70, \
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.regdma_rf_off_work_time_us = 23, \
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.regdma_s2m_work_time_us = 270, \
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.regdma_s2a_work_time_us = 666, \
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.regdma_m2a_work_time_us = 296, \
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.regdma_a2s_work_time_us = 586, \
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.regdma_rf_on_work_time_us = 138, \
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.regdma_rf_off_work_time_us = 28, \
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.xtal_wait_stable_time_us = 250, \
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.pll_wait_stable_time_us = 1 \
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} \
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@ -157,8 +157,8 @@
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
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#elif CONFIG_IDF_TARGET_ESP32C61
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (1148) //TODO: PM-231
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107)
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#elif CONFIG_IDF_TARGET_ESP32H2
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
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@ -191,6 +191,7 @@
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#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
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#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1220)
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#endif
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#endif
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// Minimal amount of time we can sleep for
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#define LIGHT_SLEEP_MIN_TIME_US 200
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@ -37,7 +37,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_hp_system_retention_in
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return ESP_OK;
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}
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#if SOC_APM_SUPPORTED
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#if SOC_APM_SUPPORTED || CONFIG_IDF_TARGET_ESP32C61
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static __attribute__((unused)) esp_err_t sleep_sys_periph_tee_apm_retention_init(void *arg)
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{
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/* TBD for ESP32P4 IDF-10020. */
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@ -132,7 +132,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
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err = sleep_sys_periph_l2_cache_retention_init();
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if(err) goto error;
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#endif
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#if SOC_APM_SUPPORTED
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#if SOC_APM_SUPPORTED || CONFIG_IDF_TARGET_ESP32C61
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err = sleep_sys_periph_tee_apm_retention_init(arg);
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if(err) goto error;
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#endif
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@ -82,6 +82,7 @@ SECONDARY: 103: esp_security_init in components/esp_security/src/init.c on BIT(0
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SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0)
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SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c on BIT(0)
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SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c on BIT(0)
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SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c on BIT(0)
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SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c on BIT(0)
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SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0)
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SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0)
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172
components/hal/esp32c61/include/hal/pau_ll.h
Normal file
172
components/hal/esp32c61/include/hal/pau_ll.h
Normal file
@ -0,0 +1,172 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-C61 PAU(Power Assist Unit) register operations
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#pragma once
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#include <stdlib.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "soc/pau_reg.h"
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#include "soc/pau_struct.h"
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#include "soc/pcr_struct.h"
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#include "hal/pau_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline void pau_ll_enable_bus_clock(bool enable)
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{
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if (enable) {
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PCR.regdma_conf.regdma_clk_en = 1;
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PCR.regdma_conf.regdma_rst_en = 0;
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} else {
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PCR.regdma_conf.regdma_clk_en = 0;
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PCR.regdma_conf.regdma_rst_en = 1;
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}
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}
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static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
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{
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return dev->regdma_conf.flow_err;
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}
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static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
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{
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dev->regdma_conf.link_sel = link;
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}
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static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
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{
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dev->regdma_conf.to_mem = to_mem ? 1 : 0;
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}
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static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
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{
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dev->regdma_conf.start = 1;
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}
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static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
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{
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dev->regdma_conf.start = 0;
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}
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static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
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{
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dev->regdma_conf.sel_mac = 1;
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}
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static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
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{
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dev->regdma_conf.sel_mac = 0;
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}
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static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
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{
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dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
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}
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static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
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{
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dev->regdma_conf.start_mac = 1;
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}
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static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
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{
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dev->regdma_conf.start_mac = 0;
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}
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static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
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{
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dev->regdma_link_0_addr.val = (uint32_t)link_addr;
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}
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static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
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{
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dev->regdma_link_1_addr.val = (uint32_t)link_addr;
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}
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static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
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{
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dev->regdma_link_2_addr.val = (uint32_t)link_addr;
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}
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static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
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{
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dev->regdma_link_3_addr.val = (uint32_t)link_addr;
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}
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static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
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{
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dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
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}
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static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
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{
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return dev->regdma_current_link_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
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{
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return dev->regdma_backup_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
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{
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return dev->regdma_mem_addr.val;
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}
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static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
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{
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return dev->int_raw.val;
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}
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static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
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{
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return dev->int_st.val;
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}
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static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
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{
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dev->int_ena.done_int_ena = 1;
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}
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static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
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{
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dev->int_ena.done_int_ena = 0;
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}
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static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
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{
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dev->int_ena.error_int_ena = enable;
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}
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static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
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{
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dev->int_clr.done_int_clr = 1;
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}
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static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
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{
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dev->int_clr.error_int_clr = 1;
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}
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static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
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{
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dev->regdma_bkp_conf.link_tout_thres = count;
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}
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static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
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{
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dev->regdma_bkp_conf.read_interval = interval;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -24,6 +24,7 @@ extern "C" {
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// Get timer group register base address with giving group number
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#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
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#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
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#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER)
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#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \
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(uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \
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@ -64,6 +64,10 @@ extern "C" {
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((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \
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PCR.uart2_##reg_suffix.uart2_##field_suffix)
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// UART sleep retention module
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#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
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(uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
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// Define UART interrupts
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typedef enum {
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UART_INTR_RXFIFO_FULL = (0x1 << 0),
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@ -4,8 +4,6 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for PAU (ESP32-C61 specific part)
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#include "soc/soc.h"
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#include "esp_attr.h"
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#include "hal/pau_hal.h"
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@ -59,3 +57,14 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
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pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
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pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
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}
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void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time)
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{
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}
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void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
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{
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||||
HAL_ASSERT(count > 0 && interval > 0);
|
||||
pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
|
||||
pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
|
||||
}
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C6 PAU(Power Assist Unit) register operations
|
||||
// The LL layer for ESP32-P4 PAU(Power Assist Unit) register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
|
||||
@ -127,6 +127,10 @@ config SOC_REG_I2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PAU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LIGHT_SLEEP_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
@ -659,6 +663,14 @@ config SOC_TIMER_GROUP_SUPPORT_RC_FAST
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MWDT_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
|
||||
bool
|
||||
default n
|
||||
@ -759,6 +771,10 @@ config SOC_UART_SUPPORT_WAKEUP_INT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
|
||||
bool
|
||||
default y
|
||||
@ -807,6 +823,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOP_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_HP_AON_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -35,7 +35,7 @@
|
||||
#define DR_REG_PAU_BASE 0x60093000
|
||||
#define DR_REG_HP_SYSTEM_BASE 0x60095000
|
||||
#define DR_REG_PCR_BASE 0x60096000
|
||||
#define DR_REG_TEE_REG_BASE 0x60098000
|
||||
#define DR_REG_TEE_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_BASE 0x60099000
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
#define DR_REG_MODEM0_BASE 0x600A0000
|
||||
|
||||
@ -18,23 +18,29 @@ typedef enum periph_retention_module {
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
|
||||
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2,
|
||||
|
||||
/* modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = 10,
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = 11,
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = 12,
|
||||
SLEEP_RETENTION_MODULE_BT_BB = 13,
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = 14,
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_SYS_PERIPH = 16,
|
||||
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0 = 24,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1 = 25,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2 = 26,
|
||||
SLEEP_RETENTION_MODULE_I2C0 = 27,
|
||||
* TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
|
||||
/* Timer Group by target */
|
||||
SLEEP_RETENTION_MODULE_TG0_WDT = 4,
|
||||
SLEEP_RETENTION_MODULE_TG1_WDT = 5,
|
||||
SLEEP_RETENTION_MODULE_TG0_TIMER = 6,
|
||||
SLEEP_RETENTION_MODULE_TG1_TIMER = 7,
|
||||
/* GDMA by channel */
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2 = 10,
|
||||
/* MISC Peripherals */
|
||||
SLEEP_RETENTION_MODULE_I2C0 = 12,
|
||||
SLEEP_RETENTION_MODULE_UART0 = 14,
|
||||
SLEEP_RETENTION_MODULE_UART1 = 15,
|
||||
|
||||
/* Modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = 26,
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = 27,
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = 28,
|
||||
SLEEP_RETENTION_MODULE_BT_BB = 29,
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = 30,
|
||||
SLEEP_RETENTION_MODULE_MAX = 31
|
||||
} periph_retention_module_t;
|
||||
|
||||
@ -42,26 +48,44 @@ typedef enum periph_retention_module_bitmap {
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
|
||||
SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_BM_SYS_PERIPH = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
|
||||
/* Timer Group by target*/
|
||||
SLEEP_RETENTION_MODULE_BM_TASK_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
|
||||
SLEEP_RETENTION_MODULE_BM_INT_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
|
||||
SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
|
||||
SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
|
||||
/* GDMA by channel */
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH2 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
|
||||
/* MISC Peripherals */
|
||||
SLEEP_RETENTION_MODULE_BM_I2C0 = BIT(SLEEP_RETENTION_MODULE_I2C0),
|
||||
SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0),
|
||||
SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1),
|
||||
/* modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
|
||||
SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
|
||||
SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
|
||||
SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB),
|
||||
SLEEP_RETENTION_MODULE_BM_802154_MAC = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_BM_SYS_PERIPH = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
|
||||
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH2 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
|
||||
SLEEP_RETENTION_MODULE_BM_I2C0 = BIT(SLEEP_RETENTION_MODULE_I2C0),
|
||||
|
||||
SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
|
||||
} periph_retention_module_bitmap_t;
|
||||
|
||||
#define TOP_DOMAIN_PERIPHERALS_BM ( SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
|
||||
| SLEEP_RETENTION_MODULE_BM_TASK_WDT \
|
||||
| SLEEP_RETENTION_MODULE_BM_INT_WDT \
|
||||
| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
|
||||
| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
|
||||
| SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \
|
||||
| SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \
|
||||
| SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \
|
||||
| SLEEP_RETENTION_MODULE_BM_I2C0 \
|
||||
| SLEEP_RETENTION_MODULE_BM_UART0 \
|
||||
| SLEEP_RETENTION_MODULE_BM_UART1 \
|
||||
)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -59,7 +59,7 @@
|
||||
#define SOC_REG_I2C_SUPPORTED 1
|
||||
// \#define SOC_ETM_SUPPORTED 0
|
||||
// \#define SOC_SDIO_SLAVE_SUPPORTED 0
|
||||
// \#define SOC_PAU_SUPPORTED 0
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
#define SOC_PM_SUPPORTED 1
|
||||
#define SOC_ECDSA_SUPPORTED 1
|
||||
@ -348,10 +348,12 @@
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
|
||||
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
|
||||
// #define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
// #define SOC_MWDT_SUPPORT_XTAL (1)
|
||||
#define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1)
|
||||
|
||||
/*-------------------------- eFuse CAPS----------------------------*/
|
||||
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 0
|
||||
@ -390,7 +392,7 @@
|
||||
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
|
||||
|
||||
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1)
|
||||
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
|
||||
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
|
||||
|
||||
@ -422,7 +424,7 @@
|
||||
#define SOC_PM_SUPPORT_RC32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
|
||||
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
|
||||
// \#define SOC_PM_SUPPORT_TOP_PD (1)
|
||||
#define SOC_PM_SUPPORT_TOP_PD (1)
|
||||
#define SOC_PM_SUPPORT_HP_AON_PD (1)
|
||||
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
|
||||
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
|
||||
@ -434,9 +436,13 @@
|
||||
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
|
||||
#define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (0)
|
||||
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
|
||||
#define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1)
|
||||
#define SOC_PM_PAU_LINK_NUM (4)
|
||||
#define SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD (1)
|
||||
|
||||
#define SOC_PM_PAU_LINK_NUM (4)
|
||||
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
|
||||
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
|
||||
@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/regdma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Provide access to interrupt matrix configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define INT_MTX_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to hp_system configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define HP_SYSTEM_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to TEE_APM configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define TEE_APM_RETENTION_LINK_LEN 2
|
||||
extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN];
|
||||
#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to IOMUX configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define IOMUX_RETENTION_LINK_LEN 7
|
||||
extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to spimem configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define SPIMEM_RETENTION_LINK_LEN 8
|
||||
extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to systimer configuration registers retention
|
||||
* context definition.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define SYSTIMER_RETENTION_LINK_LEN 19
|
||||
extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -769,9 +769,9 @@ extern "C" {
|
||||
* Version control register
|
||||
*/
|
||||
#define TEE_DATE 0x0FFFFFFFU
|
||||
#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
|
||||
#define TEE_DATE_REG_V 0x0FFFFFFFU
|
||||
#define TEE_DATE_REG_S 0
|
||||
#define TEE_DATE_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
|
||||
#define TEE_DATE_V 0x0FFFFFFFU
|
||||
#define TEE_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
121
components/soc/esp32c61/system_retention_periph.c
Normal file
121
components/soc/esp32c61/system_retention_periph.c
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/regdma.h"
|
||||
#include "soc/system_periph_retention.h"
|
||||
#include "soc/timer_periph.h"
|
||||
#include "soc/uart_reg.h"
|
||||
#include "soc/systimer_reg.h"
|
||||
#include "soc/timer_group_reg.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/hp_system_reg.h"
|
||||
#include "soc/tee_reg.h"
|
||||
#include "soc/hp_apm_reg.h"
|
||||
#include "soc/gpio_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/interrupt_matrix_reg.h"
|
||||
|
||||
/* Interrupt Matrix Registers Context */
|
||||
#define N_REGS_INTR_MATRIX() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
|
||||
const regdma_entries_config_t intr_matrix_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
|
||||
};
|
||||
_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
|
||||
|
||||
/* HP System Registers Context */
|
||||
#define N_REGS_HP_SYSTEM() (((HP_SYSTEM_CLOCK_GATE_REG - DR_REG_HP_SYSTEM_BASE) / 4) + 1)
|
||||
const regdma_entries_config_t hp_system_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYSTEM_BASE, DR_REG_HP_SYSTEM_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp system */
|
||||
};
|
||||
_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
|
||||
|
||||
/* TEE/APM Registers Context */
|
||||
#define N_REGS_TEE() (((TEE_CLOCK_GATE_REG - DR_REG_TEE_BASE) / 4) + 1)
|
||||
#define N_REGS_APM() (((HP_APM_CLOCK_GATE_REG - DR_REG_HP_APM_BASE) / 4) + 1)
|
||||
const regdma_entries_config_t tee_apm_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0), DR_REG_HP_APM_BASE, DR_REG_HP_APM_BASE, N_REGS_APM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* apm */
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(1), DR_REG_TEE_BASE, DR_REG_TEE_BASE, N_REGS_TEE(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* tee */
|
||||
};
|
||||
const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xffffffff, 1, 0), .owner = ENTRY(2) }
|
||||
};
|
||||
_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
|
||||
|
||||
/* IO MUX Registers Context */
|
||||
#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_U_PAD_SPID - REG_IO_MUX_BASE) / 4) + 1)
|
||||
#define N_REGS_IOMUX_1() (((GPIO_FUNC21_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
|
||||
#define N_REGS_IOMUX_2() (((GPIO_FUNC121_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1)
|
||||
#define N_REGS_IOMUX_3() (((GPIO_PIN21_REG - GPIO_PIN0_REG) / 4) + 1)
|
||||
#define N_REGS_IOMUX_4() (1)
|
||||
#define N_REGS_IOMUX_5() (1)
|
||||
#define N_REGS_IOMUX_6() (1)
|
||||
|
||||
const regdma_entries_config_t iomux_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_STATUS_REG, GPIO_STATUS_REG, N_REGS_IOMUX_4(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x05), GPIO_ENABLE_REG, GPIO_ENABLE_REG, N_REGS_IOMUX_5(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x06), GPIO_OUT_REG, GPIO_OUT_REG, N_REGS_IOMUX_6(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
|
||||
};
|
||||
_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");
|
||||
|
||||
/* Memory SPI Registers Context */
|
||||
#define N_REGS_SPI1_MEM_0() (((SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
|
||||
#define N_REGS_SPI1_MEM_1() (1)
|
||||
#define N_REGS_SPI1_MEM_2() (1)
|
||||
#define N_REGS_SPI0_MEM_0() (((SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
|
||||
#define N_REGS_SPI0_MEM_1() (((SPI_SMEM_AC_REG(0) - SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
|
||||
#define N_REGS_SPI0_MEM_2() (1)
|
||||
#define N_REGS_SPI0_MEM_3() (((SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
|
||||
const regdma_entries_config_t flash_spimem_regs_retention[] = {
|
||||
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
|
||||
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1), REG_SPI_MEM_BASE(1), N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_TIMING_CALI_REG(1), SPI_MEM_TIMING_CALI_REG(1), N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLOCK_GATE_REG(1), N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
|
||||
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), REG_SPI_MEM_BASE(0), REG_SPI_MEM_BASE(0), N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
|
||||
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI_FMEM_PMS0_ATTR_REG(0), SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLOCK_GATE_REG(0), N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
/* Note: spimem register should set update reg to make the configuration take effect */
|
||||
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SPIMEM_LINK(0x07), SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CALI_UPDATE, SPI_MEM_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }
|
||||
};
|
||||
_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions");
|
||||
|
||||
/* Systimer Registers Context */
|
||||
#define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1)
|
||||
const regdma_entries_config_t systimer_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_UPDATE_M, SYSTIMER_TIMER_UNIT0_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */
|
||||
[1] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG, SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG, SYSTIMER_TIMER_UNIT0_LOAD_M, SYSTIMER_TIMER_UNIT0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */
|
||||
|
||||
[9] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[10] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[11] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[12] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG, 0, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[13] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG, SYSTIMER_TARGET0_PERIOD_MODE_M, SYSTIMER_TARGET0_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[14] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG, 0, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[15] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG, SYSTIMER_TARGET1_PERIOD_MODE_M, SYSTIMER_TARGET1_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[16] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG, 0, SYSTIMER_TARGET2_PERIOD_MODE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
|
||||
[17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */
|
||||
[18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* Systimer intr enable */
|
||||
};
|
||||
_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");
|
||||
@ -22,3 +22,112 @@ const timer_group_signal_conn_t timer_group_periph_signals = {
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/* Registers in retention context:
|
||||
* TIMG_T0CONFIG_REG
|
||||
* TIMG_T0ALARMLO_REG
|
||||
* TIMG_T0ALARMHI_REG
|
||||
* TIMG_T0LOADLO_REG
|
||||
* TIMG_T0LOADHI_REG
|
||||
* TIMG_INT_ENA_TIMERS_REG
|
||||
* TIMG_REGCLK_REG
|
||||
*/
|
||||
#define TG_TIMER_RETENTION_REGS_CNT 7
|
||||
static const uint32_t tg_timer_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
|
||||
|
||||
const regdma_entries_config_t tg0_timer_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
|
||||
TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
|
||||
TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
|
||||
TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03),
|
||||
TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x04),
|
||||
TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[5] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x05),
|
||||
TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0),
|
||||
TG_TIMER_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer_regs_map[0], tg_timer_regs_map[1],
|
||||
tg_timer_regs_map[2], tg_timer_regs_map[3]),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const regdma_entries_config_t tg1_timer_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
|
||||
TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
|
||||
TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
|
||||
TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03),
|
||||
TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x04),
|
||||
TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[5] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x05),
|
||||
TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1),
|
||||
TG_TIMER_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer_regs_map[0], tg_timer_regs_map[1],
|
||||
tg_timer_regs_map[2], tg_timer_regs_map[3]),
|
||||
.owner = TIMG_RETENTION_ENTRY
|
||||
},
|
||||
};
|
||||
|
||||
const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = tg0_timer_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
|
||||
},
|
||||
[1] = {
|
||||
.regdma_entry_array = tg1_timer_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
|
||||
},
|
||||
};
|
||||
|
||||
@ -5,6 +5,7 @@
|
||||
*/
|
||||
|
||||
#include "soc/uart_periph.h"
|
||||
#include "soc/uart_reg.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
@ -108,3 +109,52 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
|
||||
.irq = ETS_UART2_INTR_SOURCE,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* UART registers to be saved during sleep retention
|
||||
*
|
||||
* Reset TXFIFO and RXFIFO
|
||||
* UART registers require set the reg_update bit to make the configuration take effect
|
||||
*
|
||||
* UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG,
|
||||
* UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
|
||||
* UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
|
||||
* UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
|
||||
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
|
||||
*/
|
||||
#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
|
||||
#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
|
||||
static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
|
||||
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
|
||||
[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
|
||||
UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
|
||||
UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \
|
||||
uart_regs_map[0], uart_regs_map[1], \
|
||||
uart_regs_map[2], uart_regs_map[3] \
|
||||
), \
|
||||
.owner = ENTRY(0) | ENTRY(2) }, \
|
||||
[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
|
||||
UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
|
||||
UART_REG_UPDATE_M, 1, 0 \
|
||||
), \
|
||||
.owner = ENTRY(0) | ENTRY(2) }, \
|
||||
[2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
|
||||
UART_REG_UPDATE_REG(uart_num), 0x0, \
|
||||
UART_REG_UPDATE_M, 1, 0 \
|
||||
), \
|
||||
.owner = ENTRY(0) | ENTRY(2) }, \
|
||||
}
|
||||
|
||||
static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
|
||||
static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
|
||||
|
||||
const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
|
||||
[0] = {
|
||||
.regdma_entry_array = uart0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(uart0_regdma_entries),
|
||||
},
|
||||
[1] = {
|
||||
.regdma_entry_array = uart1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(uart1_regdma_entries),
|
||||
},
|
||||
};
|
||||
|
||||
@ -5,3 +5,28 @@
|
||||
*/
|
||||
|
||||
#include "soc/wdt_periph.h"
|
||||
|
||||
#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
|
||||
|
||||
static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
};
|
||||
|
||||
static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
|
||||
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
|
||||
};
|
||||
|
||||
const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
|
||||
[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
|
||||
[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user