Merge a8b4627705 into 46acfdce96

feat(nimble): Set data length after connection

See merge request espressif/esp-idf!32655

.gitlab/CODEOWNERS

@@ -59,6 +59,7 @@
 /CONTRIBUTING.md                      @esp-idf-codeowners/docs
 /Kconfig                              @esp-idf-codeowners/build-config
 /README*.md                           @esp-idf-codeowners/docs
+/ROADMAP*.md                          @esp-idf-codeowners/docs
 /SUPPORT_POLICY*.md                   @esp-idf-codeowners/docs
 /add_path.sh                          @esp-idf-codeowners/tools
 /conftest.py                          @esp-idf-codeowners/ci

.gitlab/ci/build.yml

@@ -156,11 +156,12 @@ build_clang_test_apps_esp32s3:
   extends:
     - .build_cmake_clang_template
   variables:
-    # For RISCV clang generates '.linker-options' sections of type 'llvm_linker_options' in asm files.
-    # See (https://llvm.org/docs/Extensions.html#linker-options-section-linker-options).
-    # Binutils gas ignores them with warning.
-    # TODO: LLVM-333, Use integrated assembler.
-    TEST_BUILD_OPTS_EXTRA: "--ignore-warning-str 'Warning: unrecognized section type'"
+    # https://reviews.llvm.org/D90108.
+    # GNU 'as' lets .weak override .globl since binutils-gdb
+    # https://github.com/bminor/binutils-gdb/commit/5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996)
+    # while MC lets the last directive win (PR38921).
+    # For RISCV chips we use integrated assembler by default, so suppress this warning to pass CI pipeline.
+    TEST_BUILD_OPTS_EXTRA: "--ignore-warning-str 'changed binding to STB_WEAK'"
 
 build_clang_test_apps_esp32c3:
   extends:

Kconfig

@@ -676,6 +676,5 @@ mainmenu "Espressif IoT Development Framework Configuration"
             - CONFIG_ESPTOOLPY_FLASHFREQ_120M && CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
             - CONFIG_SPIRAM_SPEED_120M && CONFIG_SPIRAM_MODE_OCT
             - CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
-            - CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL
             - CONFIG_ESP_WIFI_EAP_TLS1_3
             - CONFIG_ESP_WIFI_ENABLE_ROAMING_APP

ROADMAP.md

@@ -0,0 +1,123 @@
+# ESP-IDF Project Roadmap 2024
+
+This document outlines the goals of ESP-IDF project and is shared for the convenience of our customers. It is important to clarify that this document is not a binding commitment to our customers. Instead, its primary purpose is to offer a clear roadmap and direction for the project's development. By openly sharing this information, we aim to enhance our customers' understanding, promote transparency and ensure alignment with the overarching objectives of the ESP-IDF project.
+
+## Project Overview
+
+### Project Goals
+
+In both minor and major releases, we integrate new chip support to enhance our product range. By expanding the chip matrix, we broaden the scope of our offerings, catering to a wider audience with diverse needs. This proactive approach ensures that our products remain at the forefront of technological advancements, consistently meeting and exceeding customer expectations.
+
+Furthermore, we prioritize bugfix releases for active branches, focusing on improving the stability and performance of products already in production. By addressing bugs promptly, we aim to enhance the overall user experience and provide tangible benefits to customers relying on our solutions. This proactive maintenance strategy reflects our commitment to delivering reliable, high-quality products to our valued customer base.
+
+Below are the main objectives that ESP-IDF project/teams would like to implement in 2024.
+
+-   New Chip Support
+
+    -   Add support for ESP32-P4
+    -   Add support for ESP32-C5
+    -   Add support for ESP32-C61
+
+-   More Minor Releases
+
+    -   Release IDF v5.3 in 2024
+    -   Release IDF v5.4 at the start of 2025
+
+-   More Bugfix Releases
+
+    -   Release v4.4.8 for IDF v4.4 before ESP-IDF v4.4 goes End of Life in July 2024
+    -   Do more bugfix releases for IDF v5.1 before release/5.1 enters maintenance period in June 2024
+    -   Do more bug fixes releases for release/5.2 and release/5.3, and push the two releases to be more stable and production-ready
+
+-   Updates of Libraries
+
+    -   Update GDB to 14.2
+    -   Update LLVM to 18.1.2
+    -   Update MbedTLS to 3.6 (LTS)
+    -   Update LWIP to 2.2.0
+    -   Change minimal Python requirement to 3.9
+
+Please note that support status of previous silicones could be found on [ESP-IDF Release and SoC Compatibility](https://github.com/espressif/esp-idf#esp-idf-release-and-soc-compatibility).
+
+### Roadmap Details
+
+The ESP-IDF project prioritizes consistent maintenance and updates to ensure our customers remain at the forefront of technological advancements. Our commitment to ongoing development ensures that customers continuously benefit from the latest innovations in the field.
+
+Moreover, we are dedicated to empowering our customers to leverage newly implemented features and enhanced functionalities through iterative improvements. Our steadfast commitment to pushing boundaries ensures that clients not only keep pace with evolving technology but also extract optimal value from the cutting-edge capabilities of our products.
+
+Below are the main roadmap details for functional areas inside ESP-IDF.
+
+-   New Chip Support
+
+    -   Add full support for ESP32-P4 in ESP-IDF v5.3, refer to [ESP32-P4 Support Status](https://github.com/espressif/esp-idf/issues/12996)
+    -   Add preview support for ESP32-C5 in ESP-IDF v5.3 and full support for ESP32-C5 in ESP-IDF v5.4, refer to [ESP32-C5 Support Status](https://github.com/espressif/esp-idf/issues/14021)
+    -   Add preview support for the early samples of ESP32-C61 in ESP-IDF v5.4 and full support for mass production version in ESP-IDF v5.4.x. Refer to [ESP32-C61 Support Status](https://developer.espressif.com/pages/chip-support-status/esp32c61/#esp-idf)
+
+-   Bugfix releases
+
+    -   Do bugfix release IDF v4.4.8 and stop maintaining ESP-IDF v4.4 in July 2024
+    -   Release bugfix IDF v5.0.6 and IDF v5.0.7 in 2024 (maintenance period)
+    -   Release bugfix IDF v5.1.3 and IDF v5.1.4 in H1 of 2024, and release IDF v5.1.5 in H2 of 2024
+    -   Push release/5.1 to maintenance period from June 2024
+    -   Do more bug fixes releases for release/5.2 (IDF v5.2.1, IDF v5.2.2, IDF v5.2.3) and release/5.3 (IDF v5.3.1, IDF v5.3.2), and push releases to be more stable and more production-ready
+
+## ESP-IDF Planning information
+
+For the full list of ESP-IDF releases, please visit https://github.com/espressif/esp-idf/releases
+
+### ESP-IDF Major Releases
+
+No Major Releases planned
+
+### ESP-IDF Minor Releases
+
+#### Quarter One
+
+-   v5.2-RC1, estimate release date: 2024/02/02
+-   v5.2 final release, estimate release date: 2024/02/08
+
+#### Quarter Two
+
+-   v5.3-beta1, estimate release date:: 2024/05/13
+-   v5.3-beta2, estimate release date:: 2024/05/31
+-   v5.3-RC1, estimate release date:: 2024/07/08
+
+#### Quarter Three
+
+-   v5.3-RC2, estimate release date:: 2024/07/26
+-   v5.3 final release, estimate release date:: 2024/08/02
+
+#### Quarter Four
+
+-   v5.4-beta1, estimate release date:: 2024/11/08
+-   v5.4-beta2, estimate release date:: 2024/11/29
+-   v5.4-RC1, estimate release date:: 2025/01/09
+-   v5.4-RC2, estimate release date:: 2025/01/29
+-   v5.4 final release, estimate release date: 2025/02/05
+
+### ESP-IDF Bugfix Releases
+
+#### Quarter One
+
+-   v5.1.3, estimate release date: 2024/02/08
+-   v5.0.6, estimate release date: 2024/02/18
+-   v4.4.7, estimate release date:: 2024/03/19
+-   v5.2.1, estimate release date:: 2024/03/31
+
+#### Quarter Two
+
+-   v5.1.4, estimate release date:: 2024/05/06
+-   v5.2.2, estimate release date:: 2024/06/17
+-   v4.4.8, estimate release date:: 2024/07/19
+
+#### Quarter Three
+
+-   v5.0.7, estimate release date: 2024/08/22
+-   v5.3.1, estimate release date: 2024/09/16
+-   v5.2.3, estimate release date: 2024/10/10
+
+#### Quarter Four
+
+-   v5.1.5, estimate release date: 2024/11/04  (Maintenance period since June 2024)
+-   v5.3.2, estimate release date: 2024/12/31
+-   v5.2.4, estimate release date: 2025/02/20 (Service period ends Feb. 2025)

components/app_trace/app_trace.c

@@ -26,8 +26,6 @@
 #define ESP_APPTRACE_MAX_VPRINTF_ARGS 256
 #define ESP_APPTRACE_HOST_BUF_SIZE 256
 
-#define ESP_APPTRACE_PRINT_LOCK 0
-
 const static char *TAG = "esp_apptrace";
 
 /** tracing module internal data */
@@ -90,7 +88,7 @@ void esp_apptrace_down_buffer_config(uint8_t *buf, uint32_t size)
         return;
     }
     // currently down buffer is supported for JTAG interface only
-    // TODO: one more argument should be added to this function to specify HW inteface: JTAG, UART0 etc
+    // TODO: one more argument should be added to this function to specify HW interface: JTAG, UART0 etc
     ch = &s_trace_channels[ESP_APPTRACE_DEST_JTAG];
     if (ch->hw != NULL) {
         if (ch->hw->down_buffer_config != NULL) {

components/app_trace/app_trace_util.c

@@ -9,12 +9,14 @@
 #include "esp_app_trace_util.h"
 #include "sdkconfig.h"
 
+#define ESP_APPTRACE_PRINT_LOCK 0
+
 ///////////////////////////////////////////////////////////////////////////////
 ///////////////////////////////// Locks /////////////////////////////////////
 ///////////////////////////////////////////////////////////////////////////////
 
 #if ESP_APPTRACE_PRINT_LOCK
-static esp_apptrace_lock_t s_log_lock = {.irq_stat = 0, .portmux = portMUX_INITIALIZER_UNLOCKED};
+static esp_apptrace_lock_t s_log_lock = { .mux = portMUX_INITIALIZER_UNLOCKED };
 #endif
 
 int esp_apptrace_log_lock(void)
@@ -87,7 +89,7 @@ esp_err_t esp_apptrace_lock_give(esp_apptrace_lock_t *lock)
 uint8_t *esp_apptrace_rb_produce(esp_apptrace_rb_t *rb, uint32_t size)
 {
     uint8_t *ptr = rb->data + rb->wr;
-    // check for avalable space
+    // check for available space
     if (rb->rd <= rb->wr) {
         // |?R......W??|
         if (rb->wr + size >= rb->size) {

components/app_update/test_apps/.build-test-rules.yml

@@ -1,7 +0,0 @@
-# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
-
-components/app_update/test_apps:
-  disable:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: target esp32c61 is not supported yet  # TODO: [ESP32C61] IDF-9245

components/app_update/test_apps/README.md

@@ -1,2 +0,0 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/app_update/test_apps/pytest_app_update_ut.py

@@ -1,26 +0,0 @@
-# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-import re
-
-import pytest
-from pytest_embedded import Dut
-
-DEFAULT_TIMEOUT = 20
-TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
-
-
-def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
-    for stage in range(1, stages + 1):
-        dut.write(str(test_case_num))
-        dut.expect(TEST_SUBMENU_PATTERN_PYTEST, timeout=DEFAULT_TIMEOUT)
-        dut.write(str(stage))
-        if stage != stages:
-            dut.expect_exact('Press ENTER to see the list of tests.')
-
-
-@pytest.mark.supported_targets
-# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
-@pytest.mark.generic
-def test_app_update(dut: Dut) -> None:
-    dut.run_all_single_board_cases(timeout=90)

components/app_update/test_apps/test_app_update/.build-test-rules.yml

@@ -0,0 +1,12 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/app_update/test_apps:
+  enable:
+    - if: CONFIG_NAME == "defaults" and IDF_TARGET != "linux"
+    - if: CONFIG_NAME == "xip_psram" and IDF_TARGET in ["esp32s2", "esp32s3", "esp32p4"]
+    # S2 doesn't have ROM for flash
+    - if: CONFIG_NAME == "xip_psram_with_rom_impl" and IDF_TARGET in ["esp32s3", "esp32p4"]
+  disable:
+    - if: IDF_TARGET in ["esp32c61"]
+      temporary: true
+      reason: target esp32c61 is not supported yet  # TODO: [ESP32C61] IDF-9245

components/app_update/test_apps/test_app_update/README.md

@@ -0,0 +1,2 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/app_update/test_apps/test_app_update/main/CMakeLists.txt

@@ -1,4 +1,4 @@
 idf_component_register(SRC_DIRS "."
                        PRIV_INCLUDE_DIRS "."
-                       PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash
+                       PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash esp_psram
                       WHOLE_ARCHIVE)

components/app_update/test_apps/test_app_update/main/test_ota_ops.c

@@ -6,6 +6,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include "esp_log.h"
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
 #include <freertos/semphr.h>
@@ -113,3 +114,11 @@ TEST_CASE("esp_ota_get_partition_description", "[ota]")
     };
     TEST_ESP_ERR(ESP_ERR_NOT_FOUND, bootloader_common_get_partition_description(&not_app_pos, &app_desc1));
 }
+
+TEST_CASE("esp_ota_get_running_partition points to correct address", "[spi_flash]")
+{
+    const esp_partition_t *factory = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, "factory");
+    const esp_partition_t* part = esp_ota_get_running_partition();
+    ESP_LOGI("running bin", "0x%p", (void*)part->address);
+    TEST_ASSERT_EQUAL_HEX32(factory->address, part->address);
+}

components/app_update/test_apps/test_app_update/pytest_app_update_ut.py

@@ -0,0 +1,52 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import re
+
+import pytest
+from pytest_embedded import Dut
+
+DEFAULT_TIMEOUT = 20
+TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
+
+
+@pytest.mark.supported_targets
+@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'defaults',
+    ],
+    indirect=True,
+)
+def test_app_update(dut: Dut) -> None:
+    dut.run_all_single_board_cases(timeout=90)
+
+
+@pytest.mark.supported_targets
+# TODO: [ESP32C61] IDF-9245, IDF-10983
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'xip_psram',
+    ],
+    indirect=True,
+)
+def test_app_update_xip_psram(dut: Dut) -> None:
+    dut.run_all_single_board_cases(timeout=90)
+
+
+@pytest.mark.supported_targets
+@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'xip_psram_with_rom_impl',
+    ],
+    indirect=True,
+)
+def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
+    dut.run_all_single_board_cases(timeout=90)

components/app_update/test_apps/test_app_update/sdkconfig.ci.defaults

@@ -0,0 +1,2 @@
+# don't delete.
+# used for CI to compile a default config when 'sdkconfig.ci.xxxx' is exist

components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram

@@ -1,2 +1,2 @@
-CONFIG_IDF_TARGET="esp32c5"
+CONFIG_SPIRAM=y
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y

components/app_update/test_apps/test_app_update/sdkconfig.ci.xip_psram_with_rom_impl

@@ -0,0 +1,3 @@
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_XIP_FROM_PSRAM=y
+CONFIG_SPI_FLASH_ROM_IMPL=y

components/bootloader_support/src/bootloader_mem.c

@@ -16,12 +16,6 @@
 #include "hal/apm_hal.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-#include "soc/hp_apm_reg.h"
-#include "soc/lp_apm_reg.h"
-#endif
-
-
 void bootloader_init_mem(void)
 {
 
@@ -38,13 +32,6 @@ void bootloader_init_mem(void)
 #endif
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-    // disable apm filter
-    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
-    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
-#endif
-
-
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
     esp_cpu_configure_region_protection();

components/bootloader_support/src/esp32c61/bootloader_sha.c

@@ -13,8 +13,6 @@
 
 static SHA_CTX ctx;
 
-//TODO: [ESP32C61] IDF-9234
-
 bootloader_sha256_handle_t bootloader_sha256_start()
 {
     // Enable SHA hardware

components/bt/CMakeLists.txt

@@ -6,6 +6,8 @@ endif()
 
 if(CONFIG_IDF_TARGET_ESP32S3)
     set(target_name "esp32c3")
+elseif(CONFIG_IDF_TARGET_ESP32C61)
+    set(target_name "esp32c6")
 else()
     set(target_name "${idf_target}")
 endif()
@@ -854,7 +856,16 @@ if(CONFIG_BT_ENABLED)
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
         target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
     elseif(CONFIG_BT_CONTROLLER_ENABLED)
-        add_prebuilt_library(libble_app "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        if(CONFIG_IDF_TARGET_ESP32C6)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c6/libble_app.a")
+        elseif(CONFIG_IDF_TARGET_ESP32C61)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c61/libble_app.a")
+        else()
+            add_prebuilt_library(libble_app
+                 "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        endif()
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     endif()
 

components/bt/controller/esp32c3/Kconfig.in

@@ -200,8 +200,8 @@ choice BT_CTRL_DFT_TX_POWER_LEVEL
         bool "+15dBm"
     config BT_CTRL_DFT_TX_POWER_LEVEL_P18
         bool "+18dBm"
-    config BT_CTRL_DFT_TX_POWER_LEVEL_P21
-        bool "+21dBm"
+    config BT_CTRL_DFT_TX_POWER_LEVEL_P20
+        bool "+20dBm"
 endchoice
 
 config BT_CTRL_DFT_TX_POWER_LEVEL_EFF
@@ -221,7 +221,7 @@ config BT_CTRL_DFT_TX_POWER_LEVEL_EFF
     default 12 if BT_CTRL_DFT_TX_POWER_LEVEL_P12
     default 13 if BT_CTRL_DFT_TX_POWER_LEVEL_P15
     default 14 if BT_CTRL_DFT_TX_POWER_LEVEL_P18
-    default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P21
+    default 15 if BT_CTRL_DFT_TX_POWER_LEVEL_P20
     default 0
 
 config BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP

components/bt/controller/esp32c61/Kconfig.in

@@ -0,0 +1 @@
+source "$IDF_PATH/components/bt/controller/esp32c6/Kconfig.in"

components/bt/controller/lib_esp32c2/esp32c2-bt-lib

@@ -1 +1 @@
-Subproject commit e652624750341aca124e9f850e261b0c1ac63529
+Subproject commit e5c7ef0bf701d02c2203e26081fdd348d45935e5

components/bt/controller/lib_esp32c3_family

@@ -1 +1 @@
-Subproject commit b8ef2c474d392a88ea7e6626f89acf1fa5f30e4a
+Subproject commit 5c913171361dac0821e15e83cc0cf604149e1b84

components/bt/controller/lib_esp32c6/esp32c6-bt-lib

@@ -1 +1 @@
-Subproject commit f95513f22be7b21429b01ba05dbfbc98097b5e67
+Subproject commit 3f15aa1d602aedf510dd9c686b3f7e5ea8a44002

components/bt/controller/lib_esp32h2/esp32h2-bt-lib

@@ -1 +1 @@
-Subproject commit 58a293a2b4c305157723908ea29c2776f5803bbc
+Subproject commit 50f567fff506f63b4d06ebea80d0405fe9e39568

components/bt/esp_ble_mesh/lib/lib

@@ -1 +1 @@
-Subproject commit 8312e0e0d5390d04fd282e8005528d2b5c351c08
+Subproject commit cba99c5a2e7f5d4bccb04e8f3f968dc888bb5667

components/bt/host/bluedroid/Kconfig.in

@@ -126,6 +126,7 @@ config BT_L2CAP_ENABLED
 config BT_SDP_COMMON_ENABLED
     bool "BT SDP COMMON"
     depends on BT_CLASSIC_ENABLED
+    default y if BT_L2CAP_ENABLED
     default n
     help
         This enables common SDP operation, such as SDP record creation and deletion.

components/bt/host/bluedroid/api/include/api/esp_gatts_api.h

@@ -242,6 +242,7 @@ typedef union {
      */
     struct gatts_rsp_evt_param {
         esp_gatt_status_t status;       /*!< Operation status */
+        uint16_t conn_id;               /*!< Connection id */
         uint16_t handle;                /*!< Attribute handle which send response */
     } rsp;                              /*!< Gatt server callback param of ESP_GATTS_RESPONSE_EVT */
 

components/bt/host/bluedroid/api/include/api/esp_sdp_api.h

@@ -65,30 +65,32 @@ typedef enum {
 /**
  * @brief SDP header structure
  */
-typedef struct {
+typedef struct bluetooth_sdp_hdr_overlay {
     esp_bluetooth_sdp_types_t type;                 /*!< SDP type */
+    esp_bt_uuid_t uuid;                             /*!< UUID type, include uuid and uuid length, only needed to be set for RAW record creation */
     uint32_t service_name_length;                   /*!< Service name length */
     char *service_name;                             /*!< Service name */
     int32_t rfcomm_channel_number;                  /*!< RFCOMM channel number, if not used set to -1*/
     int32_t l2cap_psm;                              /*!< L2CAP psm, if not used set to -1 */
     int32_t profile_version;                        /*!< Profile version */
-} esp_bluetooth_sdp_hdr_t;
+    int user1_ptr_len;                              /*!< User data1 length, only used for searching RAW record */
+    uint8_t *user1_ptr;                             /*!< User data1 pointer to the raw SDP response data, only used for searching RAW record */
+    int user2_ptr_len __attribute__((deprecated));  /*!< User data2 length, only used for searching RAW record */
+    uint8_t *user2_ptr __attribute__((deprecated)); /*!< User data2 pointer, only used for searching RAW record */
+} esp_bluetooth_sdp_hdr_overlay_t;
 
 /**
  * @brief Raw SDP record
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr; /*!< General info */
-    esp_bt_uuid_t uuid;          /*!< UUID type， include uuid and uuid length */
-    int user1_ptr_len;           /*!< Length of raw SDP data */
-    uint8_t *user1_ptr;          /*!< Raw SDP data */
+typedef struct bluetooth_sdp_raw_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
 } esp_bluetooth_sdp_raw_record_t;
 
 /**
  * @brief Message Access Profile - Server parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr;      /*!< General info */
+typedef struct bluetooth_sdp_mas_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
     uint32_t mas_instance_id;            /*!< MAS Instance ID */
     uint32_t supported_features;         /*!< Map supported features */
     uint32_t supported_message_types;    /*!< Supported message types */
@@ -97,16 +99,16 @@ typedef struct {
 /**
  * @brief Message Access Profile - Client (Notification Server) parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr; /*!< General info */
+typedef struct bluetooth_sdp_mns_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
     uint32_t supported_features;         /*!< Supported features */
 } esp_bluetooth_sdp_mns_record_t;
 
 /**
  * @brief Phone Book Profile - Server parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr;     /*!< General info */
+typedef struct bluetooth_sdp_pse_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
     uint32_t supported_features;         /*!< PBAP Supported Features */
     uint32_t supported_repositories;     /*!< Supported Repositories */
 } esp_bluetooth_sdp_pse_record_t;
@@ -114,15 +116,15 @@ typedef struct {
 /**
  * @brief Phone Book Profile - Client parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr; /*!< General info */
+typedef struct bluetooth_sdp_pce_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
 } esp_bluetooth_sdp_pce_record_t;
 
 /**
  * @brief Object Push Profile parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr;                                          /*!< General info */
+typedef struct bluetooth_sdp_ops_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr;                                  /*!< General info */
     int supported_formats_list_len;                                       /*!< Supported formats list length */
     uint8_t supported_formats_list[SDP_OPP_SUPPORTED_FORMATS_MAX_LENGTH]; /*!< Supported formats list */
 } esp_bluetooth_sdp_ops_record_t;
@@ -130,8 +132,8 @@ typedef struct {
 /**
  * @brief SIM Access Profile parameters
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr;       /*!< General info */
+typedef struct bluetooth_sdp_sap_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
 } esp_bluetooth_sdp_sap_record_t;
 
 /**
@@ -148,8 +150,8 @@ typedef enum {
  * @note Only one primary Device Identification service record can be added in the SDP database. If primary
  * Device Identification service is created multiple times, only the last one will take effect.
  */
-typedef struct {
-    esp_bluetooth_sdp_hdr_t hdr;    /*!< General info */
+typedef struct bluetooth_sdp_dip_record {
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
     uint16_t vendor;                     /*!< Vendor ID */
     uint16_t vendor_id_source;           /*!< Vendor ID source, 0x0001 for Bluetooth, 0x0002 for USB, other values reserved, see `esp_sdp_vendor_id_source_t` */
     uint16_t product;                    /*!< Product ID */
@@ -162,7 +164,7 @@ typedef struct {
  * @brief SDP record parameters union
  */
 typedef union {
-    esp_bluetooth_sdp_hdr_t        hdr;  /*!< General info */
+    esp_bluetooth_sdp_hdr_overlay_t hdr; /*!< General info */
     esp_bluetooth_sdp_raw_record_t raw;  /*!< Raw SDP search data for unknown UUIDs */
     esp_bluetooth_sdp_mas_record_t mas;  /*!< Message Access Profile - Server */
     esp_bluetooth_sdp_mns_record_t mns;  /*!< Message Access Profile - Client (Notification Server) */
@@ -205,7 +207,7 @@ typedef union {
     /**
      * @brief ESP_SDP_CREATE_RECORD_COMP_EVT
      */
-    struct sdp_crate_record_evt_param {
+    struct sdp_create_record_evt_param {
         esp_sdp_status_t status; /*!< Status */
         int record_handle;       /*!< SDP record handle */
     } create_record;             /*!< SDP callback param of ESP_SDP_CREATE_RECORD_COMP_EVT */

components/bt/host/bluedroid/bta/include/bta/bta_sdp_api.h

@@ -85,8 +85,10 @@ typedef void (tBTA_SDP_DM_CBACK)(tBTA_SDP_EVT event, tBTA_SDP *p_data, void *use
 
 /* MCE configuration structure */
 typedef struct {
+    UINT16            sdp_raw_size;    /* The size of p_sdp_raw_data */
     UINT16            sdp_db_size;     /* The size of p_sdp_db */
 #if (SDP_INCLUDED == TRUE)
+    UINT8             *p_sdp_raw_data; /* The data buffer to keep raw data */
     tSDP_DISCOVERY_DB *p_sdp_db;       /* The data buffer to keep SDP database */
 #endif  ///SDP_INCLUDED == TRUE
 } tBTA_SDP_CFG;

components/bt/host/bluedroid/bta/sdp/bta_sdp_act.c

@@ -395,29 +395,29 @@ static void bta_create_raw_sdp_record(bluetooth_sdp_record *record, tSDP_DISC_RE
     tSDP_DISC_ATTR *p_attr;
     tSDP_PROTOCOL_ELEM pe;
 
-    record->hdr.type = SDP_TYPE_RAW;
-    record->hdr.service_name_length = 0;
-    record->hdr.service_name = NULL;
-    record->hdr.rfcomm_channel_number = -1;
-    record->hdr.l2cap_psm = -1;
-    record->hdr.profile_version = -1;
+    record->raw.hdr.type = SDP_TYPE_RAW;
+    record->raw.hdr.service_name_length = 0;
+    record->raw.hdr.service_name = NULL;
+    record->raw.hdr.rfcomm_channel_number = -1;
+    record->raw.hdr.l2cap_psm = -1;
+    record->raw.hdr.profile_version = -1;
 
     /* Try to extract a service name */
     if ((p_attr = SDP_FindAttributeInRec(p_rec, ATTR_ID_SERVICE_NAME)) != NULL) {
-        record->pse.hdr.service_name_length = SDP_DISC_ATTR_LEN(p_attr->attr_len_type);
-        record->pse.hdr.service_name = (char *)p_attr->attr_value.v.array;
+        record->raw.hdr.service_name_length = SDP_DISC_ATTR_LEN(p_attr->attr_len_type);
+        record->raw.hdr.service_name = (char *)p_attr->attr_value.v.array;
     }
 
     if ((p_attr = SDP_FindAttributeInRec(p_rec, ATTR_ID_GOEP_L2CAP_PSM)) != NULL) {
-        record->hdr.l2cap_psm = p_attr->attr_value.v.u16;
+        record->raw.hdr.l2cap_psm = p_attr->attr_value.v.u16;
     }
 
     /* Try to extract an RFCOMM channel */
     if (SDP_FindProtocolListElemInRec(p_rec, UUID_PROTOCOL_RFCOMM, &pe)) {
-        record->pse.hdr.rfcomm_channel_number = pe.params[0];
+        record->raw.hdr.rfcomm_channel_number = pe.params[0];
     }
-    record->raw.user1_ptr_len = p_bta_sdp_cfg->p_sdp_db->raw_size;
-    record->raw.user1_ptr = p_bta_sdp_cfg->p_sdp_db->raw_data;
+    record->raw.hdr.user1_ptr_len = p_bta_sdp_cfg->p_sdp_db->raw_used;
+    record->raw.hdr.user1_ptr = p_bta_sdp_cfg->p_sdp_db->raw_data;
 }
 
 
@@ -570,6 +570,10 @@ void bta_sdp_search(tBTA_SDP_MSG *p_data)
     SDP_InitDiscoveryDb (p_bta_sdp_cfg->p_sdp_db, p_bta_sdp_cfg->sdp_db_size, 1,
                          bta_sdp_search_uuid, 0, NULL);
 
+    /* tell SDP to keep the raw data */
+    p_bta_sdp_cfg->p_sdp_db->raw_size = p_bta_sdp_cfg->sdp_raw_size;
+    p_bta_sdp_cfg->p_sdp_db->raw_data = p_bta_sdp_cfg->p_sdp_raw_data;
+
     if (!SDP_ServiceSearchAttributeRequest2(p_data->get_search.bd_addr, p_bta_sdp_cfg->p_sdp_db,
                                             bta_sdp_search_cback, (void *)bta_sdp_search_uuid)) {
         bta_sdp_cb.sdp_active = BTA_SDP_ACTIVE_NONE;

components/bt/host/bluedroid/bta/sdp/bta_sdp_api.c

@@ -65,7 +65,9 @@ tBTA_SDP_STATUS BTA_SdpEnable(tBTA_SDP_DM_CBACK *p_cback)
 #if BTA_DYNAMIC_MEMORY == TRUE
     /* Malloc buffer for SDP configuration structure */
     p_bta_sdp_cfg->p_sdp_db = (tSDP_DISCOVERY_DB *)osi_malloc(p_bta_sdp_cfg->sdp_db_size);
-    if (p_bta_sdp_cfg->p_sdp_db == NULL) {
+    p_bta_sdp_cfg->p_sdp_raw_data = (UINT8 *)osi_malloc(p_bta_sdp_cfg->sdp_raw_size);
+    if (p_bta_sdp_cfg->p_sdp_db == NULL || p_bta_sdp_cfg->p_sdp_raw_data == NULL) {
+        BTA_SdpCleanup();
         return BTA_SDP_FAILURE;
     }
 #endif
@@ -118,8 +120,15 @@ tBTA_SDP_STATUS BTA_SdpCleanup(void)
     bta_sys_deregister(BTA_ID_SDP);
 #if BTA_DYNAMIC_MEMORY == TRUE
     /* Free buffer for SDP configuration structure */
+    if (p_bta_sdp_cfg->p_sdp_db) {
         osi_free(p_bta_sdp_cfg->p_sdp_db);
         p_bta_sdp_cfg->p_sdp_db = NULL;
+    }
+
+    if (p_bta_sdp_cfg->p_sdp_raw_data) {
+        osi_free(p_bta_sdp_cfg->p_sdp_raw_data);
+        p_bta_sdp_cfg->p_sdp_raw_data = NULL;
+    }
 #endif
     return BTA_SDP_SUCCESS;
 }

components/bt/host/bluedroid/bta/sdp/bta_sdp_cfg.c

@@ -30,16 +30,24 @@
 #define BTA_SDP_DB_SIZE  1500
 #endif
 
+#ifndef BTA_SDP_RAW_DATA_SIZE
+#define BTA_SDP_RAW_DATA_SIZE 1024
+#endif
+
 #if BTA_DYNAMIC_MEMORY == FALSE
+static UINT8 bta_sdp_raw_data[BTA_SDP_RAW_DATA_SIZE];
 static UINT8 __attribute__ ((aligned(4))) bta_sdp_db_data[BTA_SDP_DB_SIZE];
 #endif
 
 /* SDP configuration structure */
 tBTA_SDP_CFG bta_sdp_cfg = {
+    BTA_SDP_RAW_DATA_SIZE,
     BTA_SDP_DB_SIZE,
 #if BTA_DYNAMIC_MEMORY == FALSE
+    bta_sdp_raw_data,
     (tSDP_DISCOVERY_DB *)bta_sdp_db_data /* The data buffer to keep SDP database */
 #else
+    NULL,
     NULL
 #endif
 };

components/bt/host/bluedroid/btc/profile/std/gatt/btc_gatts.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -469,7 +469,7 @@ static esp_gatt_status_t btc_gatts_check_valid_attr_tab(esp_gatts_attr_db_t *gat
                 if(gatts_attr_db[i+1].att_desc.uuid_length != ESP_UUID_LEN_16 &&
                    gatts_attr_db[i+1].att_desc.uuid_length != ESP_UUID_LEN_32 &&
                    gatts_attr_db[i+1].att_desc.uuid_length != ESP_UUID_LEN_128) {
-                    BTC_TRACE_ERROR("%s, The Charateristic uuid length = %d is invalid", __func__,\
+                    BTC_TRACE_ERROR("%s, The Characteristic uuid length = %d is invalid", __func__,\
                         gatts_attr_db[i+1].att_desc.uuid_length);
                     return ESP_GATT_INVALID_ATTR_LEN;
                 }
@@ -481,7 +481,7 @@ static esp_gatt_status_t btc_gatts_check_valid_attr_tab(esp_gatts_attr_db_t *gat
                         uuid == ESP_GATT_UUID_CHAR_SRVR_CONFIG || uuid == ESP_GATT_UUID_CHAR_PRESENT_FORMAT ||
                         uuid == ESP_GATT_UUID_CHAR_AGG_FORMAT || uuid == ESP_GATT_UUID_CHAR_VALID_RANGE ||
                         uuid == ESP_GATT_UUID_EXT_RPT_REF_DESCR || uuid == ESP_GATT_UUID_RPT_REF_DESCR) {
-                        BTC_TRACE_ERROR("%s, The charateristic value uuid = %d is invalid", __func__, uuid);
+                        BTC_TRACE_ERROR("%s, The characteristic value uuid = %d is invalid", __func__, uuid);
                         return ESP_GATT_INVALID_PDU;
                     }
                 }
@@ -694,6 +694,7 @@ void btc_gatts_call_handler(btc_msg_t *msg)
         }
 
         param.rsp.status = 0;
+        param.rsp.conn_id = BTC_GATT_GET_CONN_ID(arg->send_rsp.conn_id);
         btc_gatts_cb_to_app(ESP_GATTS_RESPONSE_EVT, BTC_GATT_GET_GATT_IF(arg->send_rsp.conn_id), &param);
         break;
     }

components/bt/host/bluedroid/btc/profile/std/include/bt_sdp.h

@@ -38,56 +38,62 @@ typedef enum {
     SDP_TYPE_DIP_SERVER, // Device Identification Profile
 } bluetooth_sdp_types;
 
-typedef struct _bluetooth_sdp_hdr {
+/**
+ * Some signals need additional pointers, hence we introduce a
+ * generic way to handle these pointers.
+ */
+typedef struct _bluetooth_sdp_hdr_overlay {
     bluetooth_sdp_types type;
+    esp_bt_uuid_t       uuid;
     uint32_t            service_name_length;
     char               *service_name;
     int32_t             rfcomm_channel_number;
     int32_t             l2cap_psm;
     int32_t             profile_version;
-} bluetooth_sdp_hdr;
-
-typedef struct _bluetooth_sdp_raw_record {
-    bluetooth_sdp_hdr hdr;
-    esp_bt_uuid_t     uuid;
     int                 user1_ptr_len;
     uint8_t            *user1_ptr;
+    int                 user2_ptr_len; // not used
+    uint8_t            *user2_ptr;     // not used
+} bluetooth_sdp_hdr_overlay;
+
+typedef struct _bluetooth_sdp_raw_record {
+    bluetooth_sdp_hdr_overlay hdr;
 } bluetooth_sdp_raw_record;
 
 typedef struct _bluetooth_sdp_mas_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     uint32_t                  mas_instance_id;
     uint32_t                  supported_features;
     uint32_t                  supported_message_types;
 } bluetooth_sdp_mas_record;
 
 typedef struct _bluetooth_sdp_mns_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     uint32_t                  supported_features;
 } bluetooth_sdp_mns_record;
 
 typedef struct _bluetooth_sdp_pse_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     uint32_t                  supported_features;
     uint32_t                  supported_repositories;
 } bluetooth_sdp_pse_record;
 
 typedef struct _bluetooth_sdp_pce_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
 } bluetooth_sdp_pce_record;
 
 typedef struct _bluetooth_sdp_ops_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     int                       supported_formats_list_len;
     uint8_t                   supported_formats_list[SDP_OPP_SUPPORTED_FORMATS_MAX_LENGTH];
 } bluetooth_sdp_ops_record;
 
 typedef struct _bluetooth_sdp_sap_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
 } bluetooth_sdp_sap_record;
 
 typedef struct _bluetooth_sdp_dip_record {
-    bluetooth_sdp_hdr hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     uint16_t                  vendor;
     uint16_t                  vendor_id_source;
     uint16_t                  product;
@@ -96,7 +102,7 @@ typedef struct _bluetooth_sdp_dip_record {
 } bluetooth_sdp_dip_record;
 
 typedef union {
-    bluetooth_sdp_hdr        hdr;
+    bluetooth_sdp_hdr_overlay hdr;
     bluetooth_sdp_raw_record  raw;
     bluetooth_sdp_mas_record  mas;
     bluetooth_sdp_mns_record  mns;

components/bt/host/bluedroid/btc/profile/std/sdp/btc_sdp.c

@@ -91,11 +91,6 @@ static int get_sdp_record_size(bluetooth_sdp_record* in_record)
         records_size = sizeof(bluetooth_sdp_record);
         break;
 
-    case SDP_TYPE_RAW:
-        if (record->raw.user1_ptr != NULL) {
-            records_size += record->raw.user1_ptr_len;
-        }
-        /* fall through */
     default:
         records_size += sizeof(bluetooth_sdp_record);
         records_size += record->hdr.service_name_length;
@@ -254,12 +249,6 @@ static void copy_sdp_record_common(bluetooth_sdp_record* in_record, bluetooth_sd
         *(free_ptr) = '\0'; // Set '\0' termination of string
         free_ptr++;
     }
-
-    if (in_record->hdr.type == SDP_TYPE_RAW && in_record->raw.user1_ptr != NULL) {
-        out_record->raw.user1_ptr = (UINT8 *)free_ptr;                            // Update pointer
-        memcpy(free_ptr, in_record->raw.user1_ptr, in_record->raw.user1_ptr_len); // Copy content
-        free_ptr += in_record->raw.user1_ptr_len;
-    }
 }
 
 static void copy_sdp_record(bluetooth_sdp_record* in_record, bluetooth_sdp_record* out_record)
@@ -402,6 +391,7 @@ static int add_raw_sdp(const bluetooth_sdp_raw_record *rec)
     UINT8               temp[LEN_UUID_128];
     UINT8*              p_temp = temp;
     UINT32              sdp_handle = 0;
+    const esp_bt_uuid_t *p_uuid = &rec->hdr.uuid;
 
     BTC_TRACE_DEBUG("%s(): scn 0x%02x, psm = 0x%04x\n  service name %s", __func__,
             rec->hdr.rfcomm_channel_number, rec->hdr.l2cap_psm, rec->hdr.service_name);
@@ -411,15 +401,15 @@ static int add_raw_sdp(const bluetooth_sdp_raw_record *rec)
         return sdp_handle;
     }
 
-    if (rec->uuid.len == ESP_UUID_LEN_16) {
+    if (p_uuid->len == ESP_UUID_LEN_16) {
         UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_TWO_BYTES);
-        UINT16_TO_BE_STREAM (p_temp, rec->uuid.uuid.uuid16);
-    } else if (rec->uuid.len == ESP_UUID_LEN_32) {
+        UINT16_TO_BE_STREAM (p_temp, p_uuid->uuid.uuid16);
+    } else if (p_uuid->len == ESP_UUID_LEN_32) {
         UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_FOUR_BYTES);
-        UINT32_TO_BE_STREAM (p_temp, rec->uuid.uuid.uuid32);
-    } else if (rec->uuid.len == ESP_UUID_LEN_128) {
+        UINT32_TO_BE_STREAM (p_temp, p_uuid->uuid.uuid32);
+    } else if (p_uuid->len == ESP_UUID_LEN_128) {
         UINT8_TO_BE_STREAM (p_temp, (UUID_DESC_TYPE << 3) | SIZE_SIXTEEN_BYTES);
-        ARRAY_TO_BE_STREAM (p_temp, rec->uuid.uuid.uuid128, LEN_UUID_128);
+        ARRAY_TO_BE_STREAM (p_temp, p_uuid->uuid.uuid128, LEN_UUID_128);
     } else {
         SDP_DeleteRecord(sdp_handle);
         sdp_handle = 0;
@@ -466,12 +456,12 @@ static int add_raw_sdp(const bluetooth_sdp_raw_record *rec)
         sdp_handle = 0;
         BTC_TRACE_ERROR("%s() FAILED, status = %d", __func__, status);
     } else {
-        if (rec->uuid.len == ESP_UUID_LEN_16) {
-            bta_sys_add_uuid(rec->uuid.uuid.uuid16);
-        } else if (rec->uuid.len == ESP_UUID_LEN_32) {
-            bta_sys_add_uuid_32(rec->uuid.uuid.uuid32);
-        } else if (rec->uuid.len == ESP_UUID_LEN_128) {
-            bta_sys_add_uuid_128((UINT8 *)&rec->uuid.uuid.uuid128);
+        if (p_uuid->len == ESP_UUID_LEN_16) {
+            bta_sys_add_uuid(p_uuid->uuid.uuid16);
+        } else if (p_uuid->len == ESP_UUID_LEN_32) {
+            bta_sys_add_uuid_32(p_uuid->uuid.uuid32);
+        } else if (p_uuid->len == ESP_UUID_LEN_128) {
+            bta_sys_add_uuid_128((UINT8 *)&p_uuid->uuid.uuid128);
         }
         BTC_TRACE_DEBUG("%s():  SDP Registered (handle 0x%08x)", __func__, sdp_handle);
     }
@@ -943,7 +933,7 @@ static int btc_handle_create_record_event(int id)
         switch (record->hdr.type) {
         case SDP_TYPE_RAW:
             sdp_handle = add_raw_sdp(&record->raw);
-            memcpy(&service_uuid, &record->raw.uuid, sizeof(esp_bt_uuid_t));
+            memcpy(&service_uuid, &record->hdr.uuid, sizeof(esp_bt_uuid_t));
             break;
         case SDP_TYPE_MAP_MAS:
             sdp_handle = add_maps_sdp(&record->mas);
@@ -1041,6 +1031,83 @@ static bool btc_sdp_remove_record_event(int id, int *p_sdp_handle)
     return result;
 }
 
+static void btc_sdp_cb_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src)
+{
+    switch (msg->act) {
+    case BTA_SDP_SEARCH_COMP_EVT: {
+        tBTA_SDP_SEARCH_COMP *src_search_comp = (tBTA_SDP_SEARCH_COMP *)p_src;
+        tBTA_SDP_SEARCH_COMP *dest_search_comp = (tBTA_SDP_SEARCH_COMP *)p_dest;
+        int record_count = src_search_comp->record_count;
+
+        for (int i = 0; i < record_count; i++) {
+            bluetooth_sdp_record *src_record = &src_search_comp->records[i];
+            bluetooth_sdp_record *dest_record = &dest_search_comp->records[i];
+            // deep copy service name
+            uint32_t src_service_name_length = src_record->hdr.service_name_length;
+            char *src_service_name = src_record->hdr.service_name;
+            dest_record->hdr.service_name_length = 0;
+            dest_record->hdr.service_name        = NULL;
+            if (src_service_name && src_service_name_length) {
+                char *service_name = (char *)osi_malloc(src_service_name_length + 1);
+                if (service_name) {
+                    memcpy(service_name, src_service_name, src_service_name_length);
+                    service_name[src_service_name_length] = '\0';
+
+                    dest_record->hdr.service_name_length = src_service_name_length;
+                    dest_record->hdr.service_name        = service_name;
+                } else {
+                    BTC_TRACE_ERROR("%s malloc service name failed, orig service name:%s", __func__, src_service_name);
+                }
+            }
+
+            // deep copy user1_ptr fow RAW type
+            int src_user1_ptr_len = src_record->hdr.user1_ptr_len;
+            uint8_t *src_user1_ptr = src_record->hdr.user1_ptr;
+            dest_record->hdr.user1_ptr_len = 0;
+            dest_record->hdr.user1_ptr     = NULL;
+            if (src_record->hdr.type == SDP_TYPE_RAW && src_user1_ptr && src_user1_ptr_len) {
+                uint8_t *user1_ptr = (uint8_t *)osi_malloc(src_user1_ptr_len);
+                if (user1_ptr) {
+                    memcpy(user1_ptr, src_user1_ptr, src_user1_ptr_len);
+
+                    dest_record->hdr.user1_ptr_len = src_user1_ptr_len;
+                    dest_record->hdr.user1_ptr     = user1_ptr;
+                } else {
+                    BTC_TRACE_ERROR("%s malloc user1_ptr failed", __func__);
+                }
+            }
+        }
+
+        break;
+    }
+    default:
+        break;
+    }
+}
+
+static void btc_sdp_cb_arg_deep_free(btc_msg_t *msg)
+{
+    switch (msg->act) {
+    case BTA_SDP_SEARCH_COMP_EVT: {
+        tBTA_SDP_SEARCH_COMP *search_comp = (tBTA_SDP_SEARCH_COMP *)msg->arg;
+        for (size_t i = 0; i < search_comp->record_count; i++) {
+            bluetooth_sdp_record *record = &search_comp->records[i];
+            if (record->hdr.service_name) {
+                osi_free(record->hdr.service_name);
+            }
+
+            if (record->hdr.user1_ptr) {
+                osi_free(record->hdr.user1_ptr);
+            }
+        }
+
+        break;
+    }
+    default:
+        break;
+    }
+}
+
 static void btc_sdp_dm_cback(tBTA_SDP_EVT event, tBTA_SDP* p_data, void* user_data)
 {
     btc_msg_t msg;
@@ -1072,7 +1139,7 @@ static void btc_sdp_dm_cback(tBTA_SDP_EVT event, tBTA_SDP* p_data, void* user_da
     msg.pid = BTC_PID_SDP;
     msg.act = event;
 
-    status = btc_transfer_context(&msg, p_data, sizeof(tBTA_SDP), NULL, NULL);
+    status = btc_transfer_context(&msg, p_data, sizeof(tBTA_SDP), btc_sdp_cb_arg_deep_copy, btc_sdp_cb_arg_deep_free);
 
     if (status != BT_STATUS_SUCCESS) {
         BTC_TRACE_ERROR("%s btc_transfer_context failed", __func__);
@@ -1244,11 +1311,10 @@ static void btc_sdp_search(btc_sdp_args_t *arg)
 
 void btc_sdp_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src)
 {
+    switch (msg->act) {
+    case BTC_SDP_ACT_CREATE_RECORD: {
         bluetooth_sdp_record **dst_record = &((btc_sdp_args_t *)p_dest)->create_record.record;
         bluetooth_sdp_record *src_record = ((btc_sdp_args_t *)p_src)->create_record.record;
-
-    switch (msg->act) {
-    case BTC_SDP_ACT_CREATE_RECORD:
         bluetooth_sdp_record *record = (bluetooth_sdp_record *)osi_calloc(get_sdp_record_size(src_record));
         if (record) {
             copy_sdp_record(src_record, record);
@@ -1259,6 +1325,7 @@ void btc_sdp_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src)
 
         *dst_record = record;
         break;
+    }
     default:
         break;
     }
@@ -1266,15 +1333,15 @@ void btc_sdp_arg_deep_copy(btc_msg_t *msg, void *p_dest, void *p_src)
 
 void btc_sdp_arg_deep_free(btc_msg_t *msg)
 {
+    switch (msg->act) {
+    case BTC_SDP_ACT_CREATE_RECORD: {
         btc_sdp_args_t *arg = (btc_sdp_args_t *)msg->arg;
         bluetooth_sdp_record *record = arg->create_record.record;
-
-    switch (msg->act) {
-    case BTC_SDP_ACT_CREATE_RECORD:
         if (record) {
             osi_free(record);
         }
         break;
+    }
     default:
         break;
     }
@@ -1331,23 +1398,11 @@ void btc_sdp_cb_handler(btc_msg_t *msg)
         sdp_local_param.search_allowed = true;
 
         param.search.status = p_data->sdp_search_comp.status;
-        if (param.search.status == ESP_SDP_SUCCESS) {
         memcpy(param.search.remote_addr, p_data->sdp_search_comp.remote_addr, sizeof(BD_ADDR));
         memcpy(&param.search.sdp_uuid, &p_data->sdp_search_comp.uuid, sizeof(tSDP_UUID));
         param.search.record_count = p_data->sdp_search_comp.record_count;
-            param.search.records = osi_malloc(sizeof(esp_bluetooth_sdp_record_t)*p_data->sdp_search_comp.record_count);
-            if (param.search.records != NULL) {
-                memcpy(param.search.records, p_data->sdp_search_comp.records,
-                        sizeof(esp_bluetooth_sdp_record_t)*p_data->sdp_search_comp.record_count);
-            } else {
-                BTC_TRACE_ERROR("%s %d osi_malloc failed\n", __func__, event);
-                param.search.status = ESP_SDP_NO_RESOURCE;
-            }
-        }
+        param.search.records = (esp_bluetooth_sdp_record_t *)p_data->sdp_search_comp.records;
         btc_sdp_cb_to_app(ESP_SDP_SEARCH_COMP_EVT, &param);
-        if (param.search.records != NULL) {
-            osi_free(param.search.records);
-        }
         break;
     case BTA_SDP_CREATE_RECORD_USER_EVT:
         param.create_record.status = p_data->sdp_create_record.status;
@@ -1372,6 +1427,8 @@ void btc_sdp_cb_handler(btc_msg_t *msg)
         BTC_TRACE_DEBUG("%s: Unhandled event (%d)!", __func__, msg->act);
         break;
     }
+
+    btc_sdp_cb_arg_deep_free(msg);
 }
 
 #endif ///defined BTC_SDP_COMMON_INCLUDED && BTC_SDP_COMMON_INCLUDED == TRUE

components/bt/host/bluedroid/common/include/common/bt_target.h

@@ -1310,7 +1310,7 @@
 #ifdef CONFIG_IDF_TARGET_ESP32
 #define BTM_BLE_ADV_TX_POWER {-12, -9, -6, -3, 0, 3, 6, 9}
 #else
-#define BTM_BLE_ADV_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 21}
+#define BTM_BLE_ADV_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 20}
 #endif
 #endif
 
@@ -1318,7 +1318,7 @@
 #ifdef CONFIG_IDF_TARGET_ESP32
 #define BTM_TX_POWER {-12, -9, -6, -3, 0, 3, 6, 9}
 #else
-#define BTM_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 21}
+#define BTM_TX_POWER {-24, -21, -18, -15, -12, -9, -6, -3, 0, 3, 6, 9, 12, 15, 18, 20}
 #endif
 #endif
 

components/bt/host/bluedroid/device/controller.c

@@ -269,7 +269,7 @@ static void start_up(void)
 #endif //#if (BLE_50_FEATURE_SUPPORT == TRUE)
 
 #if (BLE_50_FEATURE_SUPPORT == TRUE && BLE_42_FEATURE_SUPPORT == FALSE)
-        if (HCI_LE_ENHANCED_PRIVACY_SUPPORTED(controller_param.features_ble.as_array)) {
+        if (HCI_LE_EXT_ADV_SUPPORTED(controller_param.features_ble.as_array)) {
             response = AWAIT_COMMAND(controller_param.packet_factory->make_read_max_adv_data_len());
             controller_param.packet_parser->parse_ble_read_adv_max_len_response(
                 response,

components/bt/host/bluedroid/hci/hci_packet_parser.c

@@ -186,7 +186,9 @@ static void parse_ble_read_resolving_list_size_response(
 {
 
     uint8_t *stream = read_command_complete_header(response, HCI_BLE_READ_RESOLVING_LIST_SIZE, 1 /* bytes after */);
+    if (stream) {
         STREAM_TO_UINT8(*resolving_list_size_ptr, stream);
+    }
 
     osi_free(response);
 }
@@ -198,10 +200,14 @@ static void parse_ble_read_suggested_default_data_length_response(
 {
 
     uint8_t *stream = read_command_complete_header(response, HCI_BLE_READ_DEFAULT_DATA_LENGTH, 2 /* bytes after */);
+    if (stream) {
         STREAM_TO_UINT16(*ble_default_packet_length_ptr, stream);
         STREAM_TO_UINT16(*ble_default_packet_txtime_ptr, stream);
+    }
+
     osi_free(response);
 }
+
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 static void parse_ble_read_adv_max_len_response(
     BT_HDR *response,
@@ -209,8 +215,10 @@ static void parse_ble_read_adv_max_len_response(
 {
 
     uint8_t *stream = read_command_complete_header(response, HCI_BLE_RD_MAX_ADV_DATA_LEN, 1 /* bytes after */);
+    if (stream) {
         // Size: 2 Octets ; Value: 0x001F – 0x0672 ; Maximum supported advertising data length
         STREAM_TO_UINT16(*adv_max_len_ptr, stream);
+    }
 
     osi_free(response);
 }
@@ -254,6 +262,7 @@ static uint8_t *read_command_complete_header(
     STREAM_TO_UINT8(status, stream);
 
     if (status != HCI_SUCCESS) {
+        HCI_TRACE_ERROR("%s failed: opcode 0x%04x, status 0x%02x", __func__, opcode, status);
         return NULL;
     }
 

components/bt/host/bluedroid/stack/include/stack/hcidefs.h

@@ -1871,42 +1871,50 @@ typedef struct {
 #define HCI_PING_SUPPORTED(x) ((x)[HCI_EXT_FEATURE_PING_OFF] & HCI_EXT_FEATURE_PING_MASK)
 
 /*
-**   LE features encoding - page 0 (the only page for now)
+**   LE features encoding - page 0
 */
-/* LE Encryption */
+/* LE Encryption: bit 0 */
 #define HCI_LE_FEATURE_LE_ENCRYPTION_MASK       0x01
 #define HCI_LE_FEATURE_LE_ENCRYPTION_OFF        0
 #define HCI_LE_ENCRYPTION_SUPPORTED(x) ((x)[HCI_LE_FEATURE_LE_ENCRYPTION_OFF] & HCI_LE_FEATURE_LE_ENCRYPTION_MASK)
 
-/* Connection Parameters Request Procedure */
+/* Connection Parameters Request Procedure: bit 1 */
 #define HCI_LE_FEATURE_CONN_PARAM_REQ_MASK       0x02
 #define HCI_LE_FEATURE_CONN_PARAM_REQ_OFF        0
 #define HCI_LE_CONN_PARAM_REQ_SUPPORTED(x) ((x)[HCI_LE_FEATURE_CONN_PARAM_REQ_OFF] & HCI_LE_FEATURE_CONN_PARAM_REQ_MASK)
 
-/* Extended Reject Indication */
+/* Extended Reject Indication: bit 2 */
 #define HCI_LE_FEATURE_EXT_REJ_IND_MASK       0x04
 #define HCI_LE_FEATURE_EXT_REJ_IND_OFF        0
 #define HCI_LE_EXT_REJ_IND_SUPPORTED(x) ((x)[HCI_LE_FEATURE_EXT_REJ_IND_OFF] & HCI_LE_FEATURE_EXT_REJ_IND_MASK)
 
-/* Slave-initiated Features Exchange */
+/* Slave-initiated Features Exchange: bit 3 */
 #define HCI_LE_FEATURE_SLAVE_INIT_FEAT_EXC_MASK       0x08
 #define HCI_LE_FEATURE_SLAVE_INIT_FEAT_EXC_OFF        0
 #define HCI_LE_SLAVE_INIT_FEAT_EXC_SUPPORTED(x) ((x)[HCI_LE_FEATURE_SLAVE_INIT_FEAT_EXC_OFF] & HCI_LE_FEATURE_SLAVE_INIT_FEAT_EXC_MASK)
 
+/* LE Data Packet Length Extension: bit 5 */
+#define HCI_LE_FEATURE_DATA_LEN_EXT_MASK       0x20
+#define HCI_LE_FEATURE_DATA_LEN_EXT_OFF        0
+#define HCI_LE_DATA_LEN_EXT_SUPPORTED(x) ((x)[HCI_LE_FEATURE_DATA_LEN_EXT_OFF] & HCI_LE_FEATURE_DATA_LEN_EXT_MASK)
+
 /* Enhanced privacy Feature: bit 6 */
 #define HCI_LE_FEATURE_ENHANCED_PRIVACY_MASK       0x40
 #define HCI_LE_FEATURE_ENHANCED_PRIVACY_OFF        0
 #define HCI_LE_ENHANCED_PRIVACY_SUPPORTED(x) ((x)[HCI_LE_FEATURE_ENHANCED_PRIVACY_OFF] & HCI_LE_FEATURE_ENHANCED_PRIVACY_MASK)
 
-/* Extended scanner filter policy : 7 */
+/* Extended scanner filter policy: bit 7 */
 #define HCI_LE_FEATURE_EXT_SCAN_FILTER_POLICY_MASK       0x80
 #define HCI_LE_FEATURE_EXT_SCAN_FILTER_POLICY_OFF        0
 #define HCI_LE_EXT_SCAN_FILTER_POLICY_SUPPORTED(x) ((x)[HCI_LE_FEATURE_EXT_SCAN_FILTER_POLICY_OFF] & HCI_LE_FEATURE_EXT_SCAN_FILTER_POLICY_MASK)
 
-/* Slave-initiated Features Exchange */
-#define HCI_LE_FEATURE_DATA_LEN_EXT_MASK       0x20
-#define HCI_LE_FEATURE_DATA_LEN_EXT_OFF        0
-#define HCI_LE_DATA_LEN_EXT_SUPPORTED(x) ((x)[HCI_LE_FEATURE_DATA_LEN_EXT_OFF] & HCI_LE_FEATURE_DATA_LEN_EXT_MASK)
+/*
+**   LE features encoding - page 1
+*/
+/* LE Extended Advertising: bit 12 */
+#define HCI_LE_FEATURE_EXT_ADV_MASK       0x10
+#define HCI_LE_FEATURE_EXT_ADV_OFF        1
+#define HCI_LE_EXT_ADV_SUPPORTED(x) ((x)[HCI_LE_FEATURE_EXT_ADV_OFF] & HCI_LE_FEATURE_EXT_ADV_MASK)
 
 /*
 **   Local Supported Commands encoding

components/bt/host/nimble/Kconfig.in

@@ -65,7 +65,7 @@ config BT_NIMBLE_LOG_LEVEL
 config BT_NIMBLE_MAX_CONNECTIONS
     int "Maximum number of concurrent connections"
     range 1 2 if IDF_TARGET_ESP32C2
-    range 1 70 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5
+    range 1 70 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
     range 1 35 if IDF_TARGET_ESP32H2
     range 1 9
     default 2 if IDF_TARGET_ESP32C2

components/bt/host/nimble/esp-hci/src/esp_nimble_hci.c

@@ -190,6 +190,11 @@ static void controller_rcv_pkt_ready(void)
     }
 }
 
+static void dummy_controller_rcv_pkt_ready(void)
+{
+  /* Dummy function */
+}
+
 void bt_record_hci_data(uint8_t *data, uint16_t len)
 {
 #if (BT_HCI_LOG_INCLUDED == TRUE)
@@ -203,6 +208,12 @@ void bt_record_hci_data(uint8_t *data, uint16_t len)
 #endif // (BT_HCI_LOG_INCLUDED == TRUE)
 }
 
+static int dummy_host_rcv_pkt(uint8_t *data, uint16_t len)
+{
+    /* Dummy function */
+    return 0;
+}
+
 /*
  * @brief: BT controller callback function, to transfer data packet to the host
  */
@@ -264,6 +275,11 @@ static const esp_vhci_host_callback_t vhci_host_cb = {
     .notify_host_recv = host_rcv_pkt,
 };
 
+static const esp_vhci_host_callback_t dummy_vhci_host_cb = {
+    .notify_host_send_available = dummy_controller_rcv_pkt_ready,
+    .notify_host_recv = dummy_host_rcv_pkt,
+};
+
 
 extern void ble_transport_init(void);
 extern esp_err_t ble_buf_alloc(void);
@@ -313,6 +329,8 @@ esp_err_t esp_nimble_hci_deinit(void)
     }
     ble_transport_deinit();
 
+    esp_vhci_host_register_callback(&dummy_vhci_host_cb);
+
     ble_buf_free();
 
 #if MYNEWT_VAL(BLE_QUEUE_CONG_CHECK)

components/bt/host/nimble/nimble

@@ -1 +1 @@
-Subproject commit 6b890f81c0db10ae4757e27eb1312f4232d8fb56
+Subproject commit 62b04f185717f31c57b802d5059e13b0d4d12b0c

components/bt/include/esp32c3/include/esp_bt.h

@@ -386,7 +386,8 @@ typedef enum {
     ESP_PWR_LVL_P12 = 12,             /*!< Corresponding to +12dbm */
     ESP_PWR_LVL_P15 = 13,             /*!< Corresponding to +15dbm */
     ESP_PWR_LVL_P18 = 14,             /*!< Corresponding to +18dbm */
-    ESP_PWR_LVL_P21 = 15,             /*!< Corresponding to  +21dbm */
+    ESP_PWR_LVL_P20 = 15,             /*!< Corresponding to +20dbm */
+    ESP_PWR_LVL_P21 = 15,             /*!< Corresponding to +20dbm, this enum variable has been deprecated */
     ESP_PWR_LVL_INVALID = 0xFF,         /*!< Indicates an invalid value */
 } esp_power_level_t;
 

components/bt/include/esp32c6/include/esp_bt.h

@@ -206,7 +206,9 @@ typedef struct {
     uint8_t cca_drop_mode;                           /*!< CCA drop mode */
     int8_t cca_low_tx_pwr;                           /*!< CCA low transmit power */
     uint8_t main_xtal_freq;                          /*!< Main crystal frequency */
+#if CONFIG_IDF_TARGET_ESP32C6
     uint32_t version_num;                            /*!< Controller configuration version number */
+#endif //CONFIG_IDF_TARGET_ESP32C6
     uint8_t cpu_freq_mhz;                            /*!< CPU frequency in megahertz (MHz) */
     uint8_t ignore_wl_for_direct_adv;                /*!< Ignore the whitelist for direct advertising */
     uint8_t enable_pcl;                              /*!< Enable power control */
@@ -214,6 +216,7 @@ typedef struct {
     uint32_t config_magic;                           /*!< Magic number for configuration validation */
 } esp_bt_controller_config_t;
 
+#if CONFIG_IDF_TARGET_ESP32C6
 #define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {                                           \
     .config_version = CONFIG_VERSION,                                                   \
     .ble_ll_resolv_list_size = CONFIG_BT_LE_LL_RESOLV_LIST_SIZE,                        \
@@ -261,6 +264,54 @@ typedef struct {
     .csa2_select                = DEFAULT_BT_LE_50_FEATURE_SUPPORT,                     \
     .config_magic = CONFIG_MAGIC,                                                       \
 }
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {                                           \
+    .config_version = CONFIG_VERSION,                                                   \
+    .ble_ll_resolv_list_size = CONFIG_BT_LE_LL_RESOLV_LIST_SIZE,                        \
+    .ble_hci_evt_hi_buf_count = DEFAULT_BT_LE_HCI_EVT_HI_BUF_COUNT,                     \
+    .ble_hci_evt_lo_buf_count = DEFAULT_BT_LE_HCI_EVT_LO_BUF_COUNT,                     \
+    .ble_ll_sync_list_cnt = DEFAULT_BT_LE_MAX_PERIODIC_ADVERTISER_LIST,                 \
+    .ble_ll_sync_cnt = DEFAULT_BT_LE_MAX_PERIODIC_SYNCS,                                \
+    .ble_ll_rsp_dup_list_count = CONFIG_BT_LE_LL_DUP_SCAN_LIST_COUNT,                   \
+    .ble_ll_adv_dup_list_count = CONFIG_BT_LE_LL_DUP_SCAN_LIST_COUNT,                   \
+    .ble_ll_tx_pwr_dbm = BLE_LL_TX_PWR_DBM_N,                                           \
+    .rtc_freq = RTC_FREQ_N,                                                             \
+    .ble_ll_sca = CONFIG_BT_LE_LL_SCA,                                                  \
+    .ble_ll_scan_phy_number = BLE_LL_SCAN_PHY_NUMBER_N,                                 \
+    .ble_ll_conn_def_auth_pyld_tmo = BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N,                   \
+    .ble_ll_jitter_usecs = BLE_LL_JITTER_USECS_N,                                       \
+    .ble_ll_sched_max_adv_pdu_usecs = BLE_LL_SCHED_MAX_ADV_PDU_USECS_N,                 \
+    .ble_ll_sched_direct_adv_max_usecs = BLE_LL_SCHED_DIRECT_ADV_MAX_USECS_N,           \
+    .ble_ll_sched_adv_max_usecs = BLE_LL_SCHED_ADV_MAX_USECS_N,                         \
+    .ble_scan_rsp_data_max_len = DEFAULT_BT_LE_SCAN_RSP_DATA_MAX_LEN_N,                 \
+    .ble_ll_cfg_num_hci_cmd_pkts = BLE_LL_CFG_NUM_HCI_CMD_PKTS_N,                       \
+    .ble_ll_ctrl_proc_timeout_ms = BLE_LL_CTRL_PROC_TIMEOUT_MS_N,                       \
+    .nimble_max_connections = DEFAULT_BT_LE_MAX_CONNECTIONS,                            \
+    .ble_whitelist_size = DEFAULT_BT_NIMBLE_WHITELIST_SIZE,                             \
+    .ble_acl_buf_size = DEFAULT_BT_LE_ACL_BUF_SIZE,                                     \
+    .ble_acl_buf_count = DEFAULT_BT_LE_ACL_BUF_COUNT,                                   \
+    .ble_hci_evt_buf_size = DEFAULT_BT_LE_HCI_EVT_BUF_SIZE,                             \
+    .ble_multi_adv_instances = DEFAULT_BT_LE_MAX_EXT_ADV_INSTANCES,                     \
+    .ble_ext_adv_max_size = DEFAULT_BT_LE_EXT_ADV_MAX_SIZE,                             \
+    .controller_task_stack_size = NIMBLE_LL_STACK_SIZE,                                 \
+    .controller_task_prio       = ESP_TASK_BT_CONTROLLER_PRIO,                          \
+    .controller_run_cpu         = 0,                                                    \
+    .enable_qa_test             = RUN_QA_TEST,                                          \
+    .enable_bqb_test            = RUN_BQB_TEST,                                         \
+    .enable_tx_cca              = DEFAULT_BT_LE_TX_CCA_ENABLED,                         \
+    .cca_rssi_thresh            = 256 - DEFAULT_BT_LE_CCA_RSSI_THRESH,                  \
+    .sleep_en                   = NIMBLE_SLEEP_ENABLE,                                  \
+    .coex_phy_coded_tx_rx_time_limit = DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF,     \
+    .dis_scan_backoff           = NIMBLE_DISABLE_SCAN_BACKOFF,                          \
+    .ble_scan_classify_filter_enable         = 1,                                       \
+    .main_xtal_freq             = CONFIG_XTAL_FREQ,                                     \
+    .cpu_freq_mhz               = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,                      \
+    .ignore_wl_for_direct_adv   = 0,                                                    \
+    .enable_pcl                 = DEFAULT_BT_LE_POWER_CONTROL_ENABLED,                  \
+    .csa2_select                = DEFAULT_BT_LE_50_FEATURE_SUPPORT,                     \
+    .config_magic = CONFIG_MAGIC,                                                       \
+}
+#endif
 
 /**
  * @brief       Initialize BT controller to allocate task and other resource.

components/bt/porting/npl/freertos/src/npl_os_freertos.c

@@ -21,6 +21,7 @@
 #include "esp_log.h"
 #include "soc/soc_caps.h"
 #include "esp_bt.h"
+#include "bt_osi_mem.h"
 
 portMUX_TYPE ble_port_mutex = portMUX_INITIALIZER_UNLOCKED;
 
@@ -95,7 +96,7 @@ IRAM_ATTR npl_freertos_event_init(struct ble_npl_event *ev, ble_npl_event_fn *fn
     }
 #else
     if(!ev->event) {
-        ev->event = malloc(sizeof(struct ble_npl_event_freertos));
+        ev->event = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_event_freertos));
     }
 #endif
     event = (struct ble_npl_event_freertos *)ev->event;
@@ -113,7 +114,7 @@ IRAM_ATTR npl_freertos_event_deinit(struct ble_npl_event *ev)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_ev_pool,ev->event);
 #else
-    free(ev->event);
+    bt_osi_mem_free(ev->event);
 #endif
     ev->event = NULL;
 }
@@ -144,7 +145,7 @@ npl_freertos_eventq_init(struct ble_npl_eventq *evq)
     }
 #else
     if(!evq->eventq) {
-        evq->eventq = malloc(sizeof(struct ble_npl_eventq_freertos));
+        evq->eventq = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_eventq_freertos));
         eventq = (struct ble_npl_eventq_freertos*)evq->eventq;
         BLE_LL_ASSERT(eventq);
         memset(eventq, 0, sizeof(*eventq));
@@ -167,7 +168,7 @@ npl_freertos_eventq_deinit(struct ble_npl_eventq *evq)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_evq_pool,eventq);
 #else
-    free((void *)eventq);
+    bt_osi_mem_free((void *)eventq);
 #endif
     evq->eventq = NULL;
 }
@@ -357,7 +358,7 @@ npl_freertos_mutex_init(struct ble_npl_mutex *mu)
     }
 #else
     if(!mu->mutex) {
-        mu->mutex = malloc(sizeof(struct ble_npl_mutex_freertos));
+        mu->mutex = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_mutex_freertos));
         mutex = (struct ble_npl_mutex_freertos *)mu->mutex;
 
         if (!mutex) {
@@ -388,7 +389,7 @@ npl_freertos_mutex_deinit(struct ble_npl_mutex *mu)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_mutex_pool,mutex);
 #else
-    free((void *)mutex);
+    bt_osi_mem_free((void *)mutex);
 #endif
     mu->mutex = NULL;
 
@@ -494,7 +495,7 @@ npl_freertos_sem_init(struct ble_npl_sem *sem, uint16_t tokens)
     }
 #else
     if(!sem->sem) {
-        sem->sem = malloc(sizeof(struct ble_npl_sem_freertos));
+        sem->sem = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_sem_freertos));
         semaphore = (struct ble_npl_sem_freertos *)sem->sem;
 
         if (!semaphore) {
@@ -525,7 +526,7 @@ npl_freertos_sem_deinit(struct ble_npl_sem *sem)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_sem_pool,semaphore);
 #else
-    free((void *)semaphore);
+    bt_osi_mem_free((void *)semaphore);
 #endif
     sem->sem = NULL;
 
@@ -684,7 +685,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 #else
 
     if(!co->co) {
-        co->co = malloc(sizeof(struct ble_npl_callout_freertos));
+        co->co = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_callout_freertos));
         callout = (struct ble_npl_callout_freertos *)co->co;
         if (!callout) {
             return -1;
@@ -704,7 +705,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (esp_timer_create(&create_args, &callout->handle) != ESP_OK) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -713,7 +714,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (!callout->handle) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -761,7 +762,7 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_co_pool,callout);
 #else
-    free((void *)callout);
+    bt_osi_mem_free((void *)callout);
 #endif // OS_MEM_ALLOC
     co->co = NULL;
     memset(co, 0, sizeof(struct ble_npl_callout));
@@ -1089,7 +1090,7 @@ struct npl_funcs_t * npl_freertos_funcs_get(void)
 
 void npl_freertos_funcs_init(void)
 {
-    npl_funcs = (struct npl_funcs_t *)malloc(sizeof(struct npl_funcs_t));
+    npl_funcs = (struct npl_funcs_t *)bt_osi_mem_malloc_internal(sizeof(struct npl_funcs_t));
     if(!npl_funcs) {
         printf("npl funcs init failed\n");
         assert(0);
@@ -1123,7 +1124,7 @@ int npl_freertos_mempool_init(void)
     ble_freertos_total_event_cnt = ble_total_evt_count;
 
     if (ble_total_evt_count) {
-        ble_freertos_ev_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evt_count,
+        ble_freertos_ev_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evt_count,
                                       sizeof (struct ble_npl_event_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_ev_buf) {
@@ -1138,7 +1139,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_evtq_count) {
-        ble_freertos_evq_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evtq_count,
+        ble_freertos_evq_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evtq_count,
                                        sizeof (struct ble_npl_eventq_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_evq_buf) {
@@ -1153,7 +1154,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_co_count) {
-        ble_freertos_co_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_co_count,
+        ble_freertos_co_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_co_count,
                                       sizeof (struct ble_npl_callout_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_co_buf) {
@@ -1168,7 +1169,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_sem_count) {
-        ble_freertos_sem_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_sem_count,
+        ble_freertos_sem_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_sem_count,
                                        sizeof (struct ble_npl_sem_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_sem_buf) {
@@ -1183,7 +1184,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_mutex_count) {
-        ble_freertos_mutex_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_mutex_count,
+        ble_freertos_mutex_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_mutex_count,
                                          sizeof (struct ble_npl_mutex_freertos)) *
                                          sizeof(os_membuf_t));
         if (!ble_freertos_mutex_buf) {
@@ -1200,27 +1201,27 @@ int npl_freertos_mempool_init(void)
     return 0;
 _error:
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
 
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
 
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
 
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
 
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
     return -1;
@@ -1229,23 +1230,23 @@ _error:
 void npl_freertos_mempool_deinit(void)
 {
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
 }
@@ -1253,7 +1254,7 @@ void npl_freertos_mempool_deinit(void)
 void npl_freertos_funcs_deinit(void)
 {
     if (npl_funcs) {
-        free(npl_funcs);
+        bt_osi_mem_free(npl_funcs);
     }
     npl_funcs = NULL;
 }

components/bt/porting/transport/driver/uart/hci_driver_uart.c

@@ -154,7 +154,7 @@ hci_driver_uart_deinit(void)
 
     ESP_ERROR_CHECK(uart_driver_delete(s_hci_driver_uart_env.hci_uart_params->hci_uart_port));
 
-    if (!s_hci_driver_uart_env.tx_sem) {
+    if (s_hci_driver_uart_env.tx_sem) {
         vSemaphoreDelete(s_hci_driver_uart_env.tx_sem);
     }
 

components/driver/test_apps/.build-test-rules.yml

@@ -86,10 +86,6 @@ components/driver/test_apps/touch_sensor_v2:
 components/driver/test_apps/twai:
   disable:
     - if: SOC_TWAI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: test not pass, should be re-enable # TODO: IDF-8966
   depends_filepatterns:
     - components/driver/twai/**/*
   depends_components:

components/driver/test_apps/twai/main/test_twai_interactive.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +16,9 @@
 #include "soc/soc_caps.h"
 #include "esp_log.h"
 
+#define TEST_TWAI_TX_PIN     4
+#define TEST_TWAI_RX_PIN     5
+
 #if CONFIG_TWAI_ISR_IN_IRAM
 static void IRAM_ATTR test_delay_post_cache_disable(void *args)
 {
@@ -27,7 +30,7 @@ TEST_CASE("twai_listen_only", "[twai]")
 {
     twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS();
     twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
-    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(4, 5, TWAI_MODE_LISTEN_ONLY);
+    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(TEST_TWAI_TX_PIN, TEST_TWAI_RX_PIN, TWAI_MODE_LISTEN_ONLY);
 #if CONFIG_TWAI_ISR_IN_IRAM
     g_config.intr_flags |= ESP_INTR_FLAG_IRAM;
 #endif
@@ -60,8 +63,8 @@ TEST_CASE("twai_remote_request", "[twai]")
     twai_handle_t bus_handle;
     twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS();
     twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
-    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(4, 5, TWAI_MODE_NORMAL);
-#if CONFIG_IDF_TARGET_ESP32C6
+    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(TEST_TWAI_TX_PIN, TEST_TWAI_RX_PIN, TWAI_MODE_NORMAL);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
     g_config.controller_id = 1;
 #endif
     TEST_ESP_OK(twai_driver_install_v2(&g_config, &t_config, &f_config, &bus_handle));

components/driver/test_apps/twai/main/test_twai_loop_back.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -99,25 +99,27 @@ TEST_CASE("twai_mode_ext_no_ack_250kbps", "[twai-loop-back]")
         .extd = true, // Extended Frame Format (29bit ID)
     };
 
-    printf("install twai driver\r\n");
     for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
         g_config.controller_id = i;
         g_config.tx_io = i;
         g_config.rx_io = i;
+        printf("install twai driver %d\r\n", g_config.controller_id);
         TEST_ESP_OK(twai_driver_install_v2(&g_config, &t_config, &f_config, &twai_buses[i]));
         TEST_ESP_OK(twai_start_v2(twai_buses[i]));
     }
 
-    printf("transmit message\r\n");
     for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        printf("transmit message from %d\r\n", i);
+        tx_msg.data[5] = SOC_TWAI_CONTROLLER_NUM - i;
         TEST_ESP_OK(twai_transmit_v2(twai_buses[i], &tx_msg, pdMS_TO_TICKS(1000)));
     }
 
-    printf("receive message\r\n");
     twai_message_t rx_msg;
     for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        printf("receive message from %d\r\n", i);
         TEST_ESP_OK(twai_receive_v2(twai_buses[i], &rx_msg, pdMS_TO_TICKS(1000)));
         TEST_ASSERT_TRUE(rx_msg.data_length_code == 6);
+        tx_msg.data[5] = SOC_TWAI_CONTROLLER_NUM - i;
         for (int i = 0; i < 6; i++) {
             TEST_ASSERT_EQUAL(tx_msg.data[i], rx_msg.data[i]);
         }

components/driver/test_apps/twai/pytest_twai.py

@@ -1,12 +1,12 @@
 # SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import logging
 import subprocess
 from time import sleep
 
 import pytest
-from can import Bus, Message
+from can import Bus
+from can import Message
 from pytest_embedded import Dut
 
 
@@ -16,6 +16,7 @@ from pytest_embedded import Dut
 @pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
+@pytest.mark.esp32p4
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
@@ -46,6 +47,7 @@ def fixture_create_socket_can() -> Bus:
 @pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
+@pytest.mark.esp32p4
 @pytest.mark.twai_std
 @pytest.mark.parametrize(
     'config',
@@ -79,6 +81,7 @@ def test_twai_listen_only(dut: Dut, socket_can: Bus) -> None:
 @pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
+@pytest.mark.esp32p4
 @pytest.mark.twai_std
 @pytest.mark.parametrize(
     'config',

components/esp_coex/include/private/esp_coexist_internal.h

@@ -28,6 +28,16 @@ typedef enum {
     COEX_SCHM_CALLBACK_TYPE_I154,
 } coex_schm_callback_type_t;
 
+typedef enum {
+    COEX_SCHM_ST_TYPE_WIFI = 0,
+    COEX_SCHM_ST_TYPE_BLE,
+    COEX_SCHM_ST_TYPE_BT,
+} coex_schm_st_type_t;
+
+#define COEX_STATUS_GET_WIFI_BITMAP     (1 << COEX_SCHM_ST_TYPE_WIFI)
+#define COEX_STATUS_GET_BLE_BITMAP      (1 << COEX_SCHM_ST_TYPE_BLE)
+#define COEX_STATUS_GET_BT_BITMAP       (1 << COEX_SCHM_ST_TYPE_BT)
+
 typedef void (* coex_func_cb_t)(uint32_t event, int sched_cnt);
 typedef esp_err_t (* coex_set_lpclk_source_callback_t)(void);
 typedef void (* coex_wifi_channel_change_cb_t)(uint8_t primary, uint8_t secondary);
@@ -94,9 +104,11 @@ esp_err_t coex_preference_set(coex_prefer_t prefer);
 
 /**
  * @brief Get software coexist status.
+ *
+ * @param bitmap : bitmap of the module getting status.
  * @return : software coexist status
  */
-uint32_t coex_status_get(void);
+uint32_t coex_status_get(uint8_t bitmap);
 
 /**
  * @brief WiFi requests coexistence.

components/esp_coex/lib

@@ -1 +1 @@
-Subproject commit bf7cda7b17a4fd22c123d39748565a68c021e562
+Subproject commit e15e7a161fc1a48e8fb4fd0b3da74623c30ba1cb

components/esp_common/src/esp_err_to_name.c

@@ -469,6 +469,11 @@ static const esp_err_msg_t esp_err_msg_table[] = {
 #   endif
 #   ifdef      ESP_ERR_DPP_AUTH_TIMEOUT
     ERR_TBL_IT(ESP_ERR_DPP_AUTH_TIMEOUT),                       /* 12442 0x309a DPP Auth response was not received in time */
+#   endif
+#   ifdef      ESP_ERR_DPP_INVALID_LIST
+    ERR_TBL_IT(ESP_ERR_DPP_INVALID_LIST),                       /* 12443 0x309b Channel list given in
+                                                                                esp_supp_dpp_bootstrap_gen() is not
+                                                                                valid or too big */
 #   endif
     // components/esp_common/include/esp_err.h
 #   ifdef      ESP_ERR_MESH_BASE

components/esp_https_ota/include/esp_https_ota.h

@@ -239,6 +239,21 @@ esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, es
 int esp_https_ota_get_image_len_read(esp_https_ota_handle_t https_ota_handle);
 
 
+/**
+ * @brief  This function returns the HTTP status code of the last HTTP response.
+ *
+ * @note   This API should be called only after esp_https_ota_begin() has been called.
+ *         This can be used to check the HTTP status code of the OTA download process.
+ *
+ * @param[in]   https_ota_handle   pointer to esp_https_ota_handle_t structure
+ *
+ * @return
+ *    - -1    On failure
+ *    - HTTP status code
+ */
+int esp_https_ota_get_status_code(esp_https_ota_handle_t https_ota_handle);
+
+
 /**
 * @brief  This function returns OTA image total size.
 *

components/esp_https_ota/src/esp_https_ota.c

@@ -724,6 +724,15 @@ esp_err_t esp_https_ota_abort(esp_https_ota_handle_t https_ota_handle)
     return err;
 }
 
+int esp_https_ota_get_status_code(esp_https_ota_handle_t https_ota_handle)
+{
+    esp_https_ota_t *handle = (esp_https_ota_t *) https_ota_handle;
+    if (handle == NULL || handle->http_client == NULL) {
+        return -1;
+    }
+    return esp_http_client_get_status_code(handle->http_client);
+}
+
 int esp_https_ota_get_image_len_read(esp_https_ota_handle_t https_ota_handle)
 {
     esp_https_ota_t *handle = (esp_https_ota_t *)https_ota_handle;

components/esp_hw_support/Kconfig

@@ -273,4 +273,13 @@ menu "Hardware Settings"
     config ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM
         bool
         default n
+
+    config ESP_CLK_RC32K_NOT_TO_USE
+        bool
+        default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
+        default n
+        help
+            Due to the poor low-temperature characteristics of
+            RC32K (it cannot operate below -40 degrees Celsius),
+            please avoid using it whenever possible
 endmenu

components/esp_hw_support/include/esp_crypto_lock.h

@@ -44,7 +44,7 @@ void esp_crypto_ds_lock_acquire(void);
 void esp_crypto_ds_lock_release(void);
 #endif /* SOC_DIG_SIGN_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 /**
  * @brief Acquire lock for the SHA and AES cryptography peripheral.
  *
@@ -56,9 +56,9 @@ void esp_crypto_sha_aes_lock_acquire(void);
  *
  */
 void esp_crypto_sha_aes_lock_release(void);
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
-#if defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA)
+#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
 /**
  * This API should be used by all components which use the SHA, AES, HMAC and DS crypto hardware on the ESP32S2.
  * They can not be used in parallel because they use the same DMA or are calling each other.
@@ -76,7 +76,7 @@ void esp_crypto_dma_lock_acquire(void);
  * Release lock for the AES and SHA cryptography peripherals, which both use the crypto DMA.
  */
 void esp_crypto_dma_lock_release(void);
-#endif /* defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA) */
+#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
 
 #ifdef SOC_MPI_SUPPORTED
 /**

components/esp_hw_support/include/esp_private/sleep_modem.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,7 +120,7 @@ bool modem_domain_pd_allowed(void);
 uint32_t sleep_modem_reject_triggers(void);
 
 /**
- * @brief Configure the parameters of the modem subsytem during the sleep process
+ * @brief Configure the parameters of the modem subsystem during the sleep process
  *
  * In light sleep mode, the wake-up early time of the WiFi module and the TBTT
  * interrupt early time (trigger enabling RF) are determined by the maximum and
@@ -132,7 +132,7 @@ uint32_t sleep_modem_reject_triggers(void);
  *
  * @param max_freq_mhz       the maximum frequency of system
  * @param min_freq_mhz       the minimum frequency of system
- * @param light_sleep_enable ture or false for enable or disable light sleep mode, respectively
+ * @param light_sleep_enable true or false for enable or disable light sleep mode, respectively
  *
  * @return
  *  - ESP_OK on success
@@ -225,6 +225,27 @@ void sleep_modem_wifi_modem_state_deinit(void);
   *   - false not skip light sleep
  */
 bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
+
+/**
+ * @brief Function to initialize and create the modem state phy link
+ * @param link_head the pointer that point to the head of the created phy link
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_NO_MEM if no memory for link
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_init(void **link_head);
+
+/**
+ * @brief Function to destroy and de-initialize modem state phy link
+ * @param link_head the phy link head will be destroyed
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
 #endif
 
 #ifdef __cplusplus

components/esp_hw_support/lowpower/CMakeLists.txt

@@ -24,6 +24,10 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S
     list(APPEND srcs "port/${target}/sleep_clock.c")
 endif()
 
+if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
+    list(APPEND srcs "port/${target}/sleep_modem_state.c")
+endif()
+
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -6,6 +6,7 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/rtc.h"
 #include "modem/modem_syscon_reg.h"
 #include "modem/modem_lpcon_reg.h"
 #include "soc/i2c_ana_mst_reg.h"
@@ -14,13 +15,43 @@ static const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG,  0,               PCR_AHB_DIV_NUM,      1, 0),                                     .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1,               PCR_BUS_CLOCK_UPDATE, 1, 0),                                     .owner = ENTRY(0) | ENTRY(1) },
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+        [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE,        DR_REG_PCR_BASE, 75,                   0, 0, 0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+#endif
     };
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+
+    const static sleep_retention_entries_config_t modem_ahb_config[] = {
+        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
+    };
+    err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
+    uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+    if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
+
+        /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
+         * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
+         * command memory */
+        sleep_retention_entries_config_t bbpll_config[] = {
+            [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
+            [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                          0xffffffff,                   1, 0), .owner = ENTRY(1) },
+            [2] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,     0x1,                          1, 0), .owner = ENTRY(1) },
+            [3] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG,         0,                          MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
+        };
+        extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+        bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config();
+        err = sleep_retention_entries_create(bbpll_config, ARRAY_SIZE(bbpll_config), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+        ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for bbpll configure, 0 level priority");
+    }
 #endif
+
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
 }

components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c

@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0158)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
+#define FECOEX_SET_CHAN_EN              (BIT(17))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+static __attribute__((unused)) const char *TAG = "sleep";
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
+{
+    #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
+
+    static sleep_retention_entries_config_t wifi_modem_config[] = {
+        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
+        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xf3800000,                0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = WIFIMAC_ENTRY() },
+        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = WIFIMAC_ENTRY() },
+        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU to trigger enable RXBLOCK */
+        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU or software to trigger disable RF PHY */
+        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = WIFIMAC_ENTRY() },
+        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1), .owner = WIFIMAC_ENTRY() },
+        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
+        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 1), .owner = WIFIMAC_ENTRY() },
+        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = WIFIMAC_ENTRY() },
+        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
+
+        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+
+        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
+    return ESP_OK;
+}
+#endif
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
+    err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
+    if (err == ESP_OK) {
+        err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
+        if (err == ESP_OK) {
+            *link_head = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00));
+        }
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+    esp_err_t err = ESP_OK;
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    if (err == ESP_OK) {
+        sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    }
+#endif
+    return err;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c

@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/esp_pau.h"
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0154)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
+#define FECOEX_SET_CHAN_EN              (BIT(14))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    static regdma_link_config_t wifi_modem_config[] = {
+        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
+        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
+
+        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
+        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
+        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
+        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
+        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
+        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [9]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
+        [11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
+        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
+        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
+        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
+        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
+
+        /* PMU to trigger enable RXBLOCK */
+        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
+
+        /* PMU or software to trigger disable RF PHY */
+        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
+        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
+        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
+        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
+        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
+        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
+        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
+        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
+
+        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
+        [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+
+        [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
+        [38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[7].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+
+    void *link = NULL;
+    for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
+        void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
+        if (next) {
+            link = next;
+        } else {
+            regdma_link_destroy(link, 0);
+            err = ESP_ERR_NO_MEM;
+        }
+    }
+    if (err == ESP_OK) {
+        pau_regdma_set_modem_link_addr(link);
+        *link_head = link;
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    regdma_link_destroy(link_head, 0);
+#endif
+    return ESP_OK;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/sleep_clock.h"
+#include "soc/pcr_reg.h"
+#include "modem/modem_syscon_reg.h"
+
+static const char *TAG = "sleep_clock";
+
+esp_err_t sleep_clock_system_retention_init(void *arg)
+{
+    const static sleep_retention_entries_config_t pcr_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0),   DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+    };
+
+    esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+    ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+}
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+esp_err_t sleep_clock_modem_retention_init(void *arg)
+{
+    #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
+
+    const static sleep_retention_entries_config_t modem_regs_retention[] = {
+        [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
+    };
+
+    esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
+    ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
+    return ESP_OK;
+}
+#endif
+
+bool clock_domain_pd_allowed(void)
+{
+    const uint32_t inited_modules = sleep_retention_get_inited_modules();
+    const uint32_t created_modules = sleep_retention_get_created_modules();
+    const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
+
+    /* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
+     * through MODEM_SYSCON, when one or more MODEMs are initialized, it is
+     * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
+     * or off. The clock and reset of digital peripherals are managed through
+     * PCR, with TOP domain similar to MODEM domain. */
+    uint32_t modem_clk_dep_modules = 0;
+#if SOC_WIFI_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
+#endif
+#if SOC_BT_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+#if SOC_IEEE802154_SUPPORTED
+    modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
+#endif
+
+    uint32_t mask = 0;
+    if (inited_modules & sys_clk_dep_modules) {
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    }
+    if (inited_modules & modem_clk_dep_modules) {
+#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
+        mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
+#endif
+    }
+    return ((inited_modules & mask) == (created_modules & mask));
+}
+
+ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
+{
+    sleep_retention_module_init_param_t init_param = {
+        .cbs       = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
+
+#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
+    init_param = (sleep_retention_module_init_param_t) {
+        .cbs       = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
+        .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
+    };
+    sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
+#endif
+    return ESP_OK;
+}

components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c

@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "esp_attr.h"
+#include "esp_check.h"
+#include "esp_sleep.h"
+#include "esp_log.h"
+#include "esp_heap_caps.h"
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#include "soc/spi_mem_reg.h"
+#include "esp_private/startup_internal.h"
+
+static const char *TAG = "sleep_mmu";
+
+typedef struct {
+    uint32_t start;
+    uint32_t end;
+} mmu_domain_dev_regs_region_t;
+
+typedef struct {
+    mmu_domain_dev_regs_region_t *region;
+    int region_num;
+    uint32_t *regs_frame;
+} mmu_domain_dev_sleep_frame_t;
+
+/**
+ * Internal structure which holds all requested light sleep mmu retention parameters
+ */
+typedef struct {
+    struct {
+        mmu_domain_dev_sleep_frame_t *mmu_table_frame;
+    } retent;
+} sleep_mmu_retention_t;
+
+static DRAM_ATTR __attribute__((unused)) sleep_mmu_retention_t s_mmu_retention;
+
+static void * mmu_domain_dev_sleep_frame_alloc_and_init(const mmu_domain_dev_regs_region_t *regions, const int region_num)
+{
+    const int region_sz = sizeof(mmu_domain_dev_regs_region_t) * region_num;
+    int regs_frame_sz = 0;
+    for (int num = 0; num < region_num; num++) {
+        regs_frame_sz += regions[num].end - regions[num].start;
+    }
+    void *frame = heap_caps_malloc(sizeof(mmu_domain_dev_sleep_frame_t) + region_sz + regs_frame_sz, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL);
+    if (frame) {
+        mmu_domain_dev_regs_region_t *region = (mmu_domain_dev_regs_region_t *)(frame + sizeof(mmu_domain_dev_sleep_frame_t));
+        memcpy(region, regions, region_num * sizeof(mmu_domain_dev_regs_region_t));
+        void *regs_frame = frame + sizeof(mmu_domain_dev_sleep_frame_t) + region_sz;
+        memset(regs_frame, 0, regs_frame_sz);
+        *(mmu_domain_dev_sleep_frame_t *)frame = (mmu_domain_dev_sleep_frame_t) {
+            .region = region,
+            .region_num = region_num,
+            .regs_frame = (uint32_t *)regs_frame
+        };
+    }
+    return frame;
+}
+
+static inline void * mmu_domain_mmu_table_sleep_frame_alloc_and_init(void)
+{
+    #define MMU_TABLE_SIZE (512 * 4)
+    const static mmu_domain_dev_regs_region_t regions[] = {
+        { .start = SPI_MEM_MMU_ITEM_CONTENT_REG(0), .end = SPI_MEM_MMU_ITEM_CONTENT_REG(0) + MMU_TABLE_SIZE}
+    };
+    return mmu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
+}
+
+static IRAM_ATTR void mmu_domain_dev_regs_save(mmu_domain_dev_sleep_frame_t *frame)
+{
+    assert(frame);
+    mmu_domain_dev_regs_region_t *region = frame->region;
+    uint32_t *regs_frame = frame->regs_frame;
+
+    int offset = 0;
+    for (int i = 0; i < frame->region_num; i++) {
+        for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
+            REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
+            regs_frame[offset++] = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+        }
+    }
+}
+
+static IRAM_ATTR void mmu_domain_dev_regs_restore(mmu_domain_dev_sleep_frame_t *frame)
+{
+    assert(frame);
+    mmu_domain_dev_regs_region_t *region = frame->region;
+    uint32_t *regs_frame = frame->regs_frame;
+
+    int offset = 0;
+    for (int i = 0; i < frame->region_num; i++) {
+        for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
+            REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
+            REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0),regs_frame[offset++]);
+        }
+    }
+}
+
+IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore)
+{
+    if (backup_or_restore) {
+        mmu_domain_dev_regs_save(s_mmu_retention.retent.mmu_table_frame);
+    } else {
+        mmu_domain_dev_regs_restore(s_mmu_retention.retent.mmu_table_frame);
+    }
+}
+
+static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
+{
+    if (s_mmu_retention.retent.mmu_table_frame) {
+        heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame);
+        s_mmu_retention.retent.mmu_table_frame = NULL;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t esp_sleep_mmu_retention_init_impl(void)
+{
+    if (s_mmu_retention.retent.mmu_table_frame == NULL) {
+        void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init();
+        if (frame == NULL) {
+            goto err;
+        }
+        s_mmu_retention.retent.mmu_table_frame = (mmu_domain_dev_sleep_frame_t *)frame;
+    }
+    return ESP_OK;
+err:
+    esp_sleep_mmu_retention_deinit();
+    return ESP_ERR_NO_MEM;
+}
+
+esp_err_t esp_sleep_mmu_retention_init(void)
+{
+    return esp_sleep_mmu_retention_init_impl();
+}
+
+esp_err_t esp_sleep_mmu_retention_deinit(void)
+{
+    return esp_sleep_mmu_retention_deinit_impl();
+}
+
+bool mmu_domain_pd_allowed(void)
+{
+    return (s_mmu_retention.retent.mmu_table_frame != NULL);
+}
+
+ESP_SYSTEM_INIT_FN(sleep_mmu_startup_init, SECONDARY, BIT(0), 108)
+{
+    esp_err_t ret;
+    ret = esp_sleep_mmu_retention_init();
+    if (ret != ESP_OK) {
+        ESP_EARLY_LOGW(TAG, "Failed to enable TOP power down during light sleep.");
+    }
+    return ESP_OK;
+}

components/esp_hw_support/modem_clock.c

@@ -423,7 +423,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
     esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :
@@ -431,7 +431,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
     esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) (
               (src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :
@@ -486,7 +486,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module)
     esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST)  ? ESP_PD_DOMAIN_RC_FAST  :
               (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL    :
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
               (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K)     ? ESP_PD_DOMAIN_RC32K   :
 #endif
               (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K)   ? ESP_PD_DOMAIN_XTAL32K :

components/esp_hw_support/port/esp32c5/Kconfig.rtc

@@ -35,3 +35,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 48 MHz external crystal clock (XTAL) can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 48 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "48 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp32c5/cpu_region_protect.c

@@ -34,44 +34,44 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between debug region & IROM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 2. ROM has configured the ROM region to be cacheable, so we just need to lock the configuration
-    PMA_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_IROM_MASK_LOW, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_DROM_MASK_HIGH, PMA_TOR | PMA_RX);
 
     // 3. Gap between ROM & RAM
-    PMA_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_DROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between DRAM and I_Cache
-    PMA_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(7, SOC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration
     // This function sets invalid regions but this is a valid memory region configuration that could have
     // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA.
     // This entry is also required to be set using PMA because the region needs to be configured as cacheable.
-    PMA_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(9, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
 
     // 6. Gap between D_Cache & LP_RAM
-    PMA_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_DROM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_RTC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 7. Gap between LP memory & peripheral addresses
-    PMA_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(12, SOC_RTC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(13, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
 
     // 8. End of address space
-    PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
-
-    PMA_ENTRY_CFG_RESET(15);
-    PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp32c61/CMakeLists.txt

@@ -17,7 +17,7 @@ if(NOT BOOTLOADER_BUILD)
 
 endif()
 
-# TODO: [ESP32C61] IDF-9250
+# TODO: [ESP32C61] IDF-9304
 if(CONFIG_IDF_TARGET_ESP32C61)
     list(REMOVE_ITEM srcs
         "sar_periph_ctrl.c"

components/esp_hw_support/port/esp32c61/cpu_region_protect.c

@@ -35,34 +35,41 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between debug region & IROM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 3. Gap between ROM & RAM
-    PMA_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_DROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between DRAM and I_Cache
-    PMA_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, SOC_IRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 5. ROM has configured the MSPI region with RX permission, we should add W attribute for psram and lock the configuration
     // This function sets invalid regions but this is a valid memory region configuration that could have
     // been configured using PMP as well, but due to insufficient PMP entries we are configuring this using PMA.
     // This entry is also required to be set using PMA because the region needs to be configured as cacheable.
-    PMA_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_IROM_LOW, (SOC_IROM_HIGH - SOC_IROM_LOW), PMA_NAPOT | PMA_RWX);
 
     // 6. Gap between D_Cache & peripheral addresses
-    PMA_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_DROM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_PERIPHERAL_LOW, PMA_TOR | PMA_NONE);
 
     // 7. End of address space
-    PMA_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_PERIPHERAL_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, UINT32_MAX, PMA_TOR | PMA_NONE);
+
+    PMA_ENTRY_CFG_RESET(12);
+    PMA_ENTRY_CFG_RESET(13);
+    PMA_ENTRY_CFG_RESET(14);
+    PMA_ENTRY_CFG_RESET(15);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h

@@ -10,8 +10,6 @@
 extern "C" {
 #endif
 
-// TODO: IDF-9247
-
 #define PMU_EXT0_WAKEUP_EN          BIT(0)
 #define PMU_EXT1_WAKEUP_EN          BIT(1)
 #define PMU_GPIO_WAKEUP_EN          BIT(2)

components/esp_hw_support/port/esp32c61/private_include/pmu_param.h

@@ -476,12 +476,12 @@ typedef struct pmu_sleep_machine_constant {
         .reset_wait_time_us             = 1,    \
         .power_supply_wait_time_us      = 20,   \
         .power_up_wait_time_us          = 2,    \
-        .regdma_s2m_work_time_us        = 172,  \
-        .regdma_s2a_work_time_us        = 480,  \
-        .regdma_m2a_work_time_us        = 278,  \
-        .regdma_a2s_work_time_us        = 382,  \
-        .regdma_rf_on_work_time_us      = 70,   \
-        .regdma_rf_off_work_time_us     = 23,   \
+        .regdma_s2m_work_time_us        = 270,  \
+        .regdma_s2a_work_time_us        = 666,  \
+        .regdma_m2a_work_time_us        = 296,  \
+        .regdma_a2s_work_time_us        = 586,  \
+        .regdma_rf_on_work_time_us      = 138,  \
+        .regdma_rf_off_work_time_us     = 28,   \
         .xtal_wait_stable_time_us       = 250,  \
         .pll_wait_stable_time_us        = 1     \
     }                                           \

components/esp_hw_support/port/esp32p4/Kconfig.rtc

@@ -37,3 +37,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 40 MHz XTAL can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 40 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "40 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp32p4/cpu_region_protect.c

@@ -38,42 +38,44 @@ static void esp_cpu_configure_invalid_regions(void)
     __attribute__((unused)) const unsigned PMA_RX      = PMA_L | PMA_EN | PMA_R | PMA_X;
     __attribute__((unused)) const unsigned PMA_RWX     = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
 
+    // ROM uses some PMA entries, so we need to clear them before using them in ESP-IDF
+
     // 0. Gap at bottom of address space
-    PMA_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
 
     // 1. Gap between CPU subsystem region & HP TCM
-    PMA_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
 
     // 2. Gap between HP TCM and CPU Peripherals
-    PMA_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
 
     // 3. Gap between CPU Peripherals and I_Cache
-    PMA_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(5, CPU_PERIPH_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(6, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
 
     // 4. Gap between I_Cache and external memory range
-    PMA_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(7, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE);
 
     // 5. Gap between external memory and ROM
-    PMA_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(8, SOC_EXTRAM_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(9, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
 
     // 6. Gap between ROM and internal memory
-    PMA_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE);
-    PMA_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(10, SOC_IROM_MASK_HIGH, PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(11, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
 
     // 7. Gap between internal memory and HP peripherals
-    PMA_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(12, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE);
 
     // 8. Special case - This whitelists the External flash/RAM, HP ROM and HP L2MEM regions and make them cacheable.
     // At the startup, this is done using PMA entry 15 by the ROM code.
-    PMA_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX);
+    PMA_RESET_AND_ENTRY_SET_NAPOT(13, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX);
 
     // 9. Gap between Uncacheable L2 Mem and end of address space
-    PMA_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE);
-    PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE);
+    PMA_RESET_AND_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
 }
 
 void esp_cpu_configure_region_protection(void)

components/esp_hw_support/port/esp32s3/Kconfig.rtc

@@ -37,3 +37,13 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+config RTC_XTAL_CAL_RETRY
+    int "Number of attempts to repeat 32k XTAL calibration"
+    default 3
+    depends on RTC_CLK_SRC_EXT_CRYS
+    help
+        Number of attempts to repeat 32k XTAL calibration
+        before giving up and switching to the internal RC.
+        Increase this option if the 32k crystal oscillator
+        does not start and switches to internal RC.

components/esp_hw_support/port/esp_clk_tree_common.c

@@ -191,7 +191,7 @@ uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
     case SOC_RTC_FAST_CLK_SRC_LP_PLL:
         return clk_ll_lp_pll_get_freq_mhz() * MHZ;
 #endif
-#if SOC_CLK_LP_FAST_SUPPORT_XTAL
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
     case SOC_RTC_FAST_CLK_SRC_XTAL:
         return clk_hal_xtal_get_freq_mhz() * MHZ;
 #endif

components/esp_hw_support/sleep_modem.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,24 +12,19 @@
 #include "esp_log.h"
 #include "esp_attr.h"
 #include "esp_sleep.h"
+#include "esp_check.h"
 #include "soc/soc_caps.h"
 #include "esp_private/pm_impl.h"
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 #include "sdkconfig.h"
 
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA
-#include "modem/modem_syscon_reg.h"
-#include "modem/modem_lpcon_reg.h"
-#include "soc/i2c_ana_mst_reg.h"
-#include "esp_pau.h"
-#endif
-
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
-#include "soc/pmu_reg.h"
-#include "esp_private/esp_pau.h"
 #include "esp_private/esp_pmu.h"
 #endif
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA
+#include "esp_pau.h"
+#endif
 
 static __attribute__((unused)) const char *TAG = "sleep_modem";
 
@@ -136,29 +131,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void)
 
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
 
-#define PMU_RF_PWR_REG                  (0x600b0154)
-#define SARADC_TSENS_REG                (0x6000e058)
-#define SARADC_TSENS_PU                 (BIT(22))
-#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
-#define FECOEX_SET_CHAN_EN              (BIT(14))
-#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
-#define FECOEX_SET_CHAN_DONE            (BIT(8))
-#define FECOEX_AGC_CONF_REG             (0x600a7030)
-#define FECOEX_AGC_DIS                  (BIT(29))
-#define WDEVTXQ_BLOCK                   (0x600A4ca8)
-#define WDEV_RXBLOCK                    (BIT(12))
-#define MODEM_FE_DATA_BASE              (0x600a0400)
-#define MODEM_FE_CTRL_BASE              (0x600a0800)
-
-#define I2C_BURST_VAL(host, start, end) (((host) << 31) | ((end) << 22) | ((start) << 16))
-
-typedef struct {
-    struct {
-        uint8_t start, end; /* the start and end index of phy i2c master command memory */
-        uint8_t host_id;    /* phy i2c master host id */
-    } config[2];
-} phy_i2c_master_command_attribute_t;
-
 typedef struct sleep_modem_config {
     struct {
         void    *phy_link;
@@ -174,76 +146,15 @@ typedef struct sleep_modem_config {
 
 static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 };
 
+
 esp_err_t sleep_modem_wifi_modem_state_init(void)
 {
     esp_err_t err = ESP_OK;
-    phy_i2c_master_command_attribute_t cmd;
-
-    /* get RF on or off configuration info of i2c master command memory */
-    extern void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *);
-    phy_i2c_master_mem_cfg(&cmd);
-
-    ESP_LOGD(TAG, "Modem link i2c master configuration: (%d,%d,%d), (%d,%d,%d)", cmd.config[0].host_id, cmd.config[0].start,
-            cmd.config[0].end, cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-
-    static regdma_link_config_t wifi_modem_config[] = {
-        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
-        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
-
-        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
-        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
-
-        /* PMU or software to trigger enable RF PHY */
-        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
-        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
-        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
-        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
-        [8]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
-        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
-        [10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
-        [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
-        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
-        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
-
-        /* PMU to trigger enable RXBLOCK */
-        [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
-
-        /* PMU or software to trigger disable RF PHY */
-        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
-        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
-        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
-        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
-        [19] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x11), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
-        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
-        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
-        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
-
-        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
-
-        /* PMU to trigger disable RXBLOCK */
-        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
-        [26] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-
-        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
-        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
-    };
-    wifi_modem_config[7].write_wait.value  = I2C_BURST_VAL(cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-    wifi_modem_config[18].write_wait.value = I2C_BURST_VAL(cmd.config[0].host_id, cmd.config[0].start, cmd.config[0].end);
 
     void *link = NULL;
     if (s_sleep_modem.wifi.phy_link == NULL) {
-        for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
-            void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
-            if (next) {
-                link = next;
-            } else {
-                regdma_link_destroy(link, 0);
-                err = ESP_ERR_NO_MEM;
-            }
-        }
+        err = sleep_modem_state_phy_link_init(&link);
         if (err == ESP_OK) {
-            pau_regdma_set_modem_link_addr(link);
             s_sleep_modem.wifi.phy_link = link;
             s_sleep_modem.wifi.flags = 0;
         }
@@ -254,7 +165,7 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
 __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
 {
     if (s_sleep_modem.wifi.phy_link) {
-        regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0);
+        sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link);
         s_sleep_modem.wifi.phy_link = NULL;
         s_sleep_modem.wifi.flags = 0;
     }

components/esp_hw_support/sleep_modes.c

@@ -157,8 +157,8 @@
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
 #elif CONFIG_IDF_TARGET_ESP32C61
-#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (318)
-#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (56)
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (1148) //TODO: PM-231
+#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (107)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
@@ -189,8 +189,12 @@
 #endif
 
 #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+#if CONFIG_IDF_TARGET_ESP32C61
+#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US  (1232)
+#elif CONFIG_IDF_TARGET_ESP32C5
 #define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US  (1220)
 #endif
+#endif
 
 // Minimal amount of time we can sleep for
 #define LIGHT_SLEEP_MIN_TIME_US     200
@@ -705,7 +709,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
 #endif
-#if !CONFIG_IDF_TARGET_ESP32C61
+#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9304
     sar_periph_ctrl_power_enable();
 #endif
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
@@ -2359,7 +2363,7 @@ static uint32_t get_power_down_flags(void)
     }
 #endif
 #if SOC_PM_SUPPORT_RC32K_PD
-#if !SOC_CLK_RC32K_NOT_TO_USE
+#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
     if (s_config.domain[ESP_PD_DOMAIN_RC32K].pd_option != ESP_PD_OPTION_ON) {
         pd_flags |= PMU_SLEEP_PD_RC32K;
     }

components/esp_hw_support/sleep_retention.c

@@ -21,7 +21,7 @@
 #include "sdkconfig.h"
 #include "esp_pmu.h"
 
-#if SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE && CONFIG_IDF_TARGET_ESP32C5 // TODO: PM-202
+#if SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
 #include "soc/pmu_reg.h" // for PMU_DATE_REG, it can provide full 32 bit read and write access
 #endif
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
@@ -506,7 +506,7 @@ static esp_err_t sleep_retention_entries_create_impl(const sleep_retention_entri
             return ESP_ERR_NOT_SUPPORTED;
         }
 #endif
-#if SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE && CONFIG_IDF_TARGET_ESP32C5 // TODO: PM-202
+#if SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
         /* There is a bug in REGDMA wait mode, when two wait nodes need to wait for the
          * same value (_val & _mask), the second wait node will immediately return to
          * wait done, The reason is that the wait mode comparison output logic immediate

components/esp_lcd/test_apps/.build-test-rules.yml

@@ -52,7 +52,3 @@ components/esp_lcd/test_apps/spi_lcd:
     - esp_driver_spi
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: test failed # TODO: ESP32C61 IDF-10953

components/esp_lcd/test_apps/spi_lcd/main/test_spi_board.h

@@ -28,6 +28,13 @@ extern "C" {
 #define TEST_LCD_DC_GPIO        1
 #define TEST_LCD_PCLK_GPIO      2
 #define TEST_LCD_DATA0_GPIO     4
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define TEST_LCD_BK_LIGHT_GPIO  3
+#define TEST_LCD_RST_GPIO       5
+#define TEST_LCD_CS_GPIO        0
+#define TEST_LCD_DC_GPIO        1
+#define TEST_LCD_PCLK_GPIO      2
+#define TEST_LCD_DATA0_GPIO     4
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TEST_LCD_BK_LIGHT_GPIO  23
 #define TEST_LCD_RST_GPIO       6

components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py

@@ -5,7 +5,6 @@ from pytest_embedded import Dut
 
 
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail')    # TODO: [ESP32C61] IDF-10953
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',

components/esp_mm/esp_mmu_map.c

@@ -134,8 +134,8 @@ static void s_reserve_irom_region(mem_region_t *hw_mem_regions, int region_nums)
      * - Now IBUS addresses (between `_instruction_reserved_start` and `_instruction_reserved_end`) are consecutive on all chips,
      *   we strongly rely on this to calculate the .text length
      */
-    extern int _instruction_reserved_start;
-    extern int _instruction_reserved_end;
+    extern char _instruction_reserved_start;
+    extern char _instruction_reserved_end;
     size_t irom_len_to_reserve = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
     assert((mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_instruction_reserved_start)) == irom_len_to_reserve);
 
@@ -162,8 +162,8 @@ static void s_reserve_drom_region(mem_region_t *hw_mem_regions, int region_nums)
     /**
      * Similarly, we follow the way how 1st bootloader load flash .rodata:
      */
-    extern int _rodata_reserved_start;
-    extern int _rodata_reserved_end;
+    extern char _rodata_reserved_start;
+    extern char _rodata_reserved_end;
     size_t drom_len_to_reserve = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
     assert((mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_end) - mmu_ll_vaddr_to_laddr((uint32_t)&_rodata_reserved_start)) == drom_len_to_reserve);
 

components/esp_phy/include/esp_private/phy.h

@@ -13,17 +13,12 @@ extern "C" {
 
 #define ESP_CAL_DATA_CHECK_FAIL 1
 
-typedef enum {
-    PHY_I2C_MST_CMD_TYPE_OFF = 0,
-    PHY_I2C_MST_CMD_TYPE_ON,
-    PHY_I2C_MST_CMD_TYPE_MAX
-} phy_i2c_master_command_type_t;
-
 typedef struct {
+    uint8_t cmd_type;   /* the command type of the current phy i2c master command memory config */
     struct {
         uint8_t start, end; /* the start and end index of phy i2c master command memory */
         uint8_t host_id;    /* phy i2c master host id */
-    } config[PHY_I2C_MST_CMD_TYPE_MAX];
+    } config;
 } phy_i2c_master_command_attribute_t;
 
 /**
@@ -88,13 +83,14 @@ void phy_xpd_tsens(void);
 void phy_init_flag(void);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C6
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
 /**
  * @brief Get the configuration info of PHY i2c master command memory.
  *
- * @param   attr the configuration info of PHY i2c master command memory
+ * @param[out] attr  the configuration info of PHY i2c master command memory
+ * @param[out] size  the count of PHY i2c master command memory configuration
  */
-void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *attr);
+void phy_i2c_master_command_mem_cfg(phy_i2c_master_command_attribute_t *attr, int *size);
 #endif
 
 /**
@@ -217,6 +213,23 @@ void phy_ant_clr_update_flag(void);
  */
 void phy_ant_update(void);
 
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+/**
+ * @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode
+ *
+ * @return  the BBPLL REGDMA configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+
+/**
+ * @brief Get the REGDMA config value of the RF PHY on or off in analog i2c master burst mode
+ *
+ * @param[in] on true for enable RF PHY, false for disable RF PHY.
+ *
+ * @return  the RF on or off configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+#endif
 
 #ifdef __cplusplus
 }

components/esp_phy/lib

@@ -1 +1 @@
-Subproject commit 8608fcf54d51e81f2e74ebf335fa33f61953f7c8
+Subproject commit 1f551c5367daa87a29e0c4f724d6cf809a1841ad