Guillaume Souchere
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6dffac74e9
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heap: Fix IRAM level 2 starting address
The IRAM level 2 address should start at the same address as DRAM level 2 and not DRAM level 3.
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2023-01-06 09:30:36 +00:00 |
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wuzhenghui
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05e37ba214
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esp32h2 memory: update esp32h2 memory layout
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2023-01-06 05:30:24 +00:00 |
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Cao Sen Miao
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4713a9a7f2
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ESP32H2: Introduce new chip target esp32h2, hello_world example supported
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2022-12-29 12:29:14 +08:00 |
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Cao Sen Miao
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86aa4df5b5
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ESP32-H2: Introduce new target for ESP32H2
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2022-11-23 14:38:05 +08:00 |
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laokaiyao
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8677216576
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esp32h2: renaming esp32h2 to esp32h4
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2022-11-08 17:05:33 +08:00 |
|
wuzhenghui
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357490267a
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heap: update esp32c6 memory layout
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2022-09-29 11:13:06 +08:00 |
|
wuzhenghui
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4a86a6a258
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esp32c6: add heap support
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2022-09-26 20:32:13 +08:00 |
|
songruojing
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304a8f142d
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esp32c6: introduce the target
Add esp32c6 target to tools and Kconfig
Create directories and files that are essential for `idf.py --preview set-target esp32c6`
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2022-08-19 11:13:02 +08:00 |
|
wuzhenghui
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65f0b1a821
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bugfix: DCache data memory is dma accessible but not retention dma accessible
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2022-08-03 20:07:39 +08:00 |
|
wuzhenghui
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5e8ba9cea8
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use enum and designated initializers in soc_memory_type define
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2022-07-29 17:07:41 +08:00 |
|
wuzhenghui
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7cb9304b65
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Clean IRAM and DRAM address space conversion macros
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2022-07-29 17:07:39 +08:00 |
|
wuzhenghui
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65aea5d177
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stack/dram is also IRAM0 accessible
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2022-07-29 10:51:48 +08:00 |
|
wuzhenghui
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21a4eda4d4
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Use the entire sharedbuffer space as the heap of the D/IRAM attribute
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2022-07-29 10:51:47 +08:00 |
|
FanhuaCloud
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a1c04ad6fd
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Add missing comma
Add missing comma when CONFIG_ESP32S3_DATA_CACHE_16KB is enabled
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2022-07-27 17:12:17 +08:00 |
|
wuzhenghui
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4652f77a7c
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esp32h2beta2:update rom layout table
|
2022-03-29 14:13:06 +08:00 |
|
Kevin (Lao Kaiyao)
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bf8d4d55d0
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Merge branch 'refactor/rename_esp8684_to_esp32c2' into 'master'
esp8684: rename esp8684 to esp32c2
Closes IDF-4530
See merge request espressif/esp-idf!16745
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2022-01-19 09:08:58 +00:00 |
|
Wang Qi Xiang
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41640e2e03
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heap_init: Adjust the stack/DRAM region size for ESP8684
|
2022-01-19 08:57:54 +00:00 |
|
laokaiyao
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cf049e15ed
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esp8684: rename target to esp32c2
|
2022-01-19 11:08:57 +08:00 |
|
Jing Li
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a0e794b2ca
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heap: adjust the order of RTC memory heap caps and regions
|
2021-12-29 08:49:42 +00:00 |
|
Cao Sen Miao
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a9f0a3531e
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ESP8684: add driver esp_pm heap support
|
2021-11-06 17:33:44 +08:00 |
|
wuzhenghui
|
ca1c4114bc
|
heap: update esp32&s2&c3&h2 soc caps
|
2021-11-04 10:40:57 +08:00 |
|
Alexey Gerenkov
|
111ba5bbe6
|
trax: Adds ESP32-S3 support
|
2021-10-22 23:36:28 +03:00 |
|
Alexey Gerenkov
|
5911eb3f3e
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apptrace: Adds ESP32-S3 support
|
2021-10-22 23:24:00 +03:00 |
|
Li Shuai
|
e8188e5d8f
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ci: replacing old header with new SPDX header style
|
2021-10-20 11:36:23 +08:00 |
|
Li Shuai
|
44da7d27ef
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heap: add a new heap caps attribute for RTC fast memory
|
2021-10-20 11:36:22 +08:00 |
|
Li Shuai
|
9298db641e
|
deep sleep: fix some rtc fast memory definition errors in esp32s3
|
2021-10-19 21:47:27 +08:00 |
|
gaoxiaojie
|
191a494e08
|
support dcache 64Byte and 16k
|
2021-09-02 02:27:40 +08:00 |
|
Michael (XIAO Xufeng)
|
064f12cb90
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idf_size.py: fixed diram counted twice issue, and improve display
Currently static RAM usage are listed under corresponding physical
memory.
ld: fix linker script for C3 and S3
|
2021-08-11 17:51:50 +02:00 |
|
Omar Chebib
|
a7b6ec85b8
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Merge branch 'feature/move_memory_layout_to_heap' into 'master'
G0: Memory layouts are now part of heap components
Closes IDF-1264
See merge request espressif/esp-idf!14028
|
2021-07-19 06:23:19 +00:00 |
|
Omar Chebib
|
c4f57af6c9
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G0: Memory layouts are now part of heap components
|
2021-07-15 11:38:23 +10:00 |
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