alex/esp-idf
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37,206 Commits 20 Branches 148 Tags 384 MiB
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370 Commits

Author SHA1 Message Date
wuzhenghui
3785506ec1
change(esp_driver_gptimer): do gptimer timer target retention by needs 2024-06-13 14:08:34 +08:00
wuzhenghui
ea142bb6d1
change(esp_hw_support): do timergroup watchdogs retention by needs 2024-06-13 14:08:26 +08:00
Song Ruo Jing
bbc44b486e feat(gdma): add GDMA support for ESP32C5 MP 2024-06-12 15:28:40 +08:00
Michael (XIAO Xufeng)
98e99e712f Merge branch 'feature/esp32c5_mp_gpio_support_v5.3' into 'release/v5.3' 
Feature/esp32c5 mp gpio support (v5.3)

See merge request espressif/esp-idf!30884
 2024-06-12 00:51:06 +08:00
morris
65d9300b5c Merge branch 'bugfix/esp32h2_iomux_retention_v5.3' into 'release/v5.3' 
fix(gpio): fix IO 21-27 IOMUX registers not being backed up on ESP32H2 (v5.3)

See merge request espressif/esp-idf!31190
 2024-06-11 10:01:07 +08:00
Song Ruo Jing
8800e9d0e5 fix(gpio): fix IO 21-27 IOMUX registers not being backed up on ESP32H2 2024-05-30 15:13:58 +08:00
Marius Vikhammer
87d4172ee5 feat(ulp): add lp core panic handler 2024-05-30 14:41:31 +08:00
gaoxu
a621402e1f feat(pm): add SOC_PM_SUPPORTED in soc caps 2024-05-16 15:00:22 +08:00
Song Ruo Jing
665883229e fix(gpio_etm): allow one GPIO binds to multiple ETM tasks 2024-04-24 15:58:49 +08:00
wuzhenghui
309725fcd0
feat(esp_hw_support): support esp32p4 clock output 2024-04-17 15:09:49 +08:00
wuzhenghui
101f1abbf1
refactor(esp_hw_support): add hal layer for clock output feature 2024-04-17 14:25:29 +08:00
Konstantin Kondrashov
06c28f0ee9 feat(hal): Adds hal funcs for cpu.c 2024-04-11 13:07:04 +03:00
Cao Sen Miao
0985bfbe27 feat(i2c_master): Add lp_i2c support in i2c master driver 2024-04-03 11:39:04 +08:00
xiehang
f3c5047638 feat(extconn): Supports external WiFi connections for ESP32p4 and other espressf chips 2024-04-01 11:44:52 +08:00
xiehang
9d7bd6a8dd change(esp_phy): Add SOC_PHY_SUPPORTED to control phy mode 2024-04-01 11:36:55 +08:00
Li Shuai
c07be48edb change(esp_hw_support): add adc retention module and it is dependencies on the clock modem 2024-03-30 11:51:52 +08:00
Li Shuai
59115cd2d1 change(esp_hw_support): some system peripherals to use a retention module number 2024-03-29 15:27:08 +08:00
Li Shuai
080d09387c change(esp_hw_support): modify the style of module argument from bitmap to number 2024-03-29 15:22:52 +08:00
wuzhenghui
4a64d2fe2c change(hal): control PAU bus clock by hal layer 2024-03-29 00:36:46 +08:00
wanlei
a307096ec0 spi_master: sct mode supported on c6 2024-03-20 15:42:03 +08:00
Nachiket Kukade
4971764917 feat(esp_wifi): Refactor and improve FTM code 
Enable FTM Responder mode for ESP32C6. Update wifi libs with below -

1. Break FTM State Machine code into separate functions
2. Use dynamic allocation for FTM session to save memory
3. Add API to get FTM report instead of event based mechanism
4. Add FTM Request retry and comeback support

Closes https://github.com/espressif/esp-idf/issues/6810
 2024-03-18 22:01:36 +08:00
laokaiyao
8de41350eb feat(esp32c5mp): support to build g0 components 2024-03-14 15:09:22 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
wuzhenghui
0fc97f0e84
feat(gpio): support LP_IO clock gating management 2024-03-13 11:56:14 +08:00
wuzhenghui
9e8e20227f
feat(system): disable RNG module clock by default for save power 2024-03-12 10:10:41 +08:00
Mahavir Jain
fd6c710b27
fix: cleanup memprot files for C6/H2/P4 
There is no separate permission control peripheral in C6/H2/P4.
Memory protection is achieved using built-in PMA/PMP and hence
removing permission control specific files.
 2024-03-11 17:10:40 +05:30
wuzhenghui
85b246ac88
feat(system): gate the debug clock source by default for esp32c6 and esp32h2 2024-03-07 19:26:39 +08:00
wanlei
0cf11e5b87 feat(spi): add esp32c5 spi support 2024-03-07 18:11:48 +08:00
Guillaume Souchere
0b9f01ac20 feat(soc): Add soc_caps macros for sleep support 
- modify console example to use the new SOC_LIGHT_SLEEP_SUPPORTED
and SOC_DEEP_SLEEP_SUPPORTED macros when registering sleep commands

- remove exclusion of esp32p4 in basic and advanced example in
.build-test-rules.yml

- replace exclusion of esp32p4 for deep and light sleep tests with newly introduced macro

- remove the temporary disable check for esp32p4 and uses the
SOC_LIGHT_SLEEP_SUPPORTED maccro instead.
 2024-03-05 07:05:40 +01:00
C.S.M
0f03434119 Merge branch 'feature/tsens_etm' into 'master' 
feature(temperature sensor): Temperature sensor ETM support.

Closes IDF-6357

See merge request espressif/esp-idf!28880
 2024-03-05 10:09:25 +08:00
Cao Sen Miao
2b2b3be98f feat(temperature_sensor): Add new support for temperature sensor ETM on ESP32C6/H2 2024-03-01 18:52:39 +08:00
gaoxu
7075b61a6a docs(uart): update lp uart and p4/c5 uart programming guide 2024-03-01 16:21:22 +08:00
Song Ruo Jing
98d9f04b00 feat(gdma): add GDMA support for ESP32C5 2024-02-28 12:38:02 +08:00
Cao Sen Miao
cf521b60ea feat(i2c): Support i2c sleep retention on esp32c6/h2 2024-02-23 11:28:14 +08:00
Jiang Jiang Jian
c7a02cbe55 Merge branch 'c6_auto_dbias_master_hsq' into 'master' 
ESP32C6: Active & sleep dbg and dbias get from efuse to fix the voltage

See merge request espressif/esp-idf!27696
 2024-02-22 19:12:28 +08:00
Marius Vikhammer
c0a2043562 fix(system): update reset reasons for C6 and H2 2024-02-20 12:27:09 +08:00
Song Ruo Jing
5276cd4f1d refactor(uart): add support to be able to test LP_UART port 
Increase LP_UART_EMPTY_THRESH_DEFAULT value to 4. The original value
could cause the FIFO become empty before filling next data into the FIFO
when the buadrate is high. TX_DONE interrupt would raise before actual
transmission complete in such case.
 2024-02-07 14:37:48 +08:00
hongshuqing
35918b89a9 feat(pmu): set fix voltage to different mode for esp32c6 & c6 modify brownout rst2 2024-02-04 14:13:23 +08:00
wuzhenghui
0c2f811ca8
feat(esp_hw_support): support gdma register context sleep retention 2024-02-02 11:21:40 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
 2024-01-25 19:15:33 +08:00
Wu Zheng Hui
55f04b3326 Merge branch 'feature/clean_up_retention_context_definitions' into 'master' 
refactor(esp_hw_support): move sleep retention context definition to soc target folder

Closes PM-10

See merge request espressif/esp-idf!26753
 2024-01-24 20:24:02 +08:00
wuzhenghui
f3f12e973c
refactor(esp_hw_support): separate different chip system peripheral regs context defs to target folder 2024-01-23 13:30:01 +08:00
wuzhenghui
9b3dc69908
refactor(esp_hw_support): move regdma structure defination to soc components 2024-01-23 11:51:44 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-22 13:34:32 +08:00
Konstantin Kondrashov
261651fc19 Merge branch 'feature/efuse_update' into 'master' 
feat(efuse): Adds new efuses for H2 and C6 chips

See merge request espressif/esp-idf!27672
 2024-01-20 03:10:44 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
KonstantinKondrashov
ba0842a552 feat(efuse): Adds new efuses for esp32c6 2024-01-16 17:46:50 +08:00
Cao Sen Miao
0bf2b35b33 fix(i2c): Use hardware fsm reset on esp32c6/h2/p4 2024-01-16 10:05:05 +08:00
Kevin (Lao Kaiyao)
83d5797967 Merge branch 'feature/parlio_rx_driver' into 'master' 
driver: add parallel IO RX driver

Closes IDF-7002 and IDF-6984

See merge request espressif/esp-idf!23488
 2023-12-29 16:36:24 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4 
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
 2023-12-29 00:37:26 +08:00