1. Move channel to the first row of the table.
2. Remove the condition of HT20/HT40 for they are determined by
secondary channel.
3. Clean up the CSI table.
Fixed the error division on zero.
Also fixed range CONFIG_ESP32_RTC_CLK_CAL_CYCLES in Kconfig.
Fixed a overflow error by TIMG in the function rtc_clk_cal_internal. This error was due to a limit in values TIMG_RTC_CALI_MAX=0x7FFF (to write the slowclk_cycles) and TIMG_RTC_CALI_VALUE=0x1FFFFFF (to read xtal_cycles). Added assert finctions.
Closes https://github.com/espressif/esp-idf/issues/2147
1. Add reading psram EID.
2. Configure different clock mode for different EID.
3. add API to get psram size and voltage.
4. Remove unnecessary VSPI claim.
For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level.
For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case.
EID for psram:
32MBit 1.8v: 0x20
64MBit 1.8v: 0x26
64MBit 3.3v: 0x46
Since 94250e42a0, UART output is suspended when entering sleep mode
(deep or light sleep). This makes sense for light sleep, where sleep
normally takes small amount of time, and flushing the UART would add
a lot of latency. But this breaks existing behaviour for deep sleep,
where UART output was previously sent out before entering sleep mode.
Closes https://github.com/espressif/esp-idf/issues/2145
remote_ip was declared to be a pointer to an address that was
overwritten in later stage thus changing the address pointed by remote_ip
esp_smartconfig.h : Fixed a typo. station_config to wifi_config_t
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
components/esp32/ipc.c: In function 'esp_ipc_init':
components/esp32/ipc.c:82:31: error: '%d' directive writing between 1 and 11 bytes into a region of size 5 [-Werror=format-overflow=]
sprintf(task_name,"ipc%d",i);
^~
components/esp32/ipc.c:82:27: note: directive argument in the range [-2147483648, 1]
sprintf(task_name,"ipc%d",i);
^~~~~~~
components/esp32/ipc.c:82:9: note: 'sprintf' output between 5 and 15 bytes into a destination of size 8
sprintf(task_name,"ipc%d",i);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
INTERRUPT and CCOUNT registers will change outside of program control.
Making the inline assembly used to read these registers volatile
indicates this fact to the compiler.
Fixes https://github.com/espressif/esp-idf/issues/2127
1. fix BLE connection missing in coex mode
2. modify other parameters to make coex priority more reasonable
3. fix modem sleep procedure trap cause Wifi disable RF when BT is
working. Such cause that BR/EDR is difficult to be connected, BLE
connection stability decrease and so on.
4. modify BR/EDR coexist duration to imrove BR/EDR connect success
ratio.
5. Due to the hardware coexist bug, BLE scan interval/window should
be less than 0x100(about 160ms). Therefore, it will cause BLE cannot
scan any advertising packet while WiFi have higher priority
behaviour(such like RX beacon, scan, TX/RX VO packets and etc.).
1. add APIs to set/get announce interval values.
2. add API to enable/disable the min rate to 6Mbps for data packages.
3. add APIs to set/get RSSI threshold values.
4. fix ap_loss.
Since commit 94250e4, EXT0 wakeup mechanism, when wakeup level was set
to 0, started waking up chip immediately after entering deep sleep.
This failure was triggered in that commit by a change of
RTC_CNTL_MIN_SLP_VAL (i.e. minimum time in sleep mode until wakeup
can happen) from 128 cycles to 2 cycles.
The reason for this behaviour is related to the way input enable (IE)
signal going into an RTC pad is obtained:
PAD_IE = (SLP_SEL) ? SLP_IE & CHIP_SLEEP : IE,
where SLP_IE, SLP_SEL, and IE are bits of an RTC_IO register related
to the given pad. CHIP_SLEEP is the signal indicating that chip has
entered sleep mode.
The code in prepare_ext{0,1}_wakeup did not enable IE, but did enable
SLP_SEL and SLP_IE. This meant that until CHIP_SLEEP went high, PAD_IE
was 0, hence the input from the pad read 0 even if external signal
was 1. CHIP_SLEEP went high on the 2nd cycle of sleep. So when
RTC_CNTL_MIN_SLP_VAL was set to 2, the input signal from the pad was
latched as 0 at the moment when CHIP_SLEEP went high, causing EXT0
wakeup with level 0 to trigger.
This commit changes the way PAD_IE is enabled: SLP_SEL and SLP_IE are
no longer used, and IE is set to 1. If EXT0 wakeup is used, RTC_IO is
not powered down, so IE signal stays 1 both before CHIP_SLEEP goes
high and after. If EXT1 wakeup is used, RTC_IO may be powered down.
However prepare_ext1_wakeup enables Hold on the pad, locking states
of all the control signals, including IE.
Closes https://github.com/espressif/esp-idf/issues/1931
Closes https://github.com/espressif/esp-idf/issues/2043
Previously the loop in esp_timer_impl_set_alarm was necessary to catch
the case when timer count wraps around (goes from 2^32 - 1 to 0).
Since ALARM_OVERFLOW_VAL was reduced from 2^32 - 1 to 0xefffffff,
this is no longer necessary.
Fixes https://github.com/espressif/esp-idf/issues/1891
Allows you to move the partition table, it gives more space for the bootloader.
Added a new utility - parttool.py. This utility can search for the offset and/or size of the partitions by name and type/subtype. Use for getting APP_OFFSET and PHY_DATA_OFFSET.
The linker(esp32.bootloader.ld) made changes that allow you to write a custom bootloader code more.
TW14125
Before entering the deep sleep, the RTC and FRC counters are synchronized. Updating the boot_time.
Added a unit test for this case.
Fixed warnings for MULTIPLE_STAGES
Closes https://github.com/espressif/esp-idf/issues/1840
1. Fix the WiFi/BT coexist bug
2. Fix WPA2 enterprise example crash bug
3. Add size and version check for crypto type struct
4. Add MD5 check for crypto type header file
1. add mesh_assoc_t to esp_mesh_internal.h file.
2. rename "node" to "device" in esp_mesh.h.
3. add MESH_EVENT_SCAN_DONE event.
4. add APIs esp_mesh_scan_get_ap_record() and esp_mesh_scan_get_ap_ie_len() to get scan results.
5. modify API esp_mesh_set_self_organized() by adding parameter "select_parent".
6. modify API esp_mesh_set_parent() by adding parameter "parent_mesh_id"
7. add manual networking example.
1. Store the calibration data to NVS if PHY does full calibration because of calibration data checksum failure
2. Pass the station's mac to PHY for checksum calculation
A new method of workaround an error with DPORT is to ensure that the APB is read and followed by the DPORT register without interruptions and pauses. This fix places this implementation in the IRAM to exclude errors associated with the cache miss.
Add error handling for http client
set ssid password correct with Example_WIFI test, and clear password before free
Fixed the CI failure due to HTTP errror names
1. provide options for bluetooth low power mode
2. provide two options for bluetooth low power clock: main XTAL and external 32kHz XTAL
3. provide function and callbacks to control bluetooth low power mode, including enable/disable sleep, software wakeup request, low power clock settings, check power state, etc
4. modify vhci API vhci_host_send_packet to use blocking mode
5. note that DFS and bluetooth modem sleep can not be used together currently.
Added .rtc_noinit and .noinit section definitions into linker file /esp32/ld/esp32.common.ld.
The macro __NOINIT_ATTR, RTC_NOINIT_ATTR declared in esp32/esp_attr.h file.
Added unit test file to test added behavior for noinit variables and its attributes.
Added documentation changes for new added attributes.
Make some corrections after code review:
The linker file has been corrected to place noinit section before bss_start to make it safer.
Documentation file has been modified to clarify reset behavior of allocated data .
Corrected typos in test_noinit.c and removed assertion of noinit variable to avoid possible issues with ROM boot loader memory allocation.
The linker file has been corrected to place noinit section before bss_start to make it safer.
Documentation file has been modified to clarify reset behavior of allocated data .
Corrected typos in test_noinit.c and removed assertion of noinit variable to avoid possible issues with ROM boot loader memory allocation.
Update test_noinit.c file to address RTCWDT_RTC_RESET reset reason instead of POWERON_RESET.
Test optimized to pass automated unit testing.
esp32: Add .noinit and .rtc_noinit sections to the linker script
Update of general-notes.rst documentation to fomat examples as code and attributes as identifiers.
Test test_noinit.c corrected to pass automated testing (support ofTEST_CASE_MULTIPLE_STAGES())
https://ezredmine.espressif.cn:8765/issues/15878
1. remove rc when ap not found
closes issue: https://github.com/espressif/esp-idf/issues/1797
2. allocate mimo packet to internal memory
3. use FRC2 timer instead of WDEV_NOW() for modem sleep to calculate
TBTT time.
It fixes the bug that TBTT will be incorrect if beacon is lost.
If the RTC crystal is bad or has no matched capacitance, then you do not need to start such the crystal. It is necessary to determine this case, output an error (about impossibility to start from the oscillator) and start from the internal RC of the chain.
Reduced the default value of the number of bootstrap cycles. Because we can oscillating the oscillator which then stops. (in Kconfig). Changed from 100 to 5.
The number of calibration cycles has been increased. It is the main criterion for estimating the launch of an oscillator. A large increase leads to an increase in the load time, as well as the stability of recognition of this case. (in Kconfig).
Changed from 1024 to 3000.
When two CPUs read the area of the DPORT and the area of the APB, the result is corrupted for the CPU that read the APB area.
And another CPU has valid data.
The method of eliminating this error.
Before reading the registers of the DPORT, make a preliminary reading of the APB register.
In this case, the joint access of the two CPUs to the registers of the APB and the DPORT is successful.
If the allocated interrupt list is not empty and the new item will be inserted
as the header of the list, insert_vector_desc() causes crash because pre is
null. This commit fix this issue.
change some API function to throw event:
esp_wifi_deauth_sta
esp_wifi_get_country
esp_wifi_ap_get_sta_list
esp_wifi_sta_get_ap_info
esp_wifi_stop
esp_wifi_get_channel
esp_wifi_get_protocol
esp_wifi_get_bandwidth
When light sleep is started, the other CPU gets halted using DPORT
stall mechanism. This can happen while it is inside an esp_timer
critical section, which may lead to a deadlock. This change adds
functions to take and release esp_timer lock before entering
DPORT critical section, preventing the deadlock.
1. Add error log if failed to store calibration version/mac/data
2. Change the NVS calibration version/mac/data store sequence
3. Pass the init_data instead of NULL to esp_phy_rf_init() in esp_phy_load_cal_and_init()
* Philosophical: "explicit is better than implicit".
* Practical: Allows useful errors if invalid directories given in components as the defaults aren't
always used. Also trims the -I path from a number of components that have no actual include
directory.
* Simplifies knowing which components will be header-only and which won't
1. Bootloader reads SPI configuration from bin header, so that the burning configuration can be different with compiling configuration.
2. Psram mode init will overwrite original flash speed mode, so that users can change psram and flash speed after OTA. 3. Flash read mode(QIO/DIO…) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
4. Add read flash ID function, and save flash ID in g_rom_flashchip
5. Set drive ability for all related GPIOs
6. Check raise VDDSDIO voltage in 80Mhz mode
7. Add check flash ID and update settings in bootloader
8. Read flash ID once and keep in global variable
9. Read flash image header once and reuse the result
Tested cases:
1. Test new and old version of bootloader
boot Flash 20M —> app Flash 80M + Psram 80M
boot Flash 40M —> app Flash 80M + Psram 80M
boot Flash 80M —> app Flash 80M + Psram 80M
boot Flash 20M —> app Flash 80M + Psram 40M
boot Flash 40M —> app Flash 80M + Psram 40M
boot Flash 80M —> app Flash 80M + Psram 40M
boot Flash 20M —> app Flash 40M + Psram 40M
boot Flash 40M —> app Flash 40M + Psram 40M
boot Flash 80M —> app Flash 40M + Psram 40M 2. Working after esp_restart reboot.
* Move smartconfig to its component directory, it should be possible to override
this as whole component
* Fix few header includes related to lwIP networking stack
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
1. fix issues on sending beacon caused by too much tx retries on other packets.
2. modify not to scan if rc exists when connect.
3. modify scan dwell time to default 120ms fo root.
1. fix a bug in initliazing map beacon interval.
2. fix not send MESH_EVENT_ROUTING_TABLE_REMOVE when MESH_NWK_CHILD_DISCONNECTED.
3. fix a bug in returning roots ie len.
The files updated according to code review discussions.
In the sleep_modes.c removed immidiate disable of ULP mode and leave just trigger deactivation.
The esp_sleep.h is updated to have the same defines for source as esp_sleep_wakeup_cause_t.
Updated documentation in sleep_modes.rst file to include cross references and address esp_sleep_wakeup_cause_t type.
The get_time_ms() is updated to explicitly use fabs(dt) instead of abs(dt) in test_sleep.c.
Some other minor changes in test_sleep.c unit test.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
It is not possible to generate 1 MHz REF_TICK from 2 MHz APB clock
(this is a limitation of REF_TICK divider circuit). Since switching
REF_TICK frequency is something we would like to avoid (to maintain
UART output even with DFS), 2 MHz frequency has been marked as
unsupported.
The issue would manifest itself in cases when switching from PM
configuration like {active=160MHz, idle=80MHz} to {active=80MHz,
idle=80Mhz}. After the configuration was changed, PM logic would
think that current frequency was 80MHz and would not do any further
switching. In fact, frequency was still 160MHz.
The old code calculated MAX() of two enum values, but CPU frequency
enum values are not ordered (2MHz goes after 240MHz). This caused
incorrect configuration to be set.
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start.
2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else).
3. Added a unit test to test a new method of oscillation an external crystal.
4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency.
The new method eliminates these errors.
Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc`
- 8 Test starting external RTC crystal. Will pass.
`Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100.
QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted.
Closes TW19143
- separate mode stats from lock stats by an extra comment line
- add CPU frequency column to the mode stats
- don’t print a row for light sleep if light sleep is not enabled
s_cpu_freq_by_mode array was statically initialised with 80MHz CPU
frequency in CPU_MAX and APB_MAX modes, but sdkconfig setting for the
CPU frequency could have been different. For the case of 240MHz CPU
frequency, this would cause a frequency switch between 240MHz and
80MHz to happen, even though such switch is not supported in the fast
path switching functions used by the DFS implementation.
This fixes the issue by moving initialisation into esp_pm_impl_init,
which is called at startup before the first mode switch can happen.
Fixes https://github.com/espressif/esp-idf/issues/1729.
The files updated according to code review discussions.
In the sleep_modes.c removed immidiate disable of ULP mode and leave just trigger deactivation.
The esp_sleep.h is updated to have the same defines for source as esp_sleep_wakeup_cause_t.
Updated documentation in sleep_modes.rst file to include cross references.
Some minor changes in test_sleep.c unit test.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
Added function esp_sleep_disable_wakeup_source() to deactivate wakeup trigger for selected source.
Updated documentation for this function in sleep_modes.rst file.
Updated unit test to check this functionality for light sleep.
The test_sleep.c unit test is updated to add reliability for unit testing.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
The timer wakeup function once activated cannot be disabled later using existing api. If user wants to use different wakeup sources after first sleep but it does not work. This change disables timer wakeup trigger in configuration that will be set into appropriate RTC registers in esp_light_sleep_start() function.
Added function esp_sleep_disable_wakeup_source() to deactivate wakeup trigger for selected source.
Updated documentation for this function in sleep_modes.rst file to pass make html.
Updated unit test to check this functionality for light sleep.
The test_sleep.c unit test is updated to add reliability for auto unit testing.
(TW#18952)
Closes https://github.com/espressif/esp-idf/issues/1677
tools/gen_esp_err_to_name.py generates
components/esp32/esp_err_to_name.c for lookup of the error codes from
all of the IDF project and easily identify all codes in one place
1. Put some lwip udp rx/tx relating functions to IRAM
2. Put some wifi rx/tx relating functions to IRAMa
3. Reduce wifi dynamic malloc from 4 to 1 for each ebuf
4. Update iperf example accordingly
5. Update libphy.a to v383
close github issue#1037 WiFi Promiscuous filter breaks w/
WIFI_PROMIS_FILTER_MASK_ALL and issue#1404
esp_wifi_set_promiscuous_filter set WIFI_PROMIS_FILTER_MASK_ALL error
When INT WDT fires, panicHandler is invoked. In OCD mode, panicHandler
sets a breakpoint on the PC from the exception frame and returns.
However in case of INT WDT, interrupt flag is still set in TIMERG1
peripheral, which causes INT WDT to trigger again. This causes an
endless stream of "Core 0 panic'ed (Interrupt wdt timeout on CPU1)"
messages. OpenOCD also gets terribly confused at this point.
Disable watchdogs when exiting panic handler in OCD mode.
Clear TIMERG1 WDT interrupt flag to prevent re-entry into panic handler.
libc time function now rely on esp_timer_get_time as the source of
high-resolution time, rather than FRC1 timer. Internally, on the ESP32
esp_timer implementation uses FRC2 timer.
- Change help text and labels in Kconfig to use "high-resolution timer"
instead of FRC1. Keep existing Kconfig option name to be backwards
compatible.
- Change references to "FRC1" in the source code to "FRC".
A function to change "in IRAM" status for an existing interrupt handle, without going through free/allocate of the interrupt.
mOS HW timer implementation requires this to make HW timers safe to re-set from an IRAM ISR.
1. Add a hide API for station to receive and process probe request
frame.
2. Fix an issue that wifi/bt coexistence crashes in PSRAM version.
3. Fix an issue that the API for clearing vendor ie can not work.
4. Fix an issue that wifi stop and reboot leads watchdog.
Timer callback can delete the timer. If CONFIG_ESP_TIMER_PROFILING was
enabled, this caused an access to invalid (freed) memory.
This fix adds a pointer to track the timer while executing the callback.
This is needed so that we can check if callback deletes the timer,
in which case we won't try updating profiling counters for this timer
after the callback is done.
Renamed the internal rc to __err_rc to avoid clashes with local variables.
This code would not do the expected thing with the original ESP_ERROR_CHECK macro:
esp_err_t my_func(esp_err_t x)
{
assert(x == 23);
}
esp_err_t rc = 23; //some value that is important fo the user
ESP_ERROR_CHECK(my_func(rc));
The macro will expand to:
esp_err_t rc = (my_func(rc));
And the code will assert, as my_func will receive a random value - whatever is in the internal macro rc temp variable. This is due to the C weirdness of allowing this code:
int x = x; //x has a random value.
This commit reverts the revert on the new task watchdog API. It also
fixes the following bug which caused the reversion.
- sdkconfig TASK_WDT_TIMEOUT_S has been reverted from the unit of ms back to the
unit of seconds. Fixes bug where projects using the new API without rebuilding sdkconfig
would cause the old default value of 5 to be interpreted in ms.
This commit also adds the following features to the task watchdog
- Updated idle hook registration to be compatible with dual core hooks
- Updated dual core hooks to support deregistration for cpu
- Legacy mode has been removed and esp_task_wdt_feed() is now replaced by
esp_task_wdt_reset(). esp_task_wdt_feed() is deprecated
- Idle hooks to reset are now registered/deregistered when the idle tasks are
added/deleted from the Task Watchdog instead of at Task Watchdog init/deinit
- Updated example
1. V366, fix a problem which initialize current can reach 800mA.
2. V365, fix a problem for pll_cap tracking in Coexist (BT & WIFI)
mode. The problem will make Coexist (BT & WIFI) WIFI AP mode TX
Fail in high temperature(>70).
3. V364, fix a bug of BT and Wifi coexist (hung in function of
force_wifi_mode())
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
