alex/esp-idf
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31,447 Commits 20 Branches 148 Tags 384 MiB
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1913 Commits

Author SHA1 Message Date
Jiang Jiang Jian
487adc09f4 Merge branch 'change/change_regdma_power_issue_macro_v5.1' into 'release/v5.1' 
change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG (backport v5.1)

See merge request espressif/esp-idf!27991
 2023-12-21 11:27:10 +08:00
Marius Vikhammer
40bea117e4 Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1' 
soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)

See merge request espressif/esp-idf!27136
 2023-12-20 10:00:39 +08:00
Lou Tianhao
1419db4b91 change(pm): change macro SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG 2023-12-19 11:44:23 +08:00
Mahavir Jain
fa7383162f Merge branch 'fix/esp32s3_soc_drom_high_addr_v5.1' into 'release/v5.1' 
fix(soc): esp32s3/Fix the DROM_HIGH_ADDR (v5.1)

See merge request espressif/esp-idf!27822
 2023-12-17 16:31:41 +08:00
morris
eb7022dd06 Merge branch 'contrib/github_pr_12559_v5.1' into 'release/v5.1' 
fix(spi): Correct REG_SPI_BASE(i) macro for all targets (GitHub PR) (v5.1)

See merge request espressif/esp-idf!27714
 2023-12-14 11:08:03 +08:00
Aditya Patwardhan
f62e7fd4e8
fix(soc): esp32s3/Fix the DROM_DROM_HIGH limit 
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
    convers only 16 MB of address range. But esp32s3 supports 32 MB
    external memory. So this address should be 0x3E000000
 2023-12-11 12:17:31 +05:30
Mahavir Jain
ca02c6d274 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets_v5.1' into 'release/v5.1' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2 (v5.1)

See merge request espressif/esp-idf!27684
 2023-12-08 12:01:36 +08:00
harshal.patil
6a990a37ce
fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-12-07 11:42:00 +05:30
gaoxu
6190b3f7c9 fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-12-06 10:19:52 +00:00
wanlei
3486cf1b60 fix(spi): correct some signals and dummy bits docs 2023-12-06 16:15:23 +08:00
TD-er
8e0d64e94c fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-12-06 16:13:01 +08:00
harshal.patil
c040a614a9
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy 2023-12-05 21:08:48 +05:30
Darian Leung
411405355d refactor(soc): SOC_USB_PERIPH_NUM option 
This commit refactors SOC_USB_PERIPH_NUM as follows:

- Renamed to SOC_USB_OTG_PERIPH_NUM to avoid confusion with USB Serial JTAG
- Updated to unsigned integer "1U"
- Updated some build rules to depend on SOC_USB_OTG_SUPPORTED instead
 2023-11-28 22:00:30 +01:00
Shu Chen
ecbbd3c3d9 Merge branch 'backport/add_ot_radio_stats_enable_config_5_1' into 'release/v5.1' 
feat(openthread): backport some openthread features(BackportV5.1)

See merge request espressif/esp-idf!26885
 2023-11-22 12:23:53 +08:00
Aditya Patwardhan
514cd783a3 Merge branch 'bugfix/esp32h2_ecdsa_hardware_k_v5.1' into 'release/v5.1' 
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose (v5.1)

See merge request espressif/esp-idf!27271
 2023-11-21 13:57:38 +08:00
Jiang Jiang Jian
0e1ec38785 Merge branch 'bugfix/fix_lightsleep_current_leakage_on_usj_pad_v5.1' into 'release/v5.1' 
fix(esp_hw_support): fix lightsleep current leakage on usb pad (backport v5.1)

See merge request espressif/esp-idf!27205
 2023-11-21 10:51:11 +08:00
Mahavir Jain
0ccfa4b0c2
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose 
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
 2023-11-20 16:03:29 +05:30
Jiang Jiang Jian
5719d882d1 Merge branch 'bugfix/fix_onebyte_watchpoint_setting_v5.1' into 'release/v5.1' 
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting (v5.1)

See merge request espressif/esp-idf!27215
 2023-11-20 17:37:03 +08:00
morris
1b3713f7cd Merge branch 'feature/support_adc_calibration_on_h2_v5.1' into 'release/v5.1' 
adc_cali: supported adc calibration v1 on ESP32H2 (v5.1)

See merge request espressif/esp-idf!26963
 2023-11-17 16:41:00 +08:00
morris
ddb6d22468 Merge branch 'feature/gpio_dump_io_info_v5.1' into 'release/v5.1' 
feat(gpio): add a dump API to dump IO configurations (v5.1)

See merge request espressif/esp-idf!26870
 2023-11-17 16:30:22 +08:00
wuzhenghui
eb45eec5db
change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 20:40:03 +08:00
wuzhenghui
6ae596c764
fix(esp_hw_support): fix lightsleep current leakage on usb-phy controlled pad 2023-11-16 20:03:30 +08:00
Ivan Grokhotkov
c43b66cd35
fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency 2023-11-14 14:27:24 +01:00
Ivan Grokhotkov
6fa2080706
fix(soc): correct SOC_IROM_MASK_HIGH for esp32s3 
Fixes corrupted backtraces on S3 when a function is in ROM.

Closes https://github.com/espressif/esp-idf/issues/11512
 2023-11-14 14:27:23 +01:00
Jiang Jiang Jian
0172c33818 Merge branch 'bugfix/fix_deinit_init_wifi_scan_fail_issue_v5.1' into 'release/v5.1' 
Bugfix/fix deinit init wifi scan fail issue v5.1(Backport v5.1)

See merge request espressif/esp-idf!27064
 2023-11-14 15:25:54 +08:00
gaoxu
c5e107c53d feat(adc_cali): Add ADC calibration support for ESP32H2 2023-11-13 03:04:03 +00:00
muhaidong
666ba33829 fix(wifi): fix deinit init wifi scan fail issue 2023-11-10 11:15:38 +08:00
KonstantinKondrashov
d9b776c59a feat(efuse): Adds efuse ADC calibration data for ESP32H2 2023-11-07 15:41:59 +08:00
Song Ruo Jing
4892c481b5 feat(gpio): add a dump API to dump IO configurations 
Merges https://github.com/espressif/esp-idf/pull/12511
 2023-11-03 16:21:31 +08:00
Lou Tianhao
9b3e40c9d1 feat(pm/deepsleep): Support EXT1_WAKEUP_MODE_PER_PIN 2023-11-03 11:02:56 +08:00
Jiang Jiang Jian
1aabb5f0d5 Merge branch 'bugfix/revert_pvt_v5.1' into 'release/v5.1' 
Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2" (v5.1)

See merge request espressif/esp-idf!26485
 2023-10-18 10:44:14 +08:00
Erhan Kurubas
754b2a0de1 fix(interrupts): reorder esp32s3 irq names to align with the respective irq numbers 2023-10-16 22:20:45 +02:00
zlq
17c2931309 feat(bootloader): adjust dbias of bootloader, change clock of H2 to 64 
MHz
 2023-10-16 14:35:45 +08:00
Xiao Xufeng
81dcc61008 Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2" 
This reverts commit b221f87e00.
 2023-10-16 14:35:41 +08:00
morris
0f51501495 Merge branch 'bugfix/h2_i2c1_no_signal_v5.1' into 'release/v5.1' 
fix(i2c): I2C port 1 doesn't work on esp32h2 (backport v5.1)

See merge request espressif/esp-idf!26459
 2023-10-16 14:13:23 +08:00
Cao Sen Miao
ae604cbbdd fix(i2c): I2C port 1 doesn't work on esp32h2 2023-10-13 15:57:18 +08:00
wuzhenghui
49013a0560 feat(modem_clock): separate management of modem_adc_common_fe clock and modem_private_fe 2023-09-28 16:24:39 +00:00
Jiang Jiang Jian
1adcaf7f99 Merge branch 'feature/support_7.6.1_soc/pvt_auto_dbias_v5.1' into 'release/v5.1' 
rtc: auto adjust HP LDO voltage using pvt function(backport 5.1)

See merge request espressif/esp-idf!25995
 2023-09-28 13:35:00 +08:00
alanmaxwell
9337525cdc fix(phy): Fix PHY enabled enter WiFi RX state default 2023-09-27 14:55:25 +08:00
zlq
7bbe19d92f feat(volt): chip auto adjust volt for esp32c6 & esp32h2 2023-09-27 06:39:59 +00:00
cjin
179e3293be change: remove has clock bug macro for esp32h2 2023-09-25 13:40:26 +08:00
hongshuqing
bb33a2bf6b fix cpu switches freq bug s2s3 to v5.1 2023-09-19 11:27:08 +08:00
Marius Vikhammer
41a291fee0 fix(wdt): changed WDT clock source to XTAL for C6/H2 
Previously it used PLL, but PLL could potentially be powered down by power-management
when CPU frequency changed.
 2023-09-13 10:45:51 +08:00
Marius Vikhammer
c192ea478e fix(wdt): changed ESP32-C3 WDT to use XTAL as clock 
This clock is unchanged even when CPU/APB frequency changes (e.g. due to esp_pm),
which means timeout period is correct even after such a change.
 2023-09-13 10:45:49 +08:00
Jiang Jiang Jian
9eceef649b Merge branch 'bugfix/esp32h2_update_desc_ecdsa_workmode_v5.1' into 'release/v5.1' 
fix(soc/esp32h2): Update the description of the ECDSA_WORK_MODE (backport v5.1)

See merge request espressif/esp-idf!25818
 2023-09-08 16:09:42 +08:00
Jiang Guang Ming
9ed6944c0d fix(soc/esp32h2): Update the description of the ECDSA_WORK_MODE 2023-09-07 10:34:36 +08:00
wuzhenghui
d3bfaf8f5f feat(esp_hw_support): manage modem_etm clock in modem_clock for bt/154 indepently 2023-09-06 15:48:37 +08:00
Jiang Jiang Jian
b58706c1d2 Merge branch 'feature/support_hp_regi2c_for_esp32c6_v5.1' into 'release/v5.1' 
feat(esp_rom): support hp regi2c for esp32c6(backport v5.1)

See merge request espressif/esp-idf!25644
 2023-08-31 10:49:58 +08:00
wuzhenghui
05cd295a28 fix(esp_rom): fix esp32c6, esp32h2 hp_regi2c ops data conflict with phy ops 2023-08-30 14:28:55 +08:00
Lou Tianhao
d2730608d2 feature(esp_rom): support_hp_regi2c_for_esp32c6 2023-08-30 14:28:37 +08:00