Commit Graph

110 Commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
0adb814af3 Merge branch 'bugfix/fix_memory_miss_bug_esp32c3_esp32s3' into 'master'
ESP32C3/ESP32S3: Fix cpu crash bug  when wakeup from lightsleep for memory data miss

Closes IDF-162 and IDF-4923

See merge request espressif/esp-idf!17823
2022-05-18 12:05:08 +08:00
Michael (XIAO Xufeng)
adcdcbaa0e Merge branch 'feat/pm_dbias_refactoring' into 'master'
pm: refactoring dbias related code

See merge request espressif/esp-idf!17994
2022-05-17 14:42:16 +08:00
chaijie
cc0a5a4edb solve memory error bug when in lightsleep mode 2022-05-16 11:43:00 +08:00
Michael (XIAO Xufeng)
6f507d527c rtc: fixed 8MD256 can't be used as RTC slow src on ESP32
Sync configuration from other chips

Closes: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089
2022-05-14 22:35:41 +08:00
Michael (XIAO Xufeng)
234628b3ea pm: putting dbias and pd_cur code into same function 2022-05-14 02:35:11 +08:00
Michael (XIAO Xufeng)
2905cbbe03 pm: fixed RTC8M domain power issues
introduced in e44ead5356

1. The int8M power domain config by default is PD. While LEDC is using
RTC8M as clock source, this power domain will be kept on.

But when 8MD256 is used as RTC clock source, the power domain should
also be kept on.

On ESP32, there was protection for it, but broken by commit
e44ead5356. Currently the power domain
will be forced on when LEDC is using RTC8M as clock source &&
!int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise
the power domain will be powered off, regardless of RTC clock source.

In other words, int8M domain will be forced off (even when 8MD256
used as RTC clock source) if LEDC not using RTC8M as clock source, user
doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep.

On later chips, there's no such protection, so 8MD256 could't be used as
RTC clock source in sleep modes.

This commit adds protection of 8MD256 clock to other chips. Fixes the
incorrect protection logic overriding on ESP32. Now the power domain
will be determiend by the logic below (order by priority):

    1. When RTC clock source uses 8MD256, power up
    2. When LEDC uses RTC8M clock source, power up
    3. In deepsleep, power down
    4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M,
       power down by default. (This is preferred to have highest
       priority, but it's kept as is because of current code structure.)

2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the
protection above may force the int8m PU. This may cause the inconsistent
of dbias and the int8m PU status.

This commit lifts the logic of pd int8m/xtal fpu logic to upper layer
(sleep_modes.c).

Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089

temp
2022-05-11 11:30:47 +08:00
sly
117c30e835 fix S3 bbpll calibrate fail bug in high temperature 2022-04-25 16:41:04 +08:00
Marius Vikhammer
45c1d1cba2 Merge branch 'feature/move_target_kconfig_2' into 'master'
system: move kconfig options out of target component

See merge request espressif/esp-idf!17321
2022-04-24 13:29:43 +08:00
jingli
252a4eceb4 fix rtc mem load err(since the voltage of rtc regulator is too low) 2022-04-21 23:38:16 +08:00
Marius Vikhammer
d2872095f9 soc: moved kconfig options out of the target component.
Moved the following kconfig options out of the target component:
 * CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
 * ESP*_REV_MIN -> esp_hw_support
 * ESP*_TIME_SYSCALL -> newlib
 * ESP*_RTC_* -> esp_hw_support

Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
2022-04-21 12:09:43 +08:00
Armando (Dou Yiwen)
5bb59b00e7 Merge branch 'feature/support_bss_on_psram' into 'master'
psram: support .bss on psram on esp32s3

Closes IDF-4814, IDF-4396, IDFGH-7148, and IDFGH-7153

See merge request espressif/esp-idf!17557
2022-04-20 11:16:28 +08:00
Armando
f8249550f8 psram: support .bss on psram on esp32s3 2022-04-19 19:48:00 +08:00
songruo
60bb5c913d clk_tree: prework of introducing clk subsystem control
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
   upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
   Modify the NGed drivers to adopt new clock ids
2022-04-11 12:09:06 +08:00
Michael (XIAO Xufeng)
aab535fe4a Merge branch 'bugfix/regi2c_ctrl_spinlock_s2' into 'master'
hw_support: fixed regi2c not protected by lock on ESP32S2

See merge request espressif/esp-idf!16653
2022-03-13 02:47:53 +08:00
Michael (XIAO Xufeng)
d5bdf95580 hw_support: fixed regi2c not protected by lock on ESP32S2 2022-03-13 00:24:08 +08:00
Armando (Dou Yiwen)
6ed3ffbbf1 Merge branch 'refactor/remove_redundant_rom_cache_dependency' into 'master'
cache: remove redundant rom cache dependency in bootloader

Closes IDF-4523

See merge request espressif/esp-idf!17077
2022-03-12 10:11:39 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
laokaiyao
93b162c767 touch: fix the touch sensor wait cycle on s3 2022-03-08 09:11:14 +00:00
Sudeep Mohanty
a9fda54d39 esp_hw_support/esp_system: Re-evaluate header inclusions and include directories
This commit updates the visibility of various header files and cleans up
some unnecessary inclusions. Also, this commit removes certain header
include paths which were maintained for backward compatibility.
2022-03-07 11:18:08 +05:30
Armando
494b996ecc sleep: restore analog calibration registers after waking up from light sleep
Closes https://github.com/espressif/esp-idf/issues/8287
Closes https://github.com/espressif/esp-idf/issues/7921
2022-03-04 12:10:20 +08:00
Omar Chebib
dbba26643f RTC WDT: refactor code to remove duplicated code 2022-03-03 13:47:22 +08:00
morris
869bed1bb5 soc: don't expose unstable soc header files in public api 2022-01-06 23:10:22 +08:00
Jakob Hasse
64a355eba8 feat (bootloader): added rng sampling
Set maximum RNG query frequency to save value known from tests
2021-12-27 13:59:20 +08:00
Martin Vychodil
dd938eb952 System/Security: Memprot API unified (ESP32C3)
Unified Memory protection API for all PMS-aware chips (ESP32C3)

Closes JIRA IDF-3849
2021-12-21 01:50:36 +01:00
Michael (XIAO Xufeng)
b23ed0ee81 Merge branch 'feature/update_adc_cali_due_to_efuse_version_change' into 'master'
adc: update s3 adc calibration efuse version

Closes IDF-4069

See merge request espressif/esp-idf!15843
2021-12-14 07:27:35 +00:00
Armando
9a6f894046 psram: add octal psram ECC feature 2021-12-13 20:24:52 +08:00
Armando
021e8817cf psram: make psram wrap mode unavailable 2021-12-13 20:19:32 +08:00
Armando
bfb2a264c6 adc: update adc calibration efuse version
ADC calibration scheme and algorithm are not changed. Only the eFuse bit BLOCK1_VERSION is changed. This MR updated the logic to recognize the adc efuse version
2021-12-13 13:00:13 +08:00
Simon
6f9b89f619 Merge branch 'bugfix/usb_no_rom_log' into 'master'
USB_SERIAL_JTAG: Fix the issue that there is no rom/bootloader log when restarting

Closes IDF-4173

See merge request espressif/esp-idf!16057
2021-12-07 08:16:10 +00:00
Cao Sen Miao
17ea9d7faf USB_SERIAL_JTAG: Fix the issue that there is no rom log when restarting 2021-11-29 20:26:09 +08:00
jingli
0ea1825f64 reduce bootup time when using usb-serial-jtag 2021-11-29 17:21:11 +08:00
morris
16677b0d3c global: make periph enable/disable APIs private
peripheral enable/disable usually should be managed by driver itself,
so make it as espressif private APIs, not recommended for user to use it
in application code.
However, if user want to re-write the driver or ports to other platform,
this is still possible by including the header in this way:
"esp_private/peripheral_ctrl.h"
2021-11-08 10:37:47 +08:00
Armando
c331c85318 mspi: make cpu clock source switch safe
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
2021-10-19 21:47:27 +08:00
wuzhenghui
5000aa877f fix rtc_clk_cal: Wait for timeout in a loop instead of just judge once 2021-10-19 12:07:34 +08:00
wuzhenghui
ab9df9945f fix stuck in rtc_clk_cal 2021-10-14 16:25:54 +08:00
Li Shuai
73829221f5 esp_hw_support: force power down wifi and bt power domain when rtc module init 2021-10-14 10:51:10 +08:00
Armando
16a91399f1 psram: put opiram_psram and spiram_psram in internal ram
External memory is accessed via SPI0. When modifying the SPI0 registers,
should put the code in internal RAM. Otherwise when there is an ongoing
SPI0 transaction, CPU changes the SPI0 registers. This is dangerous.
Besides, modifying SPI0 registers may lead external memory to an
unstable state. Therefore putting these code in internal RAM is
necessary.
2021-10-08 17:39:41 +08:00
Armando
7ff9332243 rtc: fix mspi timing issue when self-calibrate ocode
When doing OCode self-calibration in rtc_init.c, it will change the
system clock from PLL to XTAL, which is in a lower frequency, and MSPI
timing tuning is not needed. Therefore we should modify the timing
configurations accordingly, and set it back after the calibration.

This is a temporary fix
2021-10-08 15:59:57 +08:00
Armando
4cafdbd83b mspi: fix psram cs timing register setting not in iram bug 2021-10-08 15:59:57 +08:00
Armando
2655a506c9 mspi: support auto detect octal flash vendor 2021-10-08 15:59:57 +08:00
Jiang Jiang Jian
f5ae8b0533 Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master'
support RTC8M and XTAL power domain in light sleep mode

Closes IDF-3419

See merge request espressif/esp-idf!15152
2021-09-27 04:02:29 +00:00
Jiang Jiang Jian
a015123a1d Merge branch 'feature/rename_apbctrl_to_syscon' into 'master'
rename apbctrl to syscon

See merge request espressif/esp-idf!14524
2021-09-16 12:58:07 +00:00
Wu Zheng Hui
1080e4f6a2 rename APB_CTRL ro SYS_CON
save
2021-09-16 20:57:57 +08:00
Armando (Dou Yiwen)
b9ea273e78 Merge branch 'feature/suppport_self_icode_calibration_on_s3' into 'master'
adc: support self calibration icode on s3

Closes IDF-3913

See merge request espressif/esp-idf!15195
2021-09-16 11:14:58 +00:00
Armando
ddd0235783 adc: support adc self-calibration on esp32s3 2021-09-16 15:17:29 +08:00
Li Shuai
b3e27403f3 esp_hw_support: keep external 40 MHz xtal related analog circuit power on during sleep 2021-09-16 14:46:21 +08:00
Li Shuai
58292a7d22 Power Management: add XTAL power domain to control whether external 40MHz xtal is powered down during sleep 2021-09-16 14:43:43 +08:00
Li Shuai
f5b39a7cde esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-16 14:40:46 +08:00
Li Shuai
b59902f4d1 Merge branch 'bugfix/esp32s3_lightsleep_psram_leakage_current' into 'master'
fix SPIRAM leakage when its CS pin has no hardware pullup

See merge request espressif/esp-idf!14730
2021-09-16 04:07:58 +00:00
Armando
ea10dacf68 mspi: add octal psram get_cs_io function 2021-09-15 20:34:18 +08:00