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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/esp32s3_lightsleep_psram_leakage_current' into 'master'
fix SPIRAM leakage when its CS pin has no hardware pullup See merge request espressif/esp-idf!14730
This commit is contained in:
commit
b59902f4d1
@ -119,6 +119,15 @@ bool bootloader_common_label_search(const char *list, char *label);
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*/
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void bootloader_configure_spi_pins(int drv);
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/**
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* @brief Get flash CS IO
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*
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* Can be determined by eFuse values, or the default value
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*
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* @return Flash CS IO
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*/
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uint8_t bootloader_flash_get_cs_io(void);
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/**
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* @brief Calculates a sha-256 for a given partition or returns a appended digest.
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*
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@ -23,6 +23,7 @@
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#include "esp_rom_crc.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_efuse.h"
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#include "esp_flash_partitions.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_common.h"
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@ -191,8 +192,19 @@ void bootloader_common_vddsdio_configure(void)
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#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
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}
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RESET_REASON bootloader_common_get_reset_reason(int cpu_no)
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{
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return (RESET_REASON)esp_rom_get_reset_reason(cpu_no);
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}
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uint8_t bootloader_flash_get_cs_io(void)
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{
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uint8_t cs_io;
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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cs_io = SPI_CS0_GPIO_NUM;
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} else {
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cs_io = (spiconfig >> 18) & 0x3f;
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}
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return cs_io;
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}
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@ -33,5 +33,22 @@ menu "Hardware Settings"
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config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
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bool
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default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
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bool "PSRAM leakage current workaround in light sleep"
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depends on SPIRAM
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help
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When the CS pin of SPIRAM is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of SPIRAM has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
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bool "Flash leakage current workaround in light sleep"
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help
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When the CS pin of Flash is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of Flash has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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endmenu
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endmenu
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@ -85,6 +85,15 @@ size_t esp_spiram_get_size(void);
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*/
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void esp_spiram_writeback_cache(void);
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/**
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* @brief get psram CS IO
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*
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* This interface should be called after PSRAM is enabled, otherwise it will
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* return an invalid value -1/0xff.
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*
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* @return psram CS IO or -1/0xff if psram not enabled
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*/
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uint8_t esp_spiram_get_cs_io(void);
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/**
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@ -70,6 +70,15 @@ size_t esp_spiram_get_size(void);
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*/
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void esp_spiram_writeback_cache(void);
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/**
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* @brief get psram CS IO
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*
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* This interface should be called after PSRAM is enabled, otherwise it will
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* return an invalid value -1/0xff.
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*
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* @return psram CS IO or -1/0xff if psram not enabled
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*/
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uint8_t esp_spiram_get_cs_io(void);
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/**
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@ -79,6 +79,16 @@ void esp_spiram_writeback_cache(void);
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*/
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bool esp_spiram_is_initialized(void);
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/**
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* @brief get psram CS IO
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*
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* This interface should be called after PSRAM is enabled, otherwise it will
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* return an invalid value -1/0xff.
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*
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* @return psram CS IO or -1/0xff if psram not enabled
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*/
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uint8_t esp_spiram_get_cs_io(void);
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/**
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* @brief Reserve a pool of internal memory for specific DMA/internal allocations
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*
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@ -316,4 +316,8 @@ bool esp_spiram_is_initialized(void)
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return spiram_inited;
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}
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uint8_t esp_spiram_get_cs_io(void)
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{
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return psram_get_cs_io();
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}
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#endif
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@ -195,6 +195,13 @@ typedef struct {
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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static uint8_t s_psram_cs_io = (uint8_t)-1;
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uint8_t psram_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
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{
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int i;
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@ -839,6 +846,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
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abort();
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}
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s_psram_cs_io = psram_io.psram_cs_io;
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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@ -63,6 +63,13 @@ psram_size_t psram_get_size(void);
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*/
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esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
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/**
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* @brief get psram CS IO
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*
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* @return psram CS IO
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*/
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uint8_t psram_get_cs_io(void);
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#ifdef __cplusplus
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}
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#endif
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@ -377,6 +377,11 @@ bool esp_spiram_is_initialized(void)
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return spiram_inited;
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}
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uint8_t esp_spiram_get_cs_io(void)
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{
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return psram_get_cs_io();
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}
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
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@ -415,4 +420,5 @@ bool esp_spiram_test(void)
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return true;
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}
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}
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#endif
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@ -160,6 +160,13 @@ static uint32_t s_psram_id = 0;
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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static uint8_t s_psram_cs_io = (uint8_t)-1;
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uint8_t psram_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
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{
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if (mode == PSRAM_CMD_QPI) {
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@ -367,6 +374,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio();
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}
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esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
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s_psram_cs_io = psram_io.psram_cs_io;
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}
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psram_size_t psram_get_size(void)
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@ -68,5 +68,11 @@ typedef enum {
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esp_err_t esp_spiram_wrap_set(spiram_wrap_mode_t mode);
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/**
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* @brief get psram CS IO
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*
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* @return psram CS IO
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*/
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uint8_t psram_get_cs_io(void);
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#endif
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@ -38,7 +38,7 @@
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#define OCT_PSRAM_ADDR_BITLEN 32
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#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
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#define OCT_PSRAM_CS1_IO 26
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#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO
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#define OCT_PSRAM_CS_SETUP_TIME 3
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#define OCT_PSRAM_CS_HOLD_TIME 3
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@ -102,6 +102,11 @@ static const char* TAG = "opi psram";
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static DRAM_ATTR psram_size_t s_psram_size;
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static void IRAM_ATTR s_config_psram_spi_phases(void);
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uint8_t IRAM_ATTR psram_get_cs_io(void)
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{
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return OCT_PSRAM_CS1_IO;
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}
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/**
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* Initialise mode registers of the PSRAM
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*/
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@ -224,7 +229,7 @@ static void IRAM_ATTR s_init_psram_pins(void)
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//Set cs1 pin function
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], FUNC_SPICS1_SPICS1);
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//Set mspi cs1 drive strength
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PIN_SET_DRV(IO_MUX_GPIO26_REG, 3);
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PIN_SET_DRV(GPIO_PIN_MUX_REG[OCT_PSRAM_CS1_IO], 3);
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//Set psram clock pin drive strength
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
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}
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@ -329,4 +329,9 @@ bool esp_spiram_is_initialized(void)
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return s_spiram_inited;
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}
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uint8_t esp_spiram_get_cs_io(void)
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{
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return psram_get_cs_io();
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}
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#endif
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@ -121,6 +121,13 @@ static uint32_t s_psram_id = 0;
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static void IRAM_ATTR config_psram_spi_phases(void);
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extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
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static uint8_t s_psram_cs_io = (uint8_t)-1;
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uint8_t psram_get_cs_io(void)
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{
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return s_psram_cs_io;
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}
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static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
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{
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if (mode == PSRAM_CMD_QPI) {
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@ -301,6 +308,7 @@ static void IRAM_ATTR psram_gpio_config(void)
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esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
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}
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s_psram_cs_io = cs1_io;
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//WP HD
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uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
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@ -68,5 +68,11 @@ typedef enum {
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esp_err_t esp_spiram_wrap_set(spiram_wrap_mode_t mode);
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/**
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* @brief get psram CS IO
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*
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* @return psram CS IO
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*/
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uint8_t psram_get_cs_io(void);
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#endif
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@ -19,6 +19,15 @@
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#include "driver/gpio.h"
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#include "esp_private/gpio.h"
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#include "esp_private/sleep_gpio.h"
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#include "bootloader_common.h"
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#ifdef CONFIG_IDF_TARGET_ESP32
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#include "esp32/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/spiram.h"
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#endif
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static const char *TAG = "sleep";
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@ -53,6 +62,12 @@ void esp_sleep_config_gpio_isolate(void)
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gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
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}
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}
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#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
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gpio_sleep_set_pull_mode(esp_spiram_get_cs_io(), GPIO_PULLUP_ONLY);
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#endif
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#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
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gpio_sleep_set_pull_mode(bootloader_flash_get_cs_io(), GPIO_PULLUP_ONLY);
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#endif
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}
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void esp_sleep_enable_gpio_switch(bool enable)
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