Commit Graph

349 Commits

Author SHA1 Message Date
Zim Kalinowski
1fd56e0b87 Merge branch 'feature/systimer_generate_rtos_tick' into 'master'
freertos(esp32s3): SysTick uses systimer

Closes IDF-2613

See merge request espressif/esp-idf!12246
2021-08-04 12:33:52 +00:00
Konstantin Kondrashov
29f581fc70 freertos(esp32s3): SysTick uses systimer 2021-08-04 20:33:44 +08:00
Armando (Dou Yiwen)
03fb3973a2 Merge branch 'feature/support_quad_flash_octal_psram_on_esp32s3' into 'master'
mspi: support up-to-80MHz quad flash & up-to-80MHz octal psram on esp32s3

Closes IDF-3603

See merge request espressif/esp-idf!14346
2021-08-04 03:57:16 +00:00
Armando
0f91a01a46 mspi: support up-to-80MHz quad flash & up-to-80MHz octal psram on esp32s3 2021-08-03 16:54:00 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
Armando (Dou Yiwen)
0dad76329f Merge branch 'feature/support_noinit_section_in_psram_on_esp32' into 'master'
memory: support noinit section in psram on esp32

Closes IDFGH-2621

See merge request espressif/esp-idf!14088
2021-07-31 09:58:59 +00:00
Jiang Jiang Jian
aebdaf08a6 Merge branch 'bugfix/esp32s3_app_core_clock_gate_invalid_issue' into 'master'
fix app cpu core clock gate invalid issue

Closes WIFI-3899

See merge request espressif/esp-idf!14518
2021-07-31 03:00:58 +00:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
Armando
ad8e1a395c memory: port SPIRAM noinit segment support to master 2021-07-29 10:28:39 +08:00
Devan Lai
b85011c15f esp32: Add support for noinit variables in SPIRAM
Add Kconfig option SPIRAM_ALLOW_NOINIT_EXTERNAL_MEMORY
When enabled, a new linker script rule (from esp32.extram.noinit.ld)
places any variables in the .ext_ram.noinit section in SPIRAM.

This section is exempted from the startup SPIRAM memory test and is
not zero-initialized or added to the malloc pool, making it usable
for noinit variables that persist across reset.

The EXT_RAM_NOINIT_ATTR macro places variables in this section.
2021-07-29 10:28:38 +08:00
Li Shuai
8a10ba4179 system: fix app cpu core clock gate invalid issue 2021-07-28 11:34:29 +08:00
Michael (XIAO Xufeng)
18bee2380a Merge branch 'refactor/usb_device_driver' into 'master'
tiny_usb: support on esp32-s3

Closes IDF-3234

See merge request espressif/esp-idf!14293
2021-07-26 16:21:55 +00:00
Martin Vychodil
ce28af2dd4 System/memprot: ESP32C3 IRAM section alignment fix (LD)
IRAM section didn't contain sufficient padding for possible CPU instruction prefetch,
ie instruction fetch could happen in DRAM section which is prohibited by the Memprot module.
This is fixed by adding 16B to the end of IRAM section in LD script (C3 CPU prefetch buffer depth is 4 words)

Closes IDF-3554

* fix
2021-07-23 17:11:12 +02:00
Michael (XIAO Xufeng)
fbb6b1b11a Merge branch 'bugfix/fix_uart_reset_issue_on_esp32c3' into 'master'
bugfix(uart): reset uart0 core before uart apb reset

Closes IDF-3362

See merge request espressif/esp-idf!12749
2021-07-22 07:20:58 +00:00
morris
81448dcae8 tiny_usb: rename Kconfig name
1. Renamed Kconfig file of tinyusb (distinguish tinyusb stack from usb
   peripheral)
2. bugfix/typofix/doc update of tinyusb
2021-07-22 10:43:10 +08:00
KonstantinKondrashov
c19b37d2a9 esp_system: Adds sync of FRC & RTC counters in esp_restart
In case when FRC and RTC counters are very different then
the need to sync them before to restart the ESP
to get the correct system time after reboot.
2021-07-21 10:23:24 +05:00
Wangjialin
2b986fbd49 For esp_restart API, reset uart0 core first, then reset uart0 apb side, so as to prevent uart output garbage after cpu reset. (UART0 RST bits will be cleared in ROM)
Add UART0/1 core reset on esp32c3, in case uart driver would also reset uart hardwares.
2021-07-21 11:41:04 +08:00
morris
2058e89448 Merge branch 'feature/fpga_bootloader' into 'master'
Boot ESP32 & ESP32-S2 apps on FPGA

See merge request espressif/esp-idf!8270
2021-07-18 08:06:38 +00:00
Angus Gratton
c1ca7a35b0 ldgen: Remove some remaining references to TARGET.project.ld.in 2021-07-16 20:14:27 +08:00
Angus Gratton
f0471b18b2 esp32h2: Move from target component to esp_hw_support (new structure) 2021-07-16 20:14:27 +08:00
Renz Bagaporo
b06dba7823 esp32: move app linker scripts 2021-07-16 20:14:27 +08:00
Renz Bagaporo
fddc0b6799 esp32: move remaining tests 2021-07-16 20:14:27 +08:00
Renz Bagaporo
7c22cccb9c esp32: cleanup build script 2021-07-16 20:14:27 +08:00
Angus Gratton
1a626ef6ca esp32: App can boot on FPGA image
Includes fix for detecting ESP32 ECO3 on FPGA
2021-07-16 10:50:06 +10:00
Angus Gratton
bbbbd5cf0c esp32s2: FPGA can boot to Hello World 2021-07-16 10:50:06 +10:00
Omar Chebib
0771bd1711 espsystem: Rearchitecture and fix eh_frame_parser bugs
eh_frame_parser is architecture independent, thus the files have
been rearchitectured. Some bugs have been fixed in the test.
A README file has also been added to eh_frame_parser host test
directory.

eh_frame_parser is now able to detect empty gaps in .eh_frame_hdr
table (missing DWARF information).
Fix a bug occuring when parsing backtraces originated from abort().
Fix build missing dependencies issue.
2021-07-15 12:47:51 +08:00
Omar Chebib
b967dc0dbf espsystem: add support for RISC-V panic backtrace
Add .eh_frame and .eh_frame_hdr sections to the binary (can be
enabled/disabled within menuconfig). These sections are parsed
when a panic occurs. Their DWARF instructions are decoded and
executed at runtime, to retrieve the whole backtrace. This
parser has been tested on both RISC-V and x86 architectures.

This feature needs esptool's merge adjacent ELF sections feature.
2021-07-13 15:42:40 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Shu Chen
ee23a489b9 esp32h2: code clean up 2021-07-01 19:53:50 +08:00
Shu Chen
5e3689ae0f esp32h2: update esp_system and esp_hw_support to support esp32h2 2021-07-01 19:53:11 +08:00
Shu Chen
7d4b2617e1 esp32h2: copy esp_system and esp_hw_support from esp32c3
Copy the esp32c3 code without any change:
 * components/esp_hw_support/include/soc/esp32h2
 * components/esp_hw_support/port/esp32h2
 * components/esp_system/port/soc/esp32h2
2021-07-01 19:53:11 +08:00
Angus Gratton
2f8debdde1 Merge branch 'feature/esp32s3_remove_rtc_apb_freq_reg' into 'master'
esp32s3: Remove APB frequency RTC register

See merge request espressif/esp-idf!11137
2021-06-29 23:50:23 +00:00
Angus Gratton
1969e4b8e5 Merge branch 'bugfix/panic_handler_disable_wdts_early' into 'master'
esp_system: Reconfigure the WDTs at the start of the panic handler

Closes IDFCI-361

See merge request espressif/esp-idf!14138
2021-06-29 23:48:40 +00:00
Angus Gratton
57fa883127 esp32s3: Remove APB frequency RTC register
Usage of this register changed between ESP32-S3 beta2 and the
final chip.
2021-06-29 17:38:46 +10:00
Angus Gratton
14c7d4965b esp_system: Reconfigure the WDTs at the start of the panic handler
This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.
2021-06-28 17:24:39 +10:00
Ivan Grokhotkov
d7928bf1db Merge branch 'feature/esp32c3_apptrace' into 'master'
apptrace: refactoring & esp32c3 support

See merge request espressif/esp-idf!11702
2021-06-28 06:00:24 +00:00
Michael (XIAO Xufeng)
afc2bc94b3 Merge branch 'feature/add_opi_flash_psram_support' into 'master'
spi flash: opi flash psram support and spi timing tuning  support on 727

Closes IDF-3097

See merge request espressif/esp-idf!12946
2021-06-28 01:59:19 +00:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Alexey Gerenkov
20fd09728f apptrace: Adds ESP32-C3 support 2021-06-24 13:16:14 +03:00
Alexey Gerenkov
821869d98d apptrace: Refactors apptrace for better support various tracing HW 2021-06-24 13:16:13 +03:00
Jakob Hasse
64750acbb0 [esp_system]: added __cxx_eh_arena_size_get again
* This function has been accidentally removed.
  It is necessary to provide the emergency
  exception memory pool size for C++ code.
  Since our libstdc++ always has exceptions
  enabled, this function must exist here even if
  -fno-exception is set for user code.
2021-06-22 14:14:08 +08:00
Cao Sen Miao
f2fe0847d5 usb_serial_jtag: add initial support for S3 (including flashing, monitoring, writing, and reading) but console is not avaliable now 2021-06-18 12:42:41 +08:00
Angus Gratton
059353b0c2 Merge branch 'feature/refactor_common_secure_boot_code' into 'master'
secure_boot/flash_encryption: Refactoring

Closes IDF-2582 and IDF-2035

See merge request espressif/esp-idf!12963
2021-06-16 23:21:45 +00:00
Konstantin Kondrashov
f339b3fc96 efuse(esp32): Deprecate esp_efuse_burn_new_values() & esp_efuse_write_random_key()
These functions were used only for esp32 in secure_boot and flash encryption.
Use idf efuse APIs instead of efuse regs.
2021-06-17 07:21:36 +08:00
Marius Vikhammer
f124536948 system: add support for reset reason hint on S3 2021-06-15 13:39:51 +08:00
Angus Gratton
d995086621 Merge branch 'bugfix/memprot_bypass' into 'master'
System/Security: Memprot bypassing mitigation

Closes IDF-2700

See merge request espressif/esp-idf!13795
2021-06-09 00:02:30 +00:00
Jiang Jiang Jian
5cbea220b0 Merge branch 'feature/decouple_esp_phy' into 'master'
esp_phy: decouple esp_phy component from esp_wifi and bt

See merge request espressif/esp-idf!13742
2021-06-04 05:20:17 +00:00
Shu Chen
6061a547e5 esp_phy: decouple esp_phy component from esp_wifi and bt
* add esp-phy-lib submodule
* move libphy.a and phy_init.c from esp_wifi to esp_phy
* move librtc.a from esp_wifi to esp_phy
* move libbtbb.a from bt to esp_phy
* corresponding updates to build system
2021-06-03 16:17:31 +08:00
Angus Gratton
dc6b950257 doc: Add performance guides for execuion speed, binary size, RAM usage
Closes https://github.com/espressif/esp-idf/issues/7007
Closes https://github.com/espressif/esp-idf/issues/6715
Closes https://github.com/espressif/esp-idf/issues/3781
Closes https://github.com/espressif/esp-idf/issues/2566
2021-06-03 13:55:34 +10:00
Martin Vychodil
1e58eb6928 system/security: Memprot bypassing mitigation
Check Memprot lock bit(s) during the system startup, abort/reset on any Memprot parts found locked during this phase.
There is no legal reason to disallow the Memprot configuration by the system, so it's either a critical bug in the
application or an malicious attempt to bypass the system security.
Error message is printed before digital system reset.

Closes IDF-2700
2021-06-01 00:07:09 +02:00