fix(hal/include): fix header violations in hal component
fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h`
fix(hal/include): Move type definitions from `xx_hal.h` to `xx_types.h`
fix(hal/include): Add comment for a far away `#endif`
fix(hal/include): change scope for cpp guard
ci: Remove components/hal/ comment from public headers check exceptions
Add missing include macro sdkconfig.h for header files
Add missing include macro stdbool.h for header files
Add missing include macro stdint.h for header files
Add missing capability guard macro for header files
Add missing cpp guard macro for header files
Remove some useless include macros
Add some missing `inline` attribute for functions defined in header files
Remove components/hal/ from public headers check exceptions
fix(hal/include): fix invalid licenses
fix(hal/include): fix invalid licenses
fix(hal/include): add missing soc_caps.h
fix(hal): include soc_caps.h before cap macro is used
fix(hal): Remove unnecessary target check
fix(hal): fix header and macro problems
Add missing include macro
Remove loop dependency in hal
Add comment for far-away endif
fix(hal): Add missing soc_caps.h
ci: update check_copyright_ignore.txt
Change the sequence of `#include` macro, cpp guard macro
Change the wrap scope of capacity macro
fix(hal): Change position of C++ guard to pass test
since the linker placement of the hal functions are controlled by the Kconfig in the driver component,
we should create the linker.lf in the driver component, not in the hal component.
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
The caches are disabled when reading/writing/erasing flash.
All CPUs should always execute code and access data from internal RAM.
Add an IRAM option to enhance the performance of LEDC.
Closes https://github.com/espressif/esp-idf/issues/11554
1. Regression introduced when refactoring on clock sources selection (0d07f859).
If channel configuration is called before timer configuration on C6, PWM signal may not be able to output.
2. Missing the improper fade parameter fix inside ledc_set_duty_and_update() function.
1. Concurrency might cause ESP_ERR_TIMEOUT when calling uart_wait_tx_done
2. Concurrency might cause RTS line being de-assreted during tx transmission for rs485 mode
