mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
change(uart): change sleep code to be cache safe
- Set uart ll with FORCE_INLINE_ATTR - Add no_flash API periph_ll_uart_enabled api
This commit is contained in:
wuzhenghui
parent
6c14e1de9f
commit
4e9cc65763
@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -13,8 +13,10 @@ extern "C" {
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "hal/assert.h"
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#include "soc/periph_defs.h"
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#include "soc/dport_reg.h"
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#include "soc/soc_caps.h"
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static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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{
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@ -264,6 +266,19 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
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}
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FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
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{
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HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
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uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
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(uart_num == 1) ? DPORT_UART1_RST :
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(uart_num == 2) ? DPORT_UART2_RST : 0);
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uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
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(uart_num == 1) ? DPORT_UART1_CLK_EN :
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(uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
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return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
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DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,10 +12,12 @@ extern "C" {
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/dport_access.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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@ -213,6 +215,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
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DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
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DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
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}
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FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
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{
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HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
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uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
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(uart_num == 1) ? SYSTEM_UART1_RST : 0);
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uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
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(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
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return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
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DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,10 +12,12 @@ extern "C" {
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/dport_access.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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@ -262,6 +264,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
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DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
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DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
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}
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FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
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{
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HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
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uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
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(uart_num == 1) ? SYSTEM_UART1_RST : 0);
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uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
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(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
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return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
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DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -8,9 +8,11 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "soc/periph_defs.h"
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#include "soc/pcr_reg.h"
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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@ -328,6 +330,19 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
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REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
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}
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FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
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{
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HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
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uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
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(uart_num == 1) ? PCR_UART1_CONF_REG : 0);
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uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
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(uart_num == 1) ? PCR_UART1_RST_EN : 0);
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uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN :
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(uart_num == 1) ? PCR_UART1_CLK_EN : 0);
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return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
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REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -10,6 +10,7 @@
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#pragma once
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#include "esp_attr.h"
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#include "hal/misc.h"
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#include "hal/uart_types.h"
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#include "soc/uart_reg.h"
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@ -90,7 +91,7 @@ typedef enum {
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* @param hw Beginning address of the peripheral registers.
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* @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t.
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*/
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static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
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FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
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{
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(void)hw;
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switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
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@ -114,7 +115,7 @@ static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_
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*
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* @return None.
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*/
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static inline void uart_ll_update(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
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{
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hw->reg_update.reg_update = 1;
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while (hw->reg_update.reg_update);
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@ -128,7 +129,7 @@ static inline void uart_ll_update(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
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FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
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{
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if ((hw) != &LP_UART) {
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UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
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@ -146,7 +147,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
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*
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* @return None.
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*/
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static inline void uart_ll_sclk_enable(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
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{
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if ((hw) != &LP_UART) {
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UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
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@ -164,7 +165,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_sclk_disable(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
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{
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if ((hw) != &LP_UART) {
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UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
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@ -184,7 +185,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
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FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
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{
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if ((hw) != &LP_UART) {
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uint32_t sel_value = 0;
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@ -218,7 +219,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
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*
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* @return None.
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*/
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static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
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FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
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{
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if ((hw) != &LP_UART) {
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switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
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@ -247,7 +248,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
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*
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* @return None
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*/
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static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
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FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
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{
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#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
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const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
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@ -275,7 +276,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
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*
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* @return The current baudrate
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*/
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static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
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{
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typeof(hw->clkdiv_sync) div_reg;
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div_reg.val = hw->clkdiv_sync.val;
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@ -296,7 +297,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
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*
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* @return None
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*/
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static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val |= mask;
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}
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@ -309,7 +310,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return None
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*/
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static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val &= (~mask);
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}
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@ -321,7 +322,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return The UART interrupt status.
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*/
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static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
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{
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return hw->int_raw.val;
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}
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@ -333,7 +334,7 @@ static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
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*
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* @return The UART interrupt status.
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*/
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static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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{
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return hw->int_st.val;
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}
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@ -346,7 +347,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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{
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hw->int_clr.val = mask;
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}
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@ -358,7 +359,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
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*
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* @return interrupt enable value
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*/
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static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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{
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return hw->int_ena.val;
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}
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@ -372,7 +373,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
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*
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* @return None.
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*/
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static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
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{
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for (int i = 0; i < (int)rd_len; i++) {
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buf[i] = hw->fifo.rxfifo_rd_byte;
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@ -388,7 +389,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
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*
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* @return None
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*/
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static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
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{
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for (int i = 0; i < (int)wr_len; i++) {
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hw->fifo.rxfifo_rd_byte = buf[i];
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@ -402,7 +403,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
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*
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* @return None
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*/
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static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
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{
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hw->conf0_sync.rxfifo_rst = 1;
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uart_ll_update(hw);
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@ -417,7 +418,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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*
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* @return None
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*/
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static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
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FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
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{
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hw->conf0_sync.txfifo_rst = 1;
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uart_ll_update(hw);
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@ -432,7 +433,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
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*
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* @return The readable data length in rxfifo.
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*/
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static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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{
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return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
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}
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@ -444,7 +445,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
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*
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* @return The data length of txfifo can be written.
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*/
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static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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{
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uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
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uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
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@ -459,7 +460,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
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*
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* @return None.
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*/
|
||||
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
{
|
||||
hw->conf0_sync.stop_bit_num = stop_bit;
|
||||
uart_ll_update(hw);
|
||||
@ -473,7 +474,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
{
|
||||
*stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num;
|
||||
}
|
||||
@ -486,7 +487,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
{
|
||||
if (parity_mode != UART_PARITY_DISABLE) {
|
||||
hw->conf0_sync.parity = parity_mode & 0x1;
|
||||
@ -503,7 +504,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
{
|
||||
if (hw->conf0_sync.parity_en) {
|
||||
*parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity);
|
||||
@ -521,7 +522,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
{
|
||||
hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
|
||||
}
|
||||
@ -535,7 +536,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
{
|
||||
hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
|
||||
}
|
||||
@ -549,7 +550,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
{
|
||||
hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr;
|
||||
uart_ll_update(hw);
|
||||
@ -563,7 +564,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
{
|
||||
hw->idle_conf_sync.tx_idle_num = idle_num;
|
||||
uart_ll_update(hw);
|
||||
@ -577,7 +578,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
{
|
||||
if (break_num > 0) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
|
||||
@ -597,7 +598,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
{
|
||||
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
|
||||
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
|
||||
@ -622,7 +623,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
{
|
||||
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
|
||||
if (hw->hwfc_conf_sync.rx_flow_en) {
|
||||
@ -642,7 +643,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
{
|
||||
if (sw_flow_ctrl_en) {
|
||||
hw->swfc_conf0_sync.xonoff_del = 1;
|
||||
@ -671,7 +672,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
|
||||
@ -689,7 +690,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
{
|
||||
hw->conf0_sync.bit_num = data_bit;
|
||||
uart_ll_update(hw);
|
||||
@ -703,7 +704,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0_sync.sw_rts = level & 0x1;
|
||||
uart_ll_update(hw);
|
||||
@ -717,7 +718,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf1.sw_dtr = level & 0x1;
|
||||
}
|
||||
@ -731,7 +732,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
{
|
||||
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -743,7 +744,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
{
|
||||
// This function is only for HP_UART use
|
||||
// LP_UART can only work in normal mode
|
||||
@ -763,7 +764,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
{
|
||||
// This function is only for HP_UART use
|
||||
// LP_UART can only work in normal mode
|
||||
@ -787,7 +788,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
{
|
||||
// This function is only for HP_UART use
|
||||
// LP_UART can only work in normal mode
|
||||
@ -814,7 +815,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
{
|
||||
// This function is only for HP_UART use
|
||||
// LP_UART can only work in normal mode
|
||||
@ -839,7 +840,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
{
|
||||
// This function is only for HP_UART use
|
||||
// LP_UART can only work in normal mode
|
||||
@ -861,7 +862,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
default:
|
||||
@ -896,7 +897,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
{
|
||||
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
|
||||
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
|
||||
@ -909,7 +910,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
|
||||
*
|
||||
* @return The UART wakeup threshold value.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -922,7 +923,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return The bit mode.
|
||||
*/
|
||||
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
{
|
||||
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
|
||||
}
|
||||
@ -934,7 +935,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
|
||||
*
|
||||
* @return True if the state machine is in the IDLE state, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
{
|
||||
return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
|
||||
}
|
||||
@ -946,7 +947,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw rts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->hwfc_conf_sync.rx_flow_en;
|
||||
}
|
||||
@ -958,7 +959,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw cts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf0_sync.tx_flow_en;
|
||||
}
|
||||
@ -971,13 +972,13 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
{
|
||||
hw->conf0_sync.loopback = loop_back_en;
|
||||
uart_ll_update(hw);
|
||||
}
|
||||
|
||||
static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
{
|
||||
hw->swfc_conf0_sync.force_xon = 1;
|
||||
uart_ll_update(hw);
|
||||
@ -996,7 +997,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
{
|
||||
// LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV
|
||||
// lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1027,7 +1028,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
{
|
||||
uint16_t tout_val = tout_thrd;
|
||||
if(tout_thrd > 0) {
|
||||
@ -1046,7 +1047,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
*
|
||||
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
|
||||
*/
|
||||
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if(hw->tout_conf_sync.rx_tout_en > 0) {
|
||||
@ -1062,7 +1063,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
*
|
||||
* @return maximum timeout threshold.
|
||||
*/
|
||||
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V;
|
||||
}
|
||||
@ -1073,7 +1074,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable Boolean marking whether the auto baudrate should be enabled or not.
|
||||
*/
|
||||
static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
{
|
||||
// LP_UART does not support autobaud
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1087,7 +1088,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
{
|
||||
// LP_UART does not support this feature
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1100,7 +1101,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
// LP_UART does not support this feature
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1113,7 +1114,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
// LP_UART does not support this feature
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1126,7 +1127,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
// LP_UART does not support this feature
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1139,7 +1140,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
// LP_UART does not support this feature
|
||||
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
|
||||
@ -1154,7 +1155,7 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
{
|
||||
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
|
||||
hw->swfc_conf0_sync.force_xon = 0;
|
||||
@ -1170,7 +1171,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
|
||||
{
|
||||
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
|
||||
hw->swfc_conf0_sync.force_xoff = 0;
|
||||
@ -1187,7 +1188,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
|
||||
*
|
||||
* @return UART module FSM status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
{
|
||||
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
|
||||
return hw->fsm_status.st_utx_out;
|
||||
@ -1200,7 +1201,7 @@ static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
* @param discard true: Receiver stops storing data into FIFO when data is wrong
|
||||
* false: Receiver continue storing data into FIFO when data is wrong
|
||||
*/
|
||||
static inline void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
|
||||
FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
|
||||
{
|
||||
hw->conf0_sync.err_wr_mask = discard ? 1 : 0;
|
||||
uart_ll_update(hw);
|
||||
|
||||
@ -8,9 +8,12 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -390,6 +393,20 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
|
||||
// DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);// ESP32H2-TODO: IDF-6400
|
||||
// DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
|
||||
{
|
||||
HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
|
||||
uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
|
||||
(uart_num == 1) ? PCR_UART1_CONF_REG : 0);
|
||||
uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
|
||||
(uart_num == 1) ? PCR_UART1_RST_EN : 0);
|
||||
uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN :
|
||||
(uart_num == 1) ? PCR_UART1_CLK_EN : 0);
|
||||
return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
|
||||
REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/uart_types.h"
|
||||
#include "soc/uart_reg.h"
|
||||
@ -100,7 +101,7 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
|
||||
{
|
||||
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
|
||||
}
|
||||
@ -112,7 +113,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_sclk_enable(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
|
||||
{
|
||||
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
|
||||
}
|
||||
@ -124,7 +125,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_sclk_disable(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
|
||||
{
|
||||
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
|
||||
}
|
||||
@ -138,7 +139,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
|
||||
{
|
||||
switch (source_clk) {
|
||||
case UART_SCLK_PLL_F48M:
|
||||
@ -164,7 +165,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
|
||||
{
|
||||
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
|
||||
default:
|
||||
@ -189,7 +190,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
|
||||
{
|
||||
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
|
||||
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
|
||||
@ -213,7 +214,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
|
||||
*
|
||||
* @return The current baudrate
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
|
||||
{
|
||||
typeof(hw->clkdiv_sync) div_reg;
|
||||
div_reg.val = hw->clkdiv_sync.val;
|
||||
@ -228,7 +229,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val |= mask;
|
||||
}
|
||||
@ -241,7 +242,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_ena.val &= (~mask);
|
||||
}
|
||||
@ -253,7 +254,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return The UART interrupt status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_raw.val;
|
||||
}
|
||||
@ -265,7 +266,7 @@ static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
|
||||
*
|
||||
* @return The UART interrupt status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_st.val;
|
||||
}
|
||||
@ -278,7 +279,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
{
|
||||
hw->int_clr.val = mask;
|
||||
}
|
||||
@ -290,7 +291,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
|
||||
*
|
||||
* @return interrupt enable value
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
{
|
||||
return hw->int_ena.val;
|
||||
}
|
||||
@ -304,7 +305,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
|
||||
{
|
||||
for (int i = 0; i < (int)rd_len; i++) {
|
||||
buf[i] = hw->fifo.rxfifo_rd_byte;
|
||||
@ -320,7 +321,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
|
||||
{
|
||||
for (int i = 0; i < (int)wr_len; i++) {
|
||||
hw->fifo.rxfifo_rd_byte = buf[i];
|
||||
@ -334,7 +335,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0_sync.rxfifo_rst = 1;
|
||||
uart_ll_update(hw);
|
||||
@ -349,7 +350,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0_sync.txfifo_rst = 1;
|
||||
uart_ll_update(hw);
|
||||
@ -364,7 +365,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
|
||||
*
|
||||
* @return The readable data length in rxfifo.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return hw->status.rxfifo_cnt;
|
||||
}
|
||||
@ -376,7 +377,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return The data length of txfifo can be written.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
{
|
||||
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
|
||||
}
|
||||
@ -389,7 +390,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
|
||||
{
|
||||
hw->conf0_sync.stop_bit_num = stop_bit;
|
||||
uart_ll_update(hw);
|
||||
@ -403,7 +404,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
|
||||
{
|
||||
*stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num;
|
||||
}
|
||||
@ -416,7 +417,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
{
|
||||
if (parity_mode != UART_PARITY_DISABLE) {
|
||||
hw->conf0_sync.parity = parity_mode & 0x1;
|
||||
@ -433,7 +434,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
|
||||
{
|
||||
if (hw->conf0_sync.parity_en) {
|
||||
*parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity);
|
||||
@ -451,7 +452,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
|
||||
{
|
||||
hw->conf1.rxfifo_full_thrhd = full_thrhd;
|
||||
}
|
||||
@ -465,7 +466,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
|
||||
{
|
||||
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
|
||||
}
|
||||
@ -479,7 +480,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
{
|
||||
hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr;
|
||||
uart_ll_update(hw);
|
||||
@ -493,7 +494,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
{
|
||||
hw->idle_conf_sync.tx_idle_num = idle_num;
|
||||
uart_ll_update(hw);
|
||||
@ -507,7 +508,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
{
|
||||
if (break_num > 0) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
|
||||
@ -527,7 +528,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
|
||||
{
|
||||
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
|
||||
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
|
||||
@ -552,7 +553,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
|
||||
{
|
||||
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
|
||||
if (hw->hwfc_conf_sync.rx_flow_en) {
|
||||
@ -572,7 +573,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
|
||||
{
|
||||
if (sw_flow_ctrl_en) {
|
||||
hw->swfc_conf0_sync.xonoff_del = 1;
|
||||
@ -601,7 +602,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
|
||||
@ -619,7 +620,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
|
||||
{
|
||||
hw->conf0_sync.bit_num = data_bit;
|
||||
uart_ll_update(hw);
|
||||
@ -633,7 +634,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf0_sync.sw_rts = level & 0x1;
|
||||
uart_ll_update(hw);
|
||||
@ -647,7 +648,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
{
|
||||
hw->conf1.sw_dtr = level & 0x1;
|
||||
}
|
||||
@ -661,7 +662,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
{
|
||||
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -673,7 +674,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf_sync.rs485_en = 0;
|
||||
hw->rs485_conf_sync.rs485tx_rx_en = 0;
|
||||
@ -689,7 +690,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
{
|
||||
// Application software control, remove echo
|
||||
hw->rs485_conf_sync.rs485rxby_tx_en = 1;
|
||||
@ -709,7 +710,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
{
|
||||
// Enable receiver, sw_rts = 1 generates low level on RTS pin
|
||||
hw->conf0_sync.sw_rts = 1;
|
||||
@ -732,7 +733,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
{
|
||||
hw->conf0_sync.irda_en = 0;
|
||||
// Enable full-duplex mode
|
||||
@ -753,7 +754,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
{
|
||||
hw->rs485_conf_sync.rs485_en = 0;
|
||||
hw->rs485_conf_sync.rs485tx_rx_en = 0;
|
||||
@ -771,7 +772,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
default:
|
||||
@ -802,7 +803,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
|
||||
{
|
||||
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
|
||||
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
|
||||
@ -815,7 +816,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
|
||||
*
|
||||
* @return The UART wakeup threshold value.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
|
||||
}
|
||||
@ -828,7 +829,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
|
||||
*
|
||||
* @return The bit mode.
|
||||
*/
|
||||
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
|
||||
{
|
||||
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
|
||||
}
|
||||
@ -840,7 +841,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
|
||||
*
|
||||
* @return True if the state machine is in the IDLE state, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
{
|
||||
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
|
||||
}
|
||||
@ -852,7 +853,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw rts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->hwfc_conf_sync.rx_flow_en;
|
||||
}
|
||||
@ -864,7 +865,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return True if hw cts flow control is enabled, otherwise false is returned.
|
||||
*/
|
||||
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
{
|
||||
return hw->conf0_sync.tx_flow_en;
|
||||
}
|
||||
@ -877,13 +878,13 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
||||
{
|
||||
hw->conf0_sync.loopback = loop_back_en;
|
||||
uart_ll_update(hw);
|
||||
}
|
||||
|
||||
static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
{
|
||||
hw->swfc_conf0_sync.force_xon = 1;
|
||||
uart_ll_update(hw);
|
||||
@ -902,7 +903,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
{
|
||||
typeof(hw->conf0_sync) conf0_reg;
|
||||
conf0_reg.val = hw->conf0_sync.val;
|
||||
@ -930,7 +931,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
{
|
||||
uint16_t tout_val = tout_thrd;
|
||||
if(tout_thrd > 0) {
|
||||
@ -949,7 +950,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
|
||||
*
|
||||
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
|
||||
*/
|
||||
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
{
|
||||
uint16_t tout_thrd = 0;
|
||||
if(hw->tout_conf_sync.rx_tout_en > 0) {
|
||||
@ -965,7 +966,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
|
||||
*
|
||||
* @return maximum timeout threshold.
|
||||
*/
|
||||
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
{
|
||||
return UART_RX_TOUT_THRHD_V;
|
||||
}
|
||||
@ -976,7 +977,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable Boolean marking whether the auto baudrate should be enabled or not.
|
||||
*/
|
||||
static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->conf0_sync.autobaud_en = enable ? 1 : 0;
|
||||
uart_ll_update(hw);
|
||||
@ -987,7 +988,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
{
|
||||
return hw->rxd_cnt.rxd_edge_cnt;
|
||||
}
|
||||
@ -997,7 +998,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
return hw->pospulse.posedge_min_cnt;
|
||||
}
|
||||
@ -1007,7 +1008,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
return hw->negpulse.negedge_min_cnt;
|
||||
}
|
||||
@ -1017,7 +1018,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
return hw->highpulse.highpulse_min_cnt;
|
||||
}
|
||||
@ -1027,7 +1028,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
{
|
||||
return hw->lowpulse.lowpulse_min_cnt;
|
||||
}
|
||||
@ -1039,7 +1040,7 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
|
||||
{
|
||||
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
|
||||
REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
|
||||
@ -1068,7 +1069,7 @@ FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
|
||||
*
|
||||
* @return UART module FSM status.
|
||||
*/
|
||||
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
{
|
||||
return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
|
||||
}
|
||||
@ -1080,7 +1081,7 @@ static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
|
||||
* @param discard true: Receiver stops storing data into FIFO when data is wrong
|
||||
* false: Receiver continue storing data into FIFO when data is wrong
|
||||
*/
|
||||
static inline void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
|
||||
FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
|
||||
{
|
||||
hw->conf0_sync.err_wr_mask = discard ? 1 : 0;
|
||||
uart_ll_update(hw);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -13,10 +13,12 @@ extern "C" {
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "soc/dport_access.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
|
||||
{
|
||||
@ -276,6 +278,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN_M);
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
|
||||
{
|
||||
HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
|
||||
uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
|
||||
(uart_num == 1) ? DPORT_UART1_RST : 0);
|
||||
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
|
||||
(uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
|
||||
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
|
||||
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -13,10 +13,12 @@ extern "C" {
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "soc/dport_access.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
|
||||
{
|
||||
@ -297,6 +299,20 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
|
||||
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
|
||||
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
|
||||
{
|
||||
HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
|
||||
uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
|
||||
(uart_num == 1) ? SYSTEM_UART1_RST :
|
||||
(uart_num == 2) ? SYSTEM_UART2_RST : 0);
|
||||
uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
|
||||
(uart_num == 1) ? SYSTEM_UART1_CLK_EN :
|
||||
(uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
|
||||
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
|
||||
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user