essl_spi: fix wrong dummy cycle under quad spi mode ant add a test to verify spi quad mod
Closes IDF-5182 and IDF-5181
See merge request espressif/esp-idf!18680
1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8.
2.Put the spi command the spi defintion in spi_types.h
3.Put the function which get spi command or dummy bits in spi_ll.h
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
XTAL_CLK_FREQ now depends on the actual XTAL used, remove this macro
and get the XTAL frequency from the RTC register instead.
No uses of XTAL_CLK_FREQ found, other than in the UART LL.
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:
1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.
For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.
This introduced two possible issues:
1. Overflow when multiplying systimer counter by 5
- Should not be an issue, since systimer counter is 52-bit, so
counter * 5 is no more than 55-bit.
2. The code needs to perform:
- divide by 5: when converting from microseconds to ticks
- divide by 52: when converting from ticks to microseconds
The latter potentially introduces a performance issue for the
esp_timer_get_time function.
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:
- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead
Also updated soc_hal.h as follows:
- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.
This commit also updates the XCHAL_ERRATUM_572 workaround by
- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
This commit moves the dedicated GPIO LL and HAL functions from
cpu_ll.h to dedic_gpio_cpu_ll.h.
- cpu_ll_enable_cycle_count() has also been removed due to lack of feasible usage scenarios
