alex/esp-idf
alex/esp-idf
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30,811 Commits 20 Branches 148 Tags 384 MiB
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77 Commits

Author SHA1 Message Date
harshal.patil
710b9d228b
feat(esp_hw_support): Add esp_crypto_lock layer for esp32c2 2023-09-25 14:31:18 +05:30
wuzhenghui
c5703cff8d fix(lightsleep): fix access pu_cfg after sleep wake wakeup which is linked to flash 2023-07-31 21:41:56 +08:00
morris
d5fb4ff7c8 esp_rom: add common ROM API to update CPU tick rate 2023-06-01 10:57:13 +08:00
Song Ruo Jing
202b18b5fa esp_clk_tree: Rename clk_tree_xxx to esp_clk_tree_xxx, add compilation warning to clk_tree.h 2023-04-27 11:11:18 +00:00
cje
93eeb4265c fix chip broken bug when run in monitor mode of S2 and modify voltage param to fit all sleep mode of S2/C2/C3 2023-04-24 10:37:57 +08:00
Li Shuai
a25ce78392 sleep: fix sleep current issue caused by sar adc 2023-03-17 13:06:39 +08:00
Sachin Parekh
7bd5d93905 esp_hw_support: Move cpu protection in port files 2023-03-09 11:37:29 +05:30
Song Ruo Jing
1a66459b44 usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep 
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
   During sleep, BBPLL clock always gets disabled
   esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
   When this option is selected, IDF will constantly monitor USB CDC port connection status.
   As long as it gets connected to a HOST, automatic light-sleep will not happen.

Closes https://github.com/espressif/esp-idf/issues/8507
 2023-02-27 12:10:49 +08:00
Armando (Dou Yiwen)
4452a3cf3e Merge branch 'feature/support_h2_adc' into 'master' 
adc: support adc h2

Closes IDF-6124, IDF-6214, IDF-6543, IDF-6215, IDF-6664, and IDF-6695

See merge request espressif/esp-idf!22205
 2023-02-24 14:28:33 +08:00
Armando
c2d5c19b28 adc: ll enum renaming 2023-02-23 11:48:31 +08:00
jingli
4c3d1e24d7 codeclean: remove unused sleep related functions 2023-02-23 11:36:13 +08:00
jingli
af9c6e3175 esp32c2/rtc: fix 8md256 as rtc slow clk not work properly during deep sleep 2023-02-02 20:41:11 +08:00
jingli
f8cc2ec86d esp32c2: support rtc time feature depend on rtc memory, since c2 does not have rtc memory 2023-02-02 20:25:59 +08:00
wuzhenghui
a5467f42a0 codeclean: only S series chip VDDSDIO is configurable 2023-01-31 22:12:58 +08:00
Song Ruo Jing
2c9aa4559c clk_tree: Add a general API to get the frequency of different clocks 
Add basic clk_tree driver and hal implementation.
 2023-01-17 11:30:24 +08:00
Armando (Dou Yiwen)
d1b8da74d8 Merge branch 'refactor/improve_adc_power_maintanance' into 'master' 
adc: improve adc power maintanance

Closes IDF-6114 and IDF-6318

See merge request espressif/esp-idf!21151
 2023-01-12 20:30:36 +08:00
jiangguangming
4b4491e736 rtc_time.c: simplify the rtc_time_get with LL function 2023-01-10 17:03:54 +08:00
Armando
5be3c21cfc adc: improve power logic 2023-01-09 17:10:04 +08:00
Armando
f9da48d94f rtc: add pwdet and sar adc power related low level func 2023-01-09 17:09:01 +08:00
morris
672ac58ad5 io_mux: can set different clock source 2022-12-29 14:46:16 +08:00
Michael (XIAO Xufeng)
9aec53e83f esp32c2: fixed chip revision of ECO2 2022-12-21 15:28:50 +08:00
Song Ruo Jing
182e937c5a clk_tree: Add basic clock support for esp32c6 
- Support SOC ROOT clock source switch
    - Support CPU frequency change
    - Support RTC SLOW clock source switch
    - Support RTC SLOW clock + RC FAST calibration

    Remove FPGA build for esp32c6
 2022-12-13 19:18:34 +08:00
KonstantinKondrashov
741e89cbaa esp_hw_support: Removes efuse dependency 2022-11-25 19:27:33 +08:00
Konstantin Kondrashov
55578295db Merge branch 'feature/api_to_define_user_mac_addres' into 'master' 
esp_hw_support: Adds APIs to define user own MAC addresses without generation from the base MAC address

Closes IDFGH-5534 and IDFGH-8022

See merge request espressif/esp-idf!21036
 2022-11-17 15:26:35 +08:00
KonstantinKondrashov
244cf14ea8 esp_hw_support: Adds APIs to define user own MAC addresses without generation from the base MAC address 
Closes https://github.com/espressif/esp-idf/pull/7261
Closes https://github.com/espressif/esp-idf/issues/9531
 2022-11-16 19:23:10 +08:00
Marius Vikhammer
beeef9df2c hw-support: update C2 chip info to reflect that esp8684 has embedded flash 
Closes https://github.com/espressif/esp-idf/issues/10175
 2022-11-14 10:12:32 +08:00
Michael (XIAO Xufeng)
f2aa736c7b esp32c2: put v2.0 back to development stage 2022-11-03 08:36:23 +00:00
KonstantinKondrashov
1f9260d790 all: Apply new version logic (major * 100 + minor) 2022-11-03 08:36:23 +00:00
Armando
260ee86c37 rtc: united sar peripheral control 2022-10-27 16:51:25 +08:00
jingli
05a2fbe810 esp_hw_support/clk_cali: fix xtal32k error detect 2022-09-21 03:03:25 +00:00
jingli
c70094f64a esp32c2/clk_cali: fix rtc slow clk cali logic 2022-08-15 16:31:54 +08:00
Jing Li
c25c254666 Merge branch 'feature/further_support_esp32c2_sleep' into 'master' 
esp32c2/sleep: further support sleep for esp32c2 with 26MHz XTAL

Closes IDF-5544

See merge request espressif/esp-idf!19017
 2022-08-08 13:26:15 +08:00
jingli
ee3423834e kconfig: refactor xtal freq kconfig to common configuration item 2022-08-05 19:12:29 +08:00
zlq
7d8f10423e 1.add ldo parameters in efuse table; 2.set ldo dbias based on pvt-efuse; 3.add pll cali stop function; 4. add efuse_ocode 2022-08-05 14:24:51 +08:00
morris
031adc01c4 gpio: add test with -O0 2022-08-02 23:07:06 +08:00
morris
5e50ec1d66 systimer: add helper functions to convert between tick and us 2022-07-25 16:08:52 +08:00
Guillaume Souchere
6005cc9163 hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces 
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
 2022-07-22 00:06:06 +08:00
songruojing
ef813b23fa rtc: esp32c2 support 26MHz xtal in startup code and rtc_clk.c 2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
672e70a023 esp_hw_support: add 26 MHz XTAL option for esp32c2 
Some esp32c2 boards will be produced with a 26 MHz XTAL. This commit
adds the basic Kconfig option for this type of hardware.
Support for CONFIG_ESP32C2_XTAL_FREQ_26 in other areas of IDF will be
implemented in subsequent commits.
 2022-07-08 15:04:17 +08:00
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master' 
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
 2022-07-07 11:48:54 +08:00
Song Ruo Jing
b662f4b74f Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master' 
support c2 26M/32M xtal for bbpll

Closes IDF-5485

See merge request espressif/esp-idf!18769
 2022-07-06 21:17:52 +08:00
cje
e16165f263 support c2 26M/32M xtal for bbpll 2022-07-05 17:45:03 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
morris
7fd9a91034 dma: move from driver to hw_support 2022-06-28 14:17:12 +08:00
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation 
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
 2022-06-20 11:34:20 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00