Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' ... G0: RISC-V targets have now an independent G0 layer See merge request espressif/esp-idf!17926		2022-06-16 11:53:39 +08:00
..
private_include	G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h"	2022-06-14 15:00:53 +08:00
chip_info.c	soc: Adds efuse hal	2022-02-24 22:20:09 +08:00
CMakeLists.txt	esp_hw_support: Add esp_cpu.h abstraction and API	2022-06-14 14:30:58 +08:00
i2c_brownout.h	esp8684: rename target to esp32c2	2022-01-19 11:08:57 +08:00
Kconfig.mac	esp8684: rename target to esp32c2	2022-01-19 11:08:57 +08:00
Kconfig.rtc	clk_tree: add initial docs for clock tree	2022-05-24 22:59:51 +08:00
rtc_clk_init.c	rtc_clk: Fix rtc8m calibration failure after cpu/core reset	2022-06-13 17:47:51 +08:00
rtc_clk.c	clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem	2022-06-13 17:47:50 +08:00
rtc_init.c	rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in	2022-05-24 22:59:41 +08:00
rtc_pm.c	C2 rtc code	2022-05-09 17:50:54 +08:00
rtc_sleep.c	rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in	2022-05-24 22:59:41 +08:00
rtc_time.c	rtc_clk: Fix rtc8m calibration failure after cpu/core reset	2022-06-13 17:47:51 +08:00