mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'feature/further_support_esp32c2_sleep' into 'master'
esp32c2/sleep: further support sleep for esp32c2 with 26MHz XTAL Closes IDF-5544 See merge request espressif/esp-idf!19017
This commit is contained in:
commit
c25c254666
@ -42,13 +42,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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#if CONFIG_IDF_TARGET_ESP32
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clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
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#endif
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#if CONFIG_IDF_TARGET_ESP32C2
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clk_cfg.xtal_freq = CONFIG_ESP32C2_XTAL_FREQ;
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#endif
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/* For other chips, there is no XTAL_FREQ choice */
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clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
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clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
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if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
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@ -576,13 +576,13 @@ void ble_rtc_clk_init(void)
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
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#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
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#ifdef CONFIG_XTAL_FREQ_26
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// LP_TIMER_CLK_DIV_NUM -> 130
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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#else
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// LP_TIMER_CLK_DIV_NUM -> 250
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SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
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#endif // CONFIG_ESP32C2_XTAL_FREQ_26
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#endif // CONFIG_XTAL_FREQ_26
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// MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
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// MODEM_CLKRST_ETM_CLK_SEL -> 0
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@ -226,7 +226,7 @@ typedef struct {
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.coex_phy_coded_tx_rx_time_limit = DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF, \
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.dis_scan_backoff = NIMBLE_DISABLE_SCAN_BACKOFF, \
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.ble_scan_classify_filter_enable = 0, \
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.main_xtal_freq = CONFIG_ESP32C2_XTAL_FREQ, \
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.main_xtal_freq = CONFIG_XTAL_FREQ, \
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.config_magic = CONFIG_MAGIC, \
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};
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@ -192,11 +192,11 @@ extern "C" {
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#define BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N (3000)
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#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
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#ifdef CONFIG_XTAL_FREQ_26
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#define RTC_FREQ_N (40000) /* in Hz */
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#else
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#define RTC_FREQ_N (32000) /* in Hz */
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#endif // CONFIG_ESP32C2_XTAL_FREQ_26
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#endif // CONFIG_XTAL_FREQ_26
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#define BLE_LL_TX_PWR_DBM_N (0)
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@ -1,2 +1,2 @@
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CONFIG_IDF_TARGET="esp32c2"
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CONFIG_ESP32C2_XTAL_FREQ_26=y
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CONFIG_XTAL_FREQ_26=y
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@ -103,7 +103,6 @@ menu "Hardware Settings"
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If you are seeing "flash read err, 1000" message printed to the
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console after deep sleep reset, try increasing this value.
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endmenu
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menu "RTC Clock Config"
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@ -168,7 +167,6 @@ menu "Hardware Settings"
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default 0x4000 if MMU_PAGE_SIZE_16KB
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default 0x8000 if MMU_PAGE_SIZE_32KB
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default 0x10000 if MMU_PAGE_SIZE_64KB
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endmenu
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# Insert chip-specific HW config
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@ -193,4 +191,45 @@ menu "Hardware Settings"
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(e.g. SPI Flash write).
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endmenu # GDMA Configuration
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menu "Main XTAL Config"
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choice XTAL_FREQ_SEL
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prompt "Main XTAL frequency"
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default XTAL_FREQ_40 if SOC_XTAL_SUPPORT_40M
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help
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This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.
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The selected value MUST reflect the frequency of the given hardware.
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Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's
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operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the
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internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being
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temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate
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in high ambient temperatures or use high-temperature qualified chips and modules.
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config XTAL_FREQ_24
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depends on SOC_XTAL_SUPPORT_24M
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bool "24 MHz"
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config XTAL_FREQ_26
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depends on SOC_XTAL_SUPPORT_26M
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bool "26 MHz"
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config XTAL_FREQ_32
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depends on SOC_XTAL_SUPPORT_32M
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bool "32 MHz"
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config XTAL_FREQ_40
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depends on SOC_XTAL_SUPPORT_40M
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bool "40 MHz"
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config XTAL_FREQ_AUTO
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depends on SOC_XTAL_SUPPORT_AUTO_DETECT
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bool "Autodetect"
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endchoice
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# rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported
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# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported
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config XTAL_FREQ
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int
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default 24 if XTAL_FREQ_24
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default 26 if XTAL_FREQ_26
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default 32 if XTAL_FREQ_32
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default 40 if XTAL_FREQ_40
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default 0 if XTAL_FREQ_AUTO
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endmenu
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endmenu
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@ -63,7 +63,7 @@ int esp_clk_apb_freq(void);
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* @brief Return frequency of the main XTAL
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*
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* Frequency of the main XTAL can be either auto-detected or set at compile
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* time (see CONFIG_ESP32_XTAL_FREQ_SEL sdkconfig option). In both cases, this
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* time (see CONFIG_XTAL_FREQ_SEL sdkconfig option). In both cases, this
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* function returns the actual value at run time.
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*
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* @return XTAL frequency, in Hz
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@ -24,33 +24,3 @@ config ESP32_REV_MIN
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default 1 if ESP32_REV_MIN_1
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default 2 if ESP32_REV_MIN_2
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default 3 if ESP32_REV_MIN_3
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choice ESP32_XTAL_FREQ_SEL
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prompt "Main XTAL frequency"
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default ESP32_XTAL_FREQ_40
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help
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ESP32 currently supports the following XTAL frequencies:
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- 26 MHz
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- 40 MHz
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Startup code can automatically estimate XTAL frequency. This feature
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uses the internal 8MHz oscillator as a reference. Because the internal
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oscillator frequency is temperature dependent, it is not recommended
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to use automatic XTAL frequency detection in applications which need
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to work at high ambient temperatures and use high-temperature
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qualified chips and modules.
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config ESP32_XTAL_FREQ_40
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bool "40 MHz"
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config ESP32_XTAL_FREQ_26
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bool "26 MHz"
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config ESP32_XTAL_FREQ_AUTO
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bool "Autodetect"
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endchoice
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# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
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config ESP32_XTAL_FREQ
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int
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default 0 if ESP32_XTAL_FREQ_AUTO
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default 40 if ESP32_XTAL_FREQ_40
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default 26 if ESP32_XTAL_FREQ_26
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@ -95,7 +95,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
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rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
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if (est_xtal_freq != configured_xtal_freq) {
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ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
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ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
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configured_xtal_freq, est_xtal_freq);
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}
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}
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@ -1,21 +0,0 @@
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config ESP32C2_XTAL_FREQ
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int
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default 40 if ESP32C2_XTAL_FREQ_40
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default 26 if ESP32C2_XTAL_FREQ_26
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choice ESP32C2_XTAL_FREQ_SEL
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prompt "Main XTAL frequency"
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default ESP32C2_XTAL_FREQ_40
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help
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ESP32-C2 currently supports the following XTAL frequencies:
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- 26 MHz
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- 40 MHz
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This option must be set to the correct value for the given hardware.
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config ESP32C2_XTAL_FREQ_40 # TODO: IDF-5488
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bool "40 MHz"
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config ESP32C2_XTAL_FREQ_26
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bool "26 MHz"
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endchoice
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@ -302,8 +302,8 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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{
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uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
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if (xtal_freq_mhz == 0) {
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ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_ESP32C2_XTAL_FREQ);
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return CONFIG_ESP32C2_XTAL_FREQ;
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ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_XTAL_FREQ);
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return CONFIG_XTAL_FREQ;
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}
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return (rtc_xtal_freq_t)xtal_freq_mhz;
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}
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@ -12,7 +12,7 @@
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* So the resolution of the systimer is 40MHz/2.5 = 16MHz, or 26MHz/2.5 = 10.4MHz.
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*/
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#if CONFIG_ESP32C2_XTAL_FREQ_40
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#if CONFIG_XTAL_FREQ_40
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uint64_t systimer_ticks_to_us(uint64_t ticks)
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{
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return ticks / 16;
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@ -22,7 +22,7 @@ uint64_t systimer_us_to_ticks(uint64_t us)
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{
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return us * 16;
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}
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#elif CONFIG_ESP32C2_XTAL_FREQ_26
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#elif CONFIG_XTAL_FREQ_26
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uint64_t systimer_ticks_to_us(uint64_t ticks)
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{
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return ticks * 5 / 52;
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@ -34,4 +34,4 @@ uint64_t systimer_us_to_ticks(uint64_t us)
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}
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#else
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#error "Unsupported XTAL frequency by systimer"
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#endif // CONFIG_ESP32C2_XTAL_FREQ_xx
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#endif // CONFIG_XTAL_FREQ_xx
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@ -22,3 +22,8 @@ CONFIG_ESP32_SPIRAM_SUPPORT CONFIG_SPIRAM
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CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
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CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
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CONFIG_ESP32_XTAL_FREQ_26 CONFIG_XTAL_FREQ_26
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CONFIG_ESP32_XTAL_FREQ_40 CONFIG_XTAL_FREQ_40
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CONFIG_ESP32_XTAL_FREQ_AUTO CONFIG_XTAL_FREQ_AUTO
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CONFIG_ESP32_XTAL_FREQ CONFIG_XTAL_FREQ
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@ -331,7 +331,7 @@ menu "ESP System Settings"
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int
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prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
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depends on ESP_CONSOLE_UART
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default 74880 if ESP32C2_XTAL_FREQ_26
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default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26)
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default 115200
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range 1200 4000000 if !PM_ENABLE
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range 1200 1000000 if PM_ENABLE
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@ -71,7 +71,9 @@ static const char *TAG = "clk";
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}
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rtc_init(cfg);
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assert(rtc_clk_xtal_freq_get() == CONFIG_ESP32C2_XTAL_FREQ);
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#ifndef CONFIG_XTAL_FREQ_AUTO
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assert(rtc_clk_xtal_freq_get() == CONFIG_XTAL_FREQ);
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#endif
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bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
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rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
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@ -127,6 +127,18 @@ config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
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int
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default 5
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config SOC_XTAL_SUPPORT_26M
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bool
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default y
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config SOC_XTAL_SUPPORT_40M
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bool
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default y
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config SOC_XTAL_SUPPORT_AUTO_DETECT
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bool
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default y
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config SOC_ADC_RTC_CTRL_SUPPORTED
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bool
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default y
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@ -122,7 +122,7 @@ typedef struct rtc_clk_config_s {
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* Default initializer for rtc_clk_config_t
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*/
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#define RTC_CLK_CONFIG_DEFAULT() { \
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.xtal_freq = RTC_XTAL_FREQ_AUTO, \
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 80, \
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.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
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.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
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@ -96,6 +96,11 @@
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#endif // SOC_CAPS_ECO_VER < 2
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#define SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL (5U)
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_26M 1
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#define SOC_XTAL_SUPPORT_40M 1
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#define SOC_XTAL_SUPPORT_AUTO_DETECT 1
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/*-------------------------- ADC CAPS ----------------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_RTC_CTRL_SUPPORTED 1
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@ -67,6 +67,14 @@ config SOC_SYSTIMER_SUPPORTED
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bool
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default y
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config SOC_XTAL_SUPPORT_26M
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bool
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default y
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config SOC_XTAL_SUPPORT_40M
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bool
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default y
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config SOC_ADC_DIG_CTRL_SUPPORTED
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bool
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default y
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|
@ -174,7 +174,7 @@ typedef struct {
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* Default initializer for rtc_clk_config_t
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*/
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#define RTC_CLK_CONFIG_DEFAULT() { \
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.xtal_freq = RTC_XTAL_FREQ_40M, \
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 80, \
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.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
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.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
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|
@ -42,6 +42,10 @@
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_SYSTIMER_SUPPORTED 1
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_26M 1
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#define SOC_XTAL_SUPPORT_40M 1
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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|
@ -115,6 +115,10 @@ config SOC_MEMPROT_SUPPORTED
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bool
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default y
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config SOC_XTAL_SUPPORT_40M
|
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bool
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default y
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config SOC_AES_SUPPORT_DMA
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bool
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default y
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|
@ -177,7 +177,7 @@ typedef struct {
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* Default initializer for rtc_clk_config_t
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*/
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#define RTC_CLK_CONFIG_DEFAULT() { \
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.xtal_freq = RTC_XTAL_FREQ_40M, \
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 80, \
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.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
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.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
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|
@ -57,6 +57,9 @@
|
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_MEMPROT_SUPPORTED 1
|
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|
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/*-------------------------- XTAL CAPS ---------------------------------------*/
|
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#define SOC_XTAL_SUPPORT_40M 1
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/*-------------------------- AES CAPS -----------------------------------------*/
|
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#define SOC_AES_SUPPORT_DMA (1)
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|
@ -103,6 +103,10 @@ config SOC_SECURE_BOOT_SUPPORTED
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bool
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default y
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config SOC_XTAL_SUPPORT_32M
|
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bool
|
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default y
|
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config SOC_AES_SUPPORT_DMA
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bool
|
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default y
|
||||
|
@ -182,7 +182,7 @@ typedef struct {
|
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* Default initializer for rtc_clk_config_t
|
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*/
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#define RTC_CLK_CONFIG_DEFAULT() { \
|
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.xtal_freq = RTC_XTAL_FREQ_32M, \
|
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 32, \
|
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.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
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.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
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|
@ -59,6 +59,8 @@
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1
|
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#define SOC_SECURE_BOOT_SUPPORTED 1
|
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|
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/*-------------------------- XTAL CAPS ---------------------------------------*/
|
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#define SOC_XTAL_SUPPORT_32M 1
|
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|
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/*-------------------------- AES CAPS -----------------------------------------*/
|
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#define SOC_AES_SUPPORT_DMA (1)
|
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|
@ -143,6 +143,10 @@ config SOC_TOUCH_SENSOR_SUPPORTED
|
||||
bool
|
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default y
|
||||
|
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config SOC_XTAL_SUPPORT_40M
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_RTC_CTRL_SUPPORTED
|
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bool
|
||||
default y
|
||||
|
@ -170,7 +170,7 @@ typedef struct {
|
||||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
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#define RTC_CLK_CONFIG_DEFAULT() { \
|
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.xtal_freq = RTC_XTAL_FREQ_40M, \
|
||||
.xtal_freq = CONFIG_XTAL_FREQ, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
||||
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
||||
|
@ -75,6 +75,8 @@
|
||||
#define SOC_MEMPROT_SUPPORTED 1
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
/*-------------------------- ADC CAPS ----------------------------------------*/
|
||||
/*!< SAR ADC Module*/
|
||||
|
@ -199,6 +199,10 @@ config SOC_TOUCH_SENSOR_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_XTAL_SUPPORT_40M
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APPCPU_HAS_CLOCK_GATING_BUG
|
||||
bool
|
||||
default y
|
||||
|
@ -179,7 +179,7 @@ typedef struct {
|
||||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = RTC_XTAL_FREQ_40M, \
|
||||
.xtal_freq = CONFIG_XTAL_FREQ, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
||||
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
||||
|
@ -65,6 +65,9 @@
|
||||
#define SOC_MEMPROT_SUPPORTED 1
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
/*-------------------------- SOC CAPS ----------------------------------------*/
|
||||
#define SOC_APPCPU_HAS_CLOCK_GATING_BUG (1)
|
||||
|
||||
|
@ -328,7 +328,7 @@ After startup and diagnostic logs scroll up, you should see "Hello world!" print
|
||||
|
||||
To exit IDF monitor use the shortcut ``Ctrl+]``.
|
||||
|
||||
.. only:: esp32
|
||||
.. only:: esp32 or esp32c2
|
||||
|
||||
If IDF monitor fails shortly after the upload, or, if instead of the messages above, you see random garbage similar to what is given below, your board is likely using a 26 MHz crystal. Most development board designs use 40 MHz, so ESP-IDF uses this frequency as a default value.
|
||||
|
||||
@ -340,9 +340,18 @@ To exit IDF monitor use the shortcut ``Ctrl+]``.
|
||||
If you have such a problem, do the following:
|
||||
|
||||
1. Exit the monitor.
|
||||
2. Go back to `menuconfig`.
|
||||
3. Go to Component config --> ESP32-specific --> Main XTAL frequency, then change :ref:`CONFIG_ESP32_XTAL_FREQ_SEL` to 26 MHz.
|
||||
4. After that, `build and flash` the application again.
|
||||
2. Go back to ``menuconfig``.
|
||||
3. Go to ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency``, then change :ref:`CONFIG_XTAL_FREQ_SEL` to 26 MHz.
|
||||
4. After that, ``build and flash`` the application again.
|
||||
|
||||
In the current version of ESP-IDF, main XTAL frequencies supported by {IDF_TARGET_NAME} are as follows:
|
||||
|
||||
.. list::
|
||||
|
||||
:SOC_XTAL_SUPPORT_24M: - 24 MHz
|
||||
:SOC_XTAL_SUPPORT_26M: - 26 MHz
|
||||
:SOC_XTAL_SUPPORT_32M: - 32 MHz
|
||||
:SOC_XTAL_SUPPORT_40M: - 40 MHz
|
||||
|
||||
.. note::
|
||||
|
||||
|
@ -328,7 +328,7 @@
|
||||
|
||||
您可使用快捷键 ``Ctrl+]``,退出 IDF 监视器。
|
||||
|
||||
.. only:: esp32
|
||||
.. only:: esp32 or esp32c2
|
||||
|
||||
如果 IDF 监视器在烧录后很快发生错误,或打印信息全是乱码(如下),很有可能是因为您的开发板采用了 26 MHz 晶振,而 ESP-IDF 默认支持大多数开发板使用的 40 MHz 晶振。
|
||||
|
||||
@ -340,9 +340,18 @@
|
||||
此时,您可以:
|
||||
|
||||
1. 退出监视器。
|
||||
2. 返回 `menuconfig`。
|
||||
3. 进入 ``Component config`` --> ``ESP32-specific`` --> ``Main XTAL frequency`` 进行配置,将 :ref:`CONFIG_ESP32_XTAL_FREQ_SEL` 设置为 26 MHz。
|
||||
4. 重新 `编译和烧录` 应用程序。
|
||||
2. 返回 ``menuconfig``。
|
||||
3. 进入 ``Component config`` --> ``Hardware Settings`` --> ``Main XTAL Config`` --> ``Main XTAL frequency`` 进行配置,将 :ref:`CONFIG_XTAL_FREQ_SEL` 设置为 26 MHz。
|
||||
4. 重新 ``编译和烧录`` 应用程序。
|
||||
|
||||
在当前的 ESP-IDF 版本中,{IDF_TARGET_NAME} 支持的主晶振频率如下:
|
||||
|
||||
.. list::
|
||||
|
||||
:SOC_XTAL_SUPPORT_24M: - 24 MHz
|
||||
:SOC_XTAL_SUPPORT_26M: - 26 MHz
|
||||
:SOC_XTAL_SUPPORT_32M: - 32 MHz
|
||||
:SOC_XTAL_SUPPORT_40M: - 40 MHz
|
||||
|
||||
.. note::
|
||||
|
||||
|
@ -1118,10 +1118,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1122,10 +1122,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1122,10 +1122,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1119,10 +1119,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1119,10 +1119,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1119,10 +1119,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1117,10 +1117,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1119,10 +1119,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1119,10 +1119,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1121,10 +1121,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -1107,10 +1107,10 @@ CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
# CONFIG_ESP32_XTAL_FREQ_26 is not set
|
||||
# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
# CONFIG_XTAL_FREQ_26 is not set
|
||||
# CONFIG_XTAL_FREQ_AUTO is not set
|
||||
CONFIG_XTAL_FREQ=40
|
||||
# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
|
||||
# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
|
||||
# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
|
||||
|
@ -10,6 +10,7 @@
|
||||
#include "soc/uart_pins.h"
|
||||
#include "driver/uart.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#define EXAMPLE_UART_NUM 0
|
||||
/* Notice that ESP32 has to use the iomux input to configure uart as wakeup source
|
||||
@ -96,7 +97,7 @@ static void uart_wakeup_task(void *arg)
|
||||
static esp_err_t uart_initialization(void)
|
||||
{
|
||||
uart_config_t uart_cfg = {
|
||||
.baud_rate = 115200,
|
||||
.baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE,
|
||||
.data_bits = UART_DATA_8_BITS,
|
||||
.parity = UART_PARITY_DISABLE,
|
||||
.stop_bits = UART_STOP_BITS_1,
|
||||
@ -106,6 +107,10 @@ static esp_err_t uart_initialization(void)
|
||||
//Install UART driver, and get the queue.
|
||||
ESP_RETURN_ON_ERROR(uart_driver_install(EXAMPLE_UART_NUM, EXAMPLE_UART_BUF_SIZE, EXAMPLE_UART_BUF_SIZE, 20, &uart_evt_que, 0),
|
||||
TAG, "Install uart failed");
|
||||
if (EXAMPLE_UART_NUM == CONFIG_ESP_CONSOLE_UART_NUM) {
|
||||
/* temp fix for uart garbled output, can be removed when IDF-5683 done */
|
||||
ESP_RETURN_ON_ERROR(uart_wait_tx_idle_polling(EXAMPLE_UART_NUM), TAG, "Wait uart tx done failed");
|
||||
}
|
||||
ESP_RETURN_ON_ERROR(uart_param_config(EXAMPLE_UART_NUM, &uart_cfg), TAG, "Configure uart param failed");
|
||||
ESP_RETURN_ON_ERROR(uart_set_pin(EXAMPLE_UART_NUM, EXAMPLE_UART_TX_IO_NUM, EXAMPLE_UART_RX_IO_NUM, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE),
|
||||
TAG, "Configure uart gpio pins failed");
|
||||
|
@ -67,7 +67,6 @@ menu "Example Configuration"
|
||||
default 160 if EXAMPLE_MAX_CPU_FREQ_160
|
||||
default 240 if EXAMPLE_MAX_CPU_FREQ_240
|
||||
|
||||
|
||||
choice EXAMPLE_MIN_CPU_FREQ
|
||||
prompt "Minimum CPU frequency"
|
||||
default EXAMPLE_MIN_CPU_FREQ_10M
|
||||
@ -78,19 +77,19 @@ menu "Example Configuration"
|
||||
|
||||
config EXAMPLE_MIN_CPU_FREQ_40M
|
||||
bool "40 MHz (use with 40MHz XTAL)"
|
||||
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
|
||||
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
|
||||
config EXAMPLE_MIN_CPU_FREQ_20M
|
||||
bool "20 MHz (use with 40MHz XTAL)"
|
||||
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
|
||||
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
|
||||
config EXAMPLE_MIN_CPU_FREQ_10M
|
||||
bool "10 MHz (use with 40MHz XTAL)"
|
||||
depends on !IDF_TARGET_ESP32 || ESP32_XTAL_FREQ_40 || ESP32_XTAL_FREQ_AUTO
|
||||
depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
|
||||
config EXAMPLE_MIN_CPU_FREQ_26M
|
||||
bool "26 MHz (use with 26MHz XTAL)"
|
||||
depends on ESP32_XTAL_FREQ_26 || ESP32_XTAL_FREQ_AUTO
|
||||
depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO
|
||||
config EXAMPLE_MIN_CPU_FREQ_13M
|
||||
bool "13 MHz (use with 26MHz XTAL)"
|
||||
depends on ESP32_XTAL_FREQ_26 || ESP32_XTAL_FREQ_AUTO
|
||||
depends on XTAL_FREQ_26 || XTAL_FREQ_AUTO
|
||||
endchoice
|
||||
|
||||
config EXAMPLE_MIN_CPU_FREQ_MHZ
|
||||
|
@ -184,10 +184,10 @@ CONFIG_RTC_CLK_SRC_EXT_CRYS=
|
||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||
CONFIG_RTC_XTAL_BOOTSTRAP_CYCLES=100
|
||||
CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
|
||||
CONFIG_ESP32_XTAL_FREQ_40=y
|
||||
CONFIG_ESP32_XTAL_FREQ_26=
|
||||
CONFIG_ESP32_XTAL_FREQ_AUTO=
|
||||
CONFIG_ESP32_XTAL_FREQ=40
|
||||
CONFIG_XTAL_FREQ_40=y
|
||||
CONFIG_XTAL_FREQ_26=
|
||||
CONFIG_XTAL_FREQ_AUTO=
|
||||
CONFIG_XTAL_FREQ=40
|
||||
CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE=
|
||||
CONFIG_ESP_TIMER_PROFILING=
|
||||
CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
|
||||
|
@ -1,2 +1,2 @@
|
||||
CONFIG_IDF_TARGET="esp32c2"
|
||||
CONFIG_ESP32C2_XTAL_FREQ_26=y
|
||||
CONFIG_XTAL_FREQ_26=y
|
||||
|
@ -1,5 +1,5 @@
|
||||
# This config is split between targets since different component needs to be included
|
||||
CONFIG_IDF_TARGET="esp32c2"
|
||||
CONFIG_ESP32C2_XTAL_FREQ_26=y
|
||||
CONFIG_XTAL_FREQ_26=y
|
||||
|
||||
TEST_COMPONENTS=esp_timer
|
||||
|
@ -1,3 +1,3 @@
|
||||
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
|
||||
CONFIG_ESP32_XTAL_FREQ_AUTO=y
|
||||
CONFIG_XTAL_FREQ_AUTO=y
|
||||
CONFIG_SPI_FLASH_SHARE_SPI1_BUS=y
|
||||
|
@ -7,5 +7,5 @@
|
||||
"ESP32C3_IDF": "CONFIG_IDF_TARGET_ESP32C3=y"
|
||||
"quad_psram": '{CONFIG_SPIRAM_MODE_QUAD=y} and {CONFIG_IDF_TARGET_ESP32S3=y}'
|
||||
"octal_psram": '{CONFIG_SPIRAM_MODE_OCT=y} and {CONFIG_IDF_TARGET_ESP32S3=y}'
|
||||
"xtal_26mhz": '{CONFIG_ESP32C2_XTAL_FREQ_26=y} and {CONFIG_IDF_TARGET_ESP32C2=y}'
|
||||
"xtal_40mhz": '{CONFIG_ESP32C2_XTAL_FREQ_40=y} and {CONFIG_IDF_TARGET_ESP32C2=y}'
|
||||
"xtal_26mhz": '{CONFIG_XTAL_FREQ_26=y} and {CONFIG_IDF_TARGET_ESP32C2=y}'
|
||||
"xtal_40mhz": '{CONFIG_XTAL_FREQ_40=y} and {CONFIG_IDF_TARGET_ESP32C2=y}'
|
||||
|
Loading…
Reference in New Issue
Block a user