Commit Graph

723 Commits

Author SHA1 Message Date
Song Ruo Jing
ea97cc93ea Merge branch 'feature/c2_systimer_26mhz' into 'master'
esp32c2: 26 MHz XTAL support: Kconfig option, systimer support

Closes IDF-5412 and IDF-5413

See merge request espressif/esp-idf!18835
2022-07-11 16:17:25 +08:00
Marius Vikhammer
6cc871d793 Merge branch 'feature/ulp_riscv_adc' into 'master'
ulp-riscv: add support for using ADC as well as an example show-casing it.

Closes IDFGH-7564 and IDF-1714

See merge request espressif/esp-idf!18767
2022-07-11 12:30:31 +08:00
songruojing
996fb0cce8 G0: hal/regi2c_ctrl.h now defines all REGI2C macros to pass g0_components build test 2022-07-11 12:24:58 +08:00
wuzhenghui
a9c8065030 Kconfig: Update dependencies to avoid invalid configurations
1. Since the baud rate in the ROM cannot be changed,
   set the default baud rate of the 26Mhz version
   of esp32c2 to 74800
2. Since the systimer configuration of the 26Mhz
   version requires a non-integer systimer frequency
   configuration, and this feature is not supported
   in the current ROM, this option is disabled for
   the 26Mhz version esp32c2
2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
2e37218ce5 soc, hal: remove XTAL_CLK_FREQ
XTAL_CLK_FREQ now depends on the actual XTAL used, remove this macro
and get the XTAL frequency from the RTC register instead.
No uses of XTAL_CLK_FREQ found, other than in the UART LL.
2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
2022-07-11 12:24:37 +08:00
Marius Vikhammer
e8b5096f52 ulp-riscv: add support for using ADC as well as an example show-casing it. 2022-07-11 09:31:22 +08:00
Jiang Jiang Jian
a7bf3af687 Merge branch 'bugfix/reset_ble_hw_on_inititalization' into 'master'
component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3

Closes BT-2402

See merge request espressif/esp-idf!18831
2022-07-08 16:21:41 +08:00
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master'
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
2022-07-07 11:48:54 +08:00
Song Ruo Jing
b662f4b74f Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master'
support c2 26M/32M xtal for bbpll

Closes IDF-5485

See merge request espressif/esp-idf!18769
2022-07-06 21:17:52 +08:00
morris
a92cce9861 Merge branch 'bugfix/calib_i2c_clk' into 'master'
I2C: Make I2C clock frequency accurate

Closes IDF-5363

See merge request espressif/esp-idf!18686
2022-07-06 20:52:31 +08:00
wangmengyang
1d55f12c2d component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3/ESP32-S3
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and clock bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
2022-07-06 16:23:48 +08:00
Cao Sen Miao
e218723e0e I2C: Make I2C clock frequency accurate 2022-07-06 11:58:08 +08:00
GengYuchao
d145c337e0 Enable rpa_moudle reset function 2022-07-05 20:50:31 +08:00
cje
e16165f263 support c2 26M/32M xtal for bbpll 2022-07-05 17:45:03 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
morris
7863c1bc45 Merge branch 'bugfix/fix_rtc_freq_err_for_h2_beta1' into 'master'
Bugfix/fix rtc freq err for h2 beta1

See merge request espressif/esp-idf!18682
2022-07-04 16:46:17 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
2022-06-30 09:40:44 +00:00
GengYuchao
10fd1daa10 Add ETM clk gate defines for h2 2022-06-30 17:02:00 +08:00
Armando (Dou Yiwen)
e13d7f8351 Merge branch 'bugfix/s2_ap64_psram_crash_issue' into 'master'
psram: fix esp32s2 module with APS6404 PSRAM crash issue

Closes IDF-5361

See merge request espressif/esp-idf!18699
2022-06-29 11:19:17 +08:00
Armando
c51c1a8651 mmu: fix wrong mmu entry id issue 2022-06-28 14:17:44 +08:00
Armando
31b3f31ef4 ext_mem: make memory region check strict 2022-06-28 14:17:44 +08:00
morris
7fd9a91034 dma: move from driver to hw_support 2022-06-28 14:17:12 +08:00
Mahavir Jain
dd24639215 Merge branch 'esp32h2/enable_ecc_accelerator' into 'master'
esp32h2: Enable ECC accelerator

Closes IDF-3397

See merge request espressif/esp-idf!18647
2022-06-23 20:06:26 +08:00
Cao Sen Miao
2c0651a671 Add regi2c enable/disable reference count 2022-06-23 15:36:44 +08:00
Cao Sen Miao
3a820462ac temperature_sensor: Add temperature sensor support for ESP32-C2 2022-06-23 15:36:43 +08:00
Sachin Parekh
6cfc9c365f esp32h2: Enable ECC accelerator 2022-06-23 12:59:13 +05:30
Omar Chebib
8fae0f0753 G0: Support Xtensa targets for G0-only compilation
G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
2022-06-20 11:34:20 +00:00
Martin Vychodil
339fcbf14d System/Security: Memprot API unified (ESP32S3)
Unified Memory protection API for all PMS-aware chips - ESP32S3 port
2022-06-20 02:36:44 +00:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
Armando (Dou Yiwen)
0b80546f8e Merge branch 'feature/new_esp_psram_component' into 'master'
esp_psram: new esp psram component

Closes IDF-4318, IDF-4382, IDF-4841, and IDFGH-7192

See merge request espressif/esp-idf!18050
2022-06-15 19:16:56 +08:00
laokaiyao
28b8fc6a7e i2s: update documents for driver-NG 2022-06-15 10:30:04 +08:00
laokaiyao
0fe3bb8ab7 i2s: update examples and unit-tests 2022-06-15 10:29:06 +08:00
laokaiyao
621d0aa942 i2s: Introduced a brand new driver 2022-06-15 10:29:06 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master'
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
2022-06-14 21:11:30 +08:00
morris
919344547b Merge branch 'bugfix/rmt_register_file_s3' into 'master'
rmt: update register file after fixing csv of RMT peripheral (esp32s2/s3)

Closes IDFGH-7537

See merge request espressif/esp-idf!18392
2022-06-14 18:24:28 +08:00
Michael (XIAO Xufeng)
7b8e5888ca Merge branch 'refactor/add_clk_tree_ll' into 'master'
clk_tree: Stage3 - HAL for clock subsystem

Closes IDF-4334

See merge request espressif/esp-idf!18270
2022-06-14 17:16:29 +08:00
Jiang Jiang Jian
3cb6abee3c Merge branch 'bugfix/hal_assert_spelling' into 'master'
HAL: fix kconfig HAL_ASSERTION typo

See merge request espressif/esp-idf!18482
2022-06-14 16:24:25 +08:00
Jiang Jiang Jian
4e33239474 Merge branch 'feature/remove_back_compatible_with_s3beta_rom' into 'master'
spi_flash: remove back-compatible with caller function of S3Beta ROM

See merge request espressif/esp-idf!18492
2022-06-14 16:22:08 +08:00
Armando
38e5043ae8 esp_psram: new psram component 2022-06-14 15:44:27 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer
G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
2022-06-14 14:40:03 +08:00
Darian Leung
149872131a hal: Move dedicated GPIO LL and HAL
This commit moves the dedicated GPIO LL and HAL functions from
cpu_ll.h to dedic_gpio_cpu_ll.h.

- cpu_ll_enable_cycle_count() has also been removed due to lack of feasible usage scenarios
2022-06-14 14:38:29 +08:00
jiangguangming
0e8401e9b0 spi_flash: remove back-compatible with caller function of S3Beta ROM 2022-06-14 11:25:30 +08:00
morris
b2bb8fd3c4 rgb_lcd: support update pclk at runtime 2022-06-14 02:20:47 +00:00
morris
843279d287 rgb_lcd: support fractional clock divisor 2022-06-14 02:20:47 +00:00
songruojing
6f6251f369 hal: Limit the HAL_ASSERTION_LEVEL in bootloader to be no larger than 1 (i.e. silent) 2022-06-13 17:47:51 +08:00
songruojing
c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00
Marius Vikhammer
e18f381905 HAL: fix kconfig HAL_ASSERTION typo 2022-06-13 16:19:28 +08:00