2020-09-09 22:37:58 -04:00
// The long term plan is to have a single soc_caps.h for all peripherals.
2020-06-18 05:13:19 -04:00
// During the refactoring and multichip support development process, we
2020-09-09 22:37:58 -04:00
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
2020-06-18 05:13:19 -04:00
# pragma once
2020-09-09 22:37:58 -04:00
/*-------------------------- COMMON CAPS ---------------------------------------*/
2020-11-19 04:03:10 -05:00
# define SOC_PCNT_SUPPORTED 1
# define SOC_TWAI_SUPPORTED 1
# define SOC_GDMA_SUPPORTED 1
2021-05-11 23:26:07 -04:00
# define SOC_LCDCAM_SUPPORTED 1
2021-01-07 04:34:59 -05:00
# define SOC_MCPWM_SUPPORTED 1
2020-11-19 04:03:10 -05:00
# define SOC_DEDICATED_GPIO_SUPPORTED 1
# define SOC_CPU_CORES_NUM 2
2020-11-25 23:39:49 -05:00
# define SOC_CACHE_SUPPORT_WRAP 1
# define SOC_ULP_SUPPORTED 1
# define SOC_RTC_SLOW_MEM_SUPPORTED 1
2020-12-03 22:35:21 -05:00
# define SOC_CCOMP_TIMER_SUPPORTED 1
2021-02-22 20:31:29 -05:00
# define SOC_DIG_SIGN_SUPPORTED 1
# define SOC_HMAC_SUPPORTED 1
2021-03-12 02:20:41 -05:00
# define SOC_ASYNC_MEMCPY_SUPPORTED 1
2021-01-05 10:09:24 -05:00
# define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
2021-01-04 14:34:31 -05:00
# define SOC_SDMMC_HOST_SUPPORTED 1
2020-12-03 22:35:21 -05:00
2020-09-08 08:17:18 -04:00
2020-09-09 22:37:58 -04:00
/*-------------------------- ADC CAPS ----------------------------------------*/
# include "adc_caps.h"
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
# include "brownout_caps.h"
/*-------------------------- CPU CAPS ----------------------------------------*/
# include "cpu_caps.h"
/*-------------------------- GDMA CAPS ---------------------------------------*/
2021-04-27 06:52:42 -04:00
# define SOC_GDMA_GROUPS (1) // Number of GDMA groups
# define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group
# define SOC_GDMA_L2_FIFO_BASE_SIZE (16) // Basic size of GDMA Level 2 FIFO
# define SOC_GDMA_SUPPORT_EXTMEM (1) // GDMA can access external PSRAM
2020-09-09 22:37:58 -04:00
/*-------------------------- GPIO CAPS ---------------------------------------*/
# include "gpio_caps.h"
2020-05-11 07:50:17 -04:00
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
# define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (4) /*!< 4 outward channels on each CPU core */
# define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (4) /*!< 4 inward channels on each CPU core */
2020-09-09 22:37:58 -04:00
/*-------------------------- I2C CAPS ----------------------------------------*/
# include "i2c_caps.h"
/*-------------------------- I2S CAPS ----------------------------------------*/
# include "i2s_caps.h"
/*-------------------------- LEDC CAPS ---------------------------------------*/
# include "ledc_caps.h"
2021-01-07 04:34:59 -05:00
/*-------------------------- MCPWM CAPS --------------------------------------*/
# define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
# define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
# define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
# define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
# define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
# define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
# define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
# define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
# define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
# define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
2020-09-09 22:37:58 -04:00
/*-------------------------- MPU CAPS ----------------------------------------*/
# include "mpu_caps.h"
/*-------------------------- PCNT CAPS ---------------------------------------*/
2020-09-18 05:22:59 -04:00
# define SOC_PCNT_PORT_NUM (1)
# define SOC_PCNT_UNIT_NUM (4)
# define SOC_PCNT_UNIT_CHANNEL_NUM (2)
2020-09-09 22:37:58 -04:00
/*-------------------------- RMT CAPS ----------------------------------------*/
2021-02-07 04:18:39 -05:00
# define SOC_RMT_GROUPS (1) /*!< One RMT group */
# define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */
# define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */
# define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */
# define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
2020-10-09 04:41:41 -04:00
# define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
# define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
# define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
2021-02-07 04:18:39 -05:00
# define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
2020-10-09 04:41:41 -04:00
# define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
2020-09-09 22:37:58 -04:00
2021-02-26 00:58:04 -05:00
/*-------------------------- LCD CAPS ----------------------------------------*/
2021-05-11 23:26:07 -04:00
/* Notes: On esp32-s3, I80 bus and RGB timing generator can't work at the same time */
# define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */
# define SOC_LCD_RGB_SUPPORTED (1) /*!< RGB LCD is supported */
2021-02-26 00:58:04 -05:00
# define SOC_LCD_I80_BUSES (1) /*!< Has one LCD Intel 8080 bus */
# define SOC_LCD_RGB_PANELS (1) /*!< Support one RGB LCD panel */
2021-05-11 23:26:07 -04:00
# define SOC_LCD_I80_BUS_WIDTH (16) /*!< Intel 8080 bus width */
# define SOC_LCD_RGB_DATA_WIDTH (16) /*!< Number of LCD data lines */
2021-02-26 00:58:04 -05:00
2020-09-09 22:37:58 -04:00
/*-------------------------- RTCIO CAPS --------------------------------------*/
# include "rtc_io_caps.h"
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
2020-10-22 01:16:49 -04:00
# define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
# define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
2020-09-09 22:37:58 -04:00
/*-------------------------- SPI CAPS ----------------------------------------*/
# include "spi_caps.h"
2020-11-25 23:39:49 -05:00
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
# define SOC_SPIRAM_SUPPORTED 1
2020-09-09 22:37:58 -04:00
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
2021-04-02 00:41:08 -04:00
# define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
# define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
# define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
# define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
# define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
# define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level
# define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
2020-09-09 22:37:58 -04:00
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
2021-02-01 01:17:10 -05:00
# define SOC_TIMER_GROUPS (2)
# define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
# define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
# define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
2020-10-13 23:46:30 -04:00
# define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
2020-09-09 22:37:58 -04:00
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
# include "touch_sensor_caps.h"
/*-------------------------- TWAI CAPS ---------------------------------------*/
# include "twai_caps.h"
/*-------------------------- UART CAPS ---------------------------------------*/
# include "uart_caps.h"
2020-11-19 04:03:10 -05:00
# define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
# define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
2020-10-28 22:51:36 -04:00
2021-05-06 04:20:54 -04:00
/*-------------------------- USB CAPS ----------------------------------------*/
# define SOC_USB_PERIPH_NUM 1
2020-10-28 22:51:36 -04:00
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
# define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
# define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user supplied context */
# define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
2021-01-14 02:25:06 -05:00
# define SOC_SHA_GDMA (1)
2020-10-28 22:51:36 -04:00
/* Supported HW algorithms */
# define SOC_SHA_SUPPORT_SHA1 (1)
# define SOC_SHA_SUPPORT_SHA224 (1)
# define SOC_SHA_SUPPORT_SHA256 (1)
# define SOC_SHA_SUPPORT_SHA384 (1)
# define SOC_SHA_SUPPORT_SHA256 (1)
# define SOC_SHA_SUPPORT_SHA512 (1)
# define SOC_SHA_SUPPORT_SHA512_224 (1)
# define SOC_SHA_SUPPORT_SHA512_256 (1)
# define SOC_SHA_SUPPORT_SHA512_T (1)
/* Supported HW algorithms */
# define SOC_SHA_SUPPORT_SHA1 (1)
# define SOC_SHA_SUPPORT_SHA256 (1)
# define SOC_SHA_SUPPORT_SHA384 (1)
# define SOC_SHA_SUPPORT_SHA512 (1)
/*--------------------------- RSA CAPS ---------------------------------------*/
# define SOC_RSA_MAX_BIT_LEN (4096)
2020-11-12 02:11:38 -05:00
/*-------------------------- AES CAPS -----------------------------------------*/
# define SOC_AES_SUPPORT_DMA (1)
2021-01-12 06:10:21 -05:00
/*-------------------------- Power Management CAPS ---------------------------*/
# define SOC_PM_SUPPORT_EXT_WAKEUP (1)
# define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
# define SOC_PM_SUPPORT_BT_WAKEUP (1)
2020-11-12 02:11:38 -05:00
/* Has a centralized DMA, which is shared with all peripherals */
2021-01-14 02:25:06 -05:00
# define SOC_AES_GDMA (1)
2020-11-12 02:11:38 -05:00
# define SOC_AES_SUPPORT_AES_128 (1)
# define SOC_AES_SUPPORT_AES_256 (1)
2021-02-24 23:25:38 -05:00
/*-------------------------- Flash Encryption CAPS----------------------------*/
# define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
2020-09-08 08:17:18 -04:00
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
// Remove them when GDMA driver API is ready
2021-01-24 11:18:42 -05:00
# define SOC_GDMA_SHA_DMA_CHANNEL (3)
# define SOC_GDMA_AES_DMA_CHANNEL (4)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
# define SOC_WIFI_HW_TSF (1)
2021-01-19 06:36:06 -05:00
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
# define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
# define SOC_MAC_BB_PD_MEM_SIZE (192*4)
2020-12-17 23:57:55 -05:00
2021-02-24 03:24:16 -05:00
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
# define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
2020-12-17 23:57:55 -05:00
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
# define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
# define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
# define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
# define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
2021-01-24 11:18:42 -05:00
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
# define SOC_COEX_HW_PTI (1)
2021-01-04 14:34:31 -05:00
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/* Card detect, write protect, interrupt use GPIO Matrix on all chips.
* On ESP32 - S3 , clock / cmd / data pins use GPIO Matrix as well .
*/
# define SOC_SDMMC_USE_GPIO_MATRIX 1
# define SOC_SDMMC_NUM_SLOTS 2
/* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */
# define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1