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esp-idf/components/soc/esp32s3/include/soc/soc_caps.h

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soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
// The long term plan is to have a single soc_caps.h for all peripherals.
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
// During the refactoring and multichip support development process, we
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
soc: add soc descriptions for esp32s3
2020-06-18 05:13:19 -04:00
#pragma once
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- COMMON CAPS ---------------------------------------*/
pcnt: add pcnt peripheral signal connections pcnt: fix bug in clear interrupt status
2020-09-18 05:22:59 -04:00
#define SOC_PCNT_SUPPORTED 1
soc: placeholder for esp32s3 HAL driver soc rtc
2020-07-31 06:26:07 -04:00
#define SOC_TWAI_SUPPORTED 1
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 08:17:18 -04:00
#define SOC_GDMA_SUPPORTED 1
dedicated gpio: add driver
2020-05-11 07:50:17 -04:00
#define SOC_DEDICATED_GPIO_SUPPORTED 1
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 08:17:18 -04:00
#define SOC_CPU_CORES_NUM 2
bootloader: fix the WRSR format for ISSI flash chips 1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability. This commit helps to clear WEL when flash configuration is done. **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA. 2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips. Status register bitmap of ISSI chip and GD chip: | SR | ISSI | GD25LQ32C | | -- | ---- | --------- | | 0 | WIP | WIP | | 1 | WEL | WEL | | 2 | BP0 | BP0 | | 3 | BP1 | BP1 | | 4 | BP2 | BP2 | | 5 | BP3 | BP3 | | 6 | QE | BP4 | | 7 | SRWD | SRP0 | | 8 | | SRP1 | | 9 | | QE | | 10 | | SUS2 | | 11 | | LB1 | | 12 | | LB2 | | 13 | | LB3 | | 14 | | CMP | | 15 | | SUS1 | QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command. However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips. Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected. This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6). 3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared. This commit skips the clearing of status register if there is no protection bits active. Also move the execute_flash_command to be a bootloader API; move implementation of spi_flash_wrap_set to the bootloader
2020-03-12 06:20:31 -04:00
#define SOC_CACHE_SUPPORT_WRAP 1
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 08:17:18 -04:00
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- ADC CAPS ----------------------------------------*/
#include "adc_caps.h"
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#include "brownout_caps.h"
/*-------------------------- CPU CAPS ----------------------------------------*/
#include "cpu_caps.h"
/*-------------------------- DAC CAPS ----------------------------------------*/
#include "dac_caps.h"
/*-------------------------- GDMA CAPS ---------------------------------------*/
#include "gdma_caps.h"
/*-------------------------- GPIO CAPS ---------------------------------------*/
#include "gpio_caps.h"
dedicated gpio: add driver
2020-05-11 07:50:17 -04:00
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (4) /*!< 4 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (4) /*!< 4 inward channels on each CPU core */
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- I2C CAPS ----------------------------------------*/
#include "i2c_caps.h"
/*-------------------------- I2S CAPS ----------------------------------------*/
#include "i2s_caps.h"
/*-------------------------- LEDC CAPS ---------------------------------------*/
#include "ledc_caps.h"
/*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h"
/*-------------------------- PCNT CAPS ---------------------------------------*/
pcnt: add pcnt peripheral signal connections pcnt: fix bug in clear interrupt status
2020-09-18 05:22:59 -04:00
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4)
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- RMT CAPS ----------------------------------------*/
rmt: split TX and RX in LL driver Split TX and RX function in LL driver. Channel number is encoded in driver layer. Added channel signal list in periph.c
2020-10-09 04:41:41 -04:00
#define SOC_RMT_CHANNEL_MEM_WORDS (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_TX_CHANNELS_NUM (4) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CHANNELS_NUM (4) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels (each channel can be configured to either TX or RX) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h"
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
sigma_delta: add periph signal list and support esp32-s3
2020-10-22 01:16:49 -04:00
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- SPI CAPS ----------------------------------------*/
#include "spi_caps.h"
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
#include "systimer_caps.h"
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
timergroup: move interrupt index into peripheral description file 1. Added timer_group_periph.c file, describing module global signals (e.g. interrupt index) 2. Added more caps in soc_caps.h
2020-10-13 23:46:30 -04:00
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
soc: combine xxx_caps.h into one soc_caps.h During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2020-09-09 22:37:58 -04:00
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#include "touch_sensor_caps.h"
/*-------------------------- TWAI CAPS ---------------------------------------*/
#include "twai_caps.h"
/*-------------------------- UART CAPS ---------------------------------------*/
#include "uart_caps.h"
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
2020-09-08 08:17:18 -04:00
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
// Remove them when GDMA driver API is ready
spi: fix build fail issue when target is esp32s3
2020-09-23 09:01:13 -04:00
#define SOC_GDMA_M2M_DMA_CHANNEL (0)
#define SOC_GDMA_SPI2_DMA_CHANNEL (1)
SHA: add HAL layer and refactor driver Add a LL and HAL layer for SHA.
2020-08-13 04:30:59 -04:00
#define SOC_GDMA_SPI3_DMA_CHANNEL (2)
#define SOC_GDMA_SHA_DMA_CHANNEL (3)
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