Merge 27b5f6298c into c01512f4b0

Fixed occational assert failure in vTaskDeleteWithCaps()

Closes IDFGH-13294

See merge request espressif/esp-idf!33468

components/app_update/test_apps/test_app_update/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/bootloader_support/src/bootloader_mem.c

@@ -16,12 +16,6 @@
 #include "hal/apm_hal.h"
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-#include "soc/hp_apm_reg.h"
-#include "soc/lp_apm_reg.h"
-#endif
-
-
 void bootloader_init_mem(void)
 {
 
@@ -38,13 +32,6 @@ void bootloader_init_mem(void)
 #endif
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
-    // disable apm filter
-    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
-    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
-#endif
-
-
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
     esp_cpu_configure_region_protection();

components/bootloader_support/src/esp32c61/bootloader_sha.c

@@ -13,8 +13,6 @@
 
 static SHA_CTX ctx;
 
-//TODO: [ESP32C61] IDF-9234
-
 bootloader_sha256_handle_t bootloader_sha256_start()
 {
     // Enable SHA hardware

components/bt/CMakeLists.txt

@@ -855,16 +855,17 @@ if(CONFIG_BT_ENABLED)
         target_link_directories(${COMPONENT_LIB} INTERFACE
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
         target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C6)
-        add_prebuilt_library(libble_app
-                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c6/libble_app.a")
-        target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C61)
-        add_prebuilt_library(libble_app
-                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c61/libble_app.a")
-        target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     elseif(CONFIG_BT_CONTROLLER_ENABLED)
-        add_prebuilt_library(libble_app "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        if(CONFIG_IDF_TARGET_ESP32C6)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c6/libble_app.a")
+        elseif(CONFIG_IDF_TARGET_ESP32C61)
+            add_prebuilt_library(libble_app
+                "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c6/esp32c6-bt-lib/esp32c61/libble_app.a")
+        else()
+            add_prebuilt_library(libble_app
+                 "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
+        endif()
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     endif()
 

components/bt/esp_ble_mesh/lib/lib

@@ -1 +1 @@
-Subproject commit 8312e0e0d5390d04fd282e8005528d2b5c351c08
+Subproject commit cba99c5a2e7f5d4bccb04e8f3f968dc888bb5667

components/bt/porting/npl/freertos/src/npl_os_freertos.c

@@ -21,6 +21,7 @@
 #include "esp_log.h"
 #include "soc/soc_caps.h"
 #include "esp_bt.h"
+#include "bt_osi_mem.h"
 
 portMUX_TYPE ble_port_mutex = portMUX_INITIALIZER_UNLOCKED;
 
@@ -95,7 +96,7 @@ IRAM_ATTR npl_freertos_event_init(struct ble_npl_event *ev, ble_npl_event_fn *fn
     }
 #else
     if(!ev->event) {
-        ev->event = malloc(sizeof(struct ble_npl_event_freertos));
+        ev->event = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_event_freertos));
     }
 #endif
     event = (struct ble_npl_event_freertos *)ev->event;
@@ -113,7 +114,7 @@ IRAM_ATTR npl_freertos_event_deinit(struct ble_npl_event *ev)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_ev_pool,ev->event);
 #else
-    free(ev->event);
+    bt_osi_mem_free(ev->event);
 #endif
     ev->event = NULL;
 }
@@ -144,7 +145,7 @@ npl_freertos_eventq_init(struct ble_npl_eventq *evq)
     }
 #else
     if(!evq->eventq) {
-        evq->eventq = malloc(sizeof(struct ble_npl_eventq_freertos));
+        evq->eventq = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_eventq_freertos));
         eventq = (struct ble_npl_eventq_freertos*)evq->eventq;
         BLE_LL_ASSERT(eventq);
         memset(eventq, 0, sizeof(*eventq));
@@ -167,7 +168,7 @@ npl_freertos_eventq_deinit(struct ble_npl_eventq *evq)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_evq_pool,eventq);
 #else
-    free((void *)eventq);
+    bt_osi_mem_free((void *)eventq);
 #endif
     evq->eventq = NULL;
 }
@@ -357,7 +358,7 @@ npl_freertos_mutex_init(struct ble_npl_mutex *mu)
     }
 #else
     if(!mu->mutex) {
-        mu->mutex = malloc(sizeof(struct ble_npl_mutex_freertos));
+        mu->mutex = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_mutex_freertos));
         mutex = (struct ble_npl_mutex_freertos *)mu->mutex;
 
         if (!mutex) {
@@ -388,7 +389,7 @@ npl_freertos_mutex_deinit(struct ble_npl_mutex *mu)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_mutex_pool,mutex);
 #else
-    free((void *)mutex);
+    bt_osi_mem_free((void *)mutex);
 #endif
     mu->mutex = NULL;
 
@@ -494,7 +495,7 @@ npl_freertos_sem_init(struct ble_npl_sem *sem, uint16_t tokens)
     }
 #else
     if(!sem->sem) {
-        sem->sem = malloc(sizeof(struct ble_npl_sem_freertos));
+        sem->sem = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_sem_freertos));
         semaphore = (struct ble_npl_sem_freertos *)sem->sem;
 
         if (!semaphore) {
@@ -525,7 +526,7 @@ npl_freertos_sem_deinit(struct ble_npl_sem *sem)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_sem_pool,semaphore);
 #else
-    free((void *)semaphore);
+    bt_osi_mem_free((void *)semaphore);
 #endif
     sem->sem = NULL;
 
@@ -684,7 +685,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 #else
 
     if(!co->co) {
-        co->co = malloc(sizeof(struct ble_npl_callout_freertos));
+        co->co = bt_osi_mem_malloc_internal(sizeof(struct ble_npl_callout_freertos));
         callout = (struct ble_npl_callout_freertos *)co->co;
         if (!callout) {
             return -1;
@@ -704,7 +705,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (esp_timer_create(&create_args, &callout->handle) != ESP_OK) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -713,7 +714,7 @@ npl_freertos_callout_init(struct ble_npl_callout *co, struct ble_npl_eventq *evq
 
         if (!callout->handle) {
             ble_npl_event_deinit(&callout->ev);
-            free((void *)callout);
+            bt_osi_mem_free((void *)callout);
             co->co = NULL;
             return -1;
         }
@@ -761,7 +762,7 @@ npl_freertos_callout_deinit(struct ble_npl_callout *co)
 #if OS_MEM_ALLOC
     os_memblock_put(&ble_freertos_co_pool,callout);
 #else
-    free((void *)callout);
+    bt_osi_mem_free((void *)callout);
 #endif // OS_MEM_ALLOC
     co->co = NULL;
     memset(co, 0, sizeof(struct ble_npl_callout));
@@ -1089,7 +1090,7 @@ struct npl_funcs_t * npl_freertos_funcs_get(void)
 
 void npl_freertos_funcs_init(void)
 {
-    npl_funcs = (struct npl_funcs_t *)malloc(sizeof(struct npl_funcs_t));
+    npl_funcs = (struct npl_funcs_t *)bt_osi_mem_malloc_internal(sizeof(struct npl_funcs_t));
     if(!npl_funcs) {
         printf("npl funcs init failed\n");
         assert(0);
@@ -1123,7 +1124,7 @@ int npl_freertos_mempool_init(void)
     ble_freertos_total_event_cnt = ble_total_evt_count;
 
     if (ble_total_evt_count) {
-        ble_freertos_ev_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evt_count,
+        ble_freertos_ev_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evt_count,
                                       sizeof (struct ble_npl_event_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_ev_buf) {
@@ -1138,7 +1139,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_evtq_count) {
-        ble_freertos_evq_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_evtq_count,
+        ble_freertos_evq_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_evtq_count,
                                        sizeof (struct ble_npl_eventq_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_evq_buf) {
@@ -1153,7 +1154,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_co_count) {
-        ble_freertos_co_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_co_count,
+        ble_freertos_co_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_co_count,
                                       sizeof (struct ble_npl_callout_freertos)) *
                                       sizeof(os_membuf_t));
         if (!ble_freertos_co_buf) {
@@ -1168,7 +1169,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_sem_count) {
-        ble_freertos_sem_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_sem_count,
+        ble_freertos_sem_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_sem_count,
                                        sizeof (struct ble_npl_sem_freertos)) *
                                        sizeof(os_membuf_t));
         if (!ble_freertos_sem_buf) {
@@ -1183,7 +1184,7 @@ int npl_freertos_mempool_init(void)
     }
 
     if (ble_total_mutex_count) {
-        ble_freertos_mutex_buf  = malloc(OS_MEMPOOL_SIZE(ble_total_mutex_count,
+        ble_freertos_mutex_buf  = bt_osi_mem_malloc_internal(OS_MEMPOOL_SIZE(ble_total_mutex_count,
                                          sizeof (struct ble_npl_mutex_freertos)) *
                                          sizeof(os_membuf_t));
         if (!ble_freertos_mutex_buf) {
@@ -1200,27 +1201,27 @@ int npl_freertos_mempool_init(void)
     return 0;
 _error:
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
 
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
 
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
 
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
 
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
     return -1;
@@ -1229,23 +1230,23 @@ _error:
 void npl_freertos_mempool_deinit(void)
 {
     if (ble_freertos_ev_buf) {
-        free(ble_freertos_ev_buf);
+        bt_osi_mem_free(ble_freertos_ev_buf);
         ble_freertos_ev_buf = NULL;
     }
     if (ble_freertos_evq_buf) {
-        free(ble_freertos_evq_buf);
+        bt_osi_mem_free(ble_freertos_evq_buf);
         ble_freertos_evq_buf = NULL;
     }
     if (ble_freertos_co_buf) {
-        free(ble_freertos_co_buf);
+        bt_osi_mem_free(ble_freertos_co_buf);
         ble_freertos_co_buf = NULL;
     }
     if (ble_freertos_sem_buf) {
-        free(ble_freertos_sem_buf);
+        bt_osi_mem_free(ble_freertos_sem_buf);
         ble_freertos_sem_buf = NULL;
     }
     if (ble_freertos_mutex_buf) {
-        free(ble_freertos_mutex_buf);
+        bt_osi_mem_free(ble_freertos_mutex_buf);
         ble_freertos_mutex_buf = NULL;
     }
 }
@@ -1253,7 +1254,7 @@ void npl_freertos_mempool_deinit(void)
 void npl_freertos_funcs_deinit(void)
 {
     if (npl_funcs) {
-        free(npl_funcs);
+        bt_osi_mem_free(npl_funcs);
     }
     npl_funcs = NULL;
 }

components/esp_common/src/esp_err_to_name.c

@@ -469,6 +469,11 @@ static const esp_err_msg_t esp_err_msg_table[] = {
 #   endif
 #   ifdef      ESP_ERR_DPP_AUTH_TIMEOUT
     ERR_TBL_IT(ESP_ERR_DPP_AUTH_TIMEOUT),                       /* 12442 0x309a DPP Auth response was not received in time */
+#   endif
+#   ifdef      ESP_ERR_DPP_INVALID_LIST
+    ERR_TBL_IT(ESP_ERR_DPP_INVALID_LIST),                       /* 12443 0x309b Channel list given in
+                                                                                esp_supp_dpp_bootstrap_gen() is not
+                                                                                valid or too big */
 #   endif
     // components/esp_common/include/esp_err.h
 #   ifdef      ESP_ERR_MESH_BASE

components/esp_hw_support/include/esp_crypto_lock.h

@@ -44,7 +44,7 @@ void esp_crypto_ds_lock_acquire(void);
 void esp_crypto_ds_lock_release(void);
 #endif /* SOC_DIG_SIGN_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 /**
  * @brief Acquire lock for the SHA and AES cryptography peripheral.
  *
@@ -56,9 +56,9 @@ void esp_crypto_sha_aes_lock_acquire(void);
  *
  */
 void esp_crypto_sha_aes_lock_release(void);
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
-#if defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA)
+#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
 /**
  * This API should be used by all components which use the SHA, AES, HMAC and DS crypto hardware on the ESP32S2.
  * They can not be used in parallel because they use the same DMA or are calling each other.
@@ -76,7 +76,7 @@ void esp_crypto_dma_lock_acquire(void);
  * Release lock for the AES and SHA cryptography peripherals, which both use the crypto DMA.
  */
 void esp_crypto_dma_lock_release(void);
-#endif /* defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA) */
+#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
 
 #ifdef SOC_MPI_SUPPORTED
 /**

components/esp_hw_support/include/esp_private/sleep_modem.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,7 +120,7 @@ bool modem_domain_pd_allowed(void);
 uint32_t sleep_modem_reject_triggers(void);
 
 /**
- * @brief Configure the parameters of the modem subsytem during the sleep process
+ * @brief Configure the parameters of the modem subsystem during the sleep process
  *
  * In light sleep mode, the wake-up early time of the WiFi module and the TBTT
  * interrupt early time (trigger enabling RF) are determined by the maximum and
@@ -132,7 +132,7 @@ uint32_t sleep_modem_reject_triggers(void);
  *
  * @param max_freq_mhz       the maximum frequency of system
  * @param min_freq_mhz       the minimum frequency of system
- * @param light_sleep_enable ture or false for enable or disable light sleep mode, respectively
+ * @param light_sleep_enable true or false for enable or disable light sleep mode, respectively
  *
  * @return
  *  - ESP_OK on success
@@ -225,6 +225,27 @@ void sleep_modem_wifi_modem_state_deinit(void);
   *   - false not skip light sleep
  */
 bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
+
+/**
+ * @brief Function to initialize and create the modem state phy link
+ * @param link_head the pointer that point to the head of the created phy link
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_NO_MEM if no memory for link
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_init(void **link_head);
+
+/**
+ * @brief Function to destroy and de-initialize modem state phy link
+ * @param link_head the phy link head will be destroyed
+ * @return
+ *   - ESP_OK on success
+ *   - ESP_ERR_INVALID_ARG if value is out of range
+ *   - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
+ */
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
 #endif
 
 #ifdef __cplusplus

components/esp_hw_support/lowpower/CMakeLists.txt

@@ -24,6 +24,10 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S
     list(APPEND srcs "port/${target}/sleep_clock.c")
 endif()
 
+if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
+    list(APPEND srcs "port/${target}/sleep_modem_state.c")
+endif()
+
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -6,6 +6,7 @@
 
 #include "esp_private/sleep_clock.h"
 #include "soc/pcr_reg.h"
+#include "soc/rtc.h"
 #include "modem/modem_syscon_reg.h"
 #include "modem/modem_lpcon_reg.h"
 #include "soc/i2c_ana_mst_reg.h"
@@ -14,13 +15,43 @@ static const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
-        [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+        [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG,  0,               PCR_AHB_DIV_NUM,      1, 0),                                     .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1,               PCR_BUS_CLOCK_UPDATE, 1, 0),                                     .owner = ENTRY(0) | ENTRY(1) },
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+        [2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE,        DR_REG_PCR_BASE, 74,                   0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+#endif
     };
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
+
+    const static sleep_retention_entries_config_t modem_ahb_config[] = {
+        [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), PCR_AHB_FREQ_CONF_REG,  3, PCR_AHB_DIV_NUM,      1, 0), .owner = ENTRY(1) }, /* Set AHB bus frequency to 40 MHz under PMU MODEM state */
+        [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(1) },
+    };
+    err = sleep_retention_entries_create(modem_ahb_config, ARRAY_SIZE(modem_ahb_config), REGDMA_LINK_PRI_4, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention, 4 level priority");
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
+    uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+    if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
+
+        /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
+         * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
+         * command memory */
+        sleep_retention_entries_config_t bbpll_config[] = {
+            [0] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(5), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST enable */
+            [1] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(6), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                          0xffffffff,                   1, 0), .owner = ENTRY(1) },
+            [2] = { .config = REGDMA_LINK_WAIT_INIT    (REGDMA_PCR_LINK(7), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,     0x1,                          1, 0), .owner = ENTRY(1) },
+            [3] = { .config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(8), MODEM_LPCON_CLK_CONF_REG,         0,                          MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(1) }, /* I2C MST disable */
+        };
+        extern uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+        bbpll_config[1].config.write_wait.value = phy_ana_i2c_master_burst_bbpll_config();
+        err = sleep_retention_entries_create(bbpll_config, ARRAY_SIZE(bbpll_config), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+        ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for bbpll configure, 0 level priority");
+    }
 #endif
+
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
 }

components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c

@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0158)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a001c)
+#define FECOEX_SET_CHAN_EN              (BIT(17))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+static __attribute__((unused)) const char *TAG = "sleep";
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
+{
+    #define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
+
+    static sleep_retention_entries_config_t wifi_modem_config[] = {
+        [0]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [1]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
+        [2]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG,                   0xf3800000,                0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [3]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0), .owner = WIFIMAC_ENTRY() },
+        [4]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [5]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [6]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [7]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    1, 0), .owner = WIFIMAC_ENTRY() },
+        [8]  = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0), .owner = WIFIMAC_ENTRY() },
+        [9]  = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0), .owner = WIFIMAC_ENTRY() },
+        [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU to trigger enable RXBLOCK */
+        [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0), .owner = WIFIMAC_ENTRY() },
+
+        /* PMU or software to trigger disable RF PHY */
+        [12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1), .owner = WIFIMAC_ENTRY() },
+        [14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x20000,    0, 1), .owner = WIFIMAC_ENTRY() },
+        [15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
+        [16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 1), .owner = WIFIMAC_ENTRY() },
+        [17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1), .owner = WIFIMAC_ENTRY() },
+        [18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG,                   0,                         0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
+        [19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
+
+        [20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1), .owner = WIFIMAC_ENTRY() },
+        [23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1), .owner = WIFIMAC_ENTRY() },
+
+        [24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
+        [25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[4].config.write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+    esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
+    ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
+    return ESP_OK;
+}
+#endif
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
+    err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
+    if (err == ESP_OK) {
+        err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
+        if (err == ESP_OK) {
+            *link_head = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00));
+        }
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+    esp_err_t err = ESP_OK;
+#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    if (err == ESP_OK) {
+        sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
+    }
+#endif
+    return err;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c

@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "soc/soc_caps.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+
+#include "modem/modem_syscon_reg.h"
+#include "modem/modem_lpcon_reg.h"
+
+#include "esp_private/esp_pau.h"
+#include "esp_private/sleep_modem.h"
+#include "esp_private/sleep_retention.h"
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+#define SARADC_TSENS_REG                (0x6000e058)
+#define SARADC_TSENS_PU                 (BIT(22))
+#define PMU_RF_PWR_REG                  (0x600b0154)
+
+#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
+#define FECOEX_SET_CHAN_EN              (BIT(14))
+#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
+#define FECOEX_SET_CHAN_DONE            (BIT(8))
+#define FECOEX_AGC_CONF_REG             (0x600a7030)
+#define FECOEX_AGC_DIS                  (BIT(29))
+
+#define WDEVTXQ_BLOCK                   (0x600A4ca8)
+#define WDEV_RXBLOCK                    (BIT(12))
+#define MODEM_FE_DATA_BASE              (0x600a0400)
+#define MODEM_FE_CTRL_BASE              (0x600a0800)
+
+esp_err_t sleep_modem_state_phy_link_init(void **link_head)
+{
+    esp_err_t err = ESP_OK;
+
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    static regdma_link_config_t wifi_modem_config[] = {
+        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
+        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
+
+        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
+        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
+
+        /* PMU or software to trigger enable RF PHY */
+        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
+        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
+        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
+        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
+        [8]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [9]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        1, 0),
+        [10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
+        [11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
+        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
+        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG,                     ~FECOEX_SET_CHAN_DONE,     0x100,      1, 0),
+        [15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
+        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
+        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
+
+        /* PMU to trigger enable RXBLOCK */
+        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
+
+        /* PMU or software to trigger disable RF PHY */
+        [19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
+        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
+        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
+        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
+        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG,                     ~I2C_ANA_MST_BURST_DONE,   0x1,        0, 1),
+        [25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
+        [26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
+        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
+        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
+
+        [29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
+
+        /* PMU to trigger disable RXBLOCK */
+        [30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+        [33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
+        [34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG,                     ~0,                        0x6000,     0, 1),
+        [36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
+
+        [37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
+        [38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
+    };
+    extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+    wifi_modem_config[7].write_wait.value  = phy_ana_i2c_master_burst_rf_onoff(true);
+    wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
+
+    void *link = NULL;
+    for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
+        void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
+        if (next) {
+            link = next;
+        } else {
+            regdma_link_destroy(link, 0);
+            err = ESP_ERR_NO_MEM;
+        }
+    }
+    if (err == ESP_OK) {
+        pau_regdma_set_modem_link_addr(link);
+        *link_head = link;
+    }
+#endif
+    return err;
+}
+
+esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
+{
+#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
+    regdma_link_destroy(link_head, 0);
+#endif
+    return ESP_OK;
+}
+
+#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

components/esp_hw_support/port/esp32c5/Kconfig.rtc

@@ -35,3 +35,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 48 MHz external crystal clock (XTAL) can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 48 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "48 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp32p4/Kconfig.rtc

@@ -37,3 +37,24 @@ config RTC_CLK_CAL_CYCLES
         - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
             In case more value will help improve the definition of the launch of the crystal.
             If the crystal could not start, it will be switched to internal RC.
+
+choice RTC_FAST_CLK_SRC
+    depends on SOC_CLK_LP_FAST_SUPPORT_XTAL
+    prompt "RTC fast clock source"
+    default RTC_FAST_CLK_SRC_RC_FAST
+    help
+        Choose which clock is used as RTC fast clock source.
+
+        Choosing the faster 40 MHz XTAL can allow modules which depend on RTC_FAST
+        to work at a higher clock frequency. With this the ULP LP-Core will run with a
+        CPU frequency of 40 Mhz instead of the default 20 Mhz.
+
+        The drawback is that the XTAL is usually powered down during sleep, as
+        it draw a lot of power. Choosing this option will cause the XTAL to stay
+        powered on, increasing sleep power consumption.
+
+    config RTC_FAST_CLK_SRC_RC_FAST
+        bool "20 Mhz RC Fast Clock"
+    config RTC_FAST_CLK_SRC_XTAL
+        bool "40 Mhz crystal (increased power consumption during sleep)"
+endchoice

components/esp_hw_support/port/esp_clk_tree_common.c

@@ -191,7 +191,7 @@ uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
     case SOC_RTC_FAST_CLK_SRC_LP_PLL:
         return clk_ll_lp_pll_get_freq_mhz() * MHZ;
 #endif
-#if SOC_CLK_LP_FAST_SUPPORT_XTAL
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
     case SOC_RTC_FAST_CLK_SRC_XTAL:
         return clk_hal_xtal_get_freq_mhz() * MHZ;
 #endif

components/esp_hw_support/sleep_modem.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,24 +12,19 @@
 #include "esp_log.h"
 #include "esp_attr.h"
 #include "esp_sleep.h"
+#include "esp_check.h"
 #include "soc/soc_caps.h"
 #include "esp_private/pm_impl.h"
 #include "esp_private/sleep_modem.h"
 #include "esp_private/sleep_retention.h"
 #include "sdkconfig.h"
 
-#if SOC_PM_MODEM_RETENTION_BY_REGDMA
-#include "modem/modem_syscon_reg.h"
-#include "modem/modem_lpcon_reg.h"
-#include "soc/i2c_ana_mst_reg.h"
-#include "esp_pau.h"
-#endif
-
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
-#include "soc/pmu_reg.h"
-#include "esp_private/esp_pau.h"
 #include "esp_private/esp_pmu.h"
 #endif
+#if SOC_PM_MODEM_RETENTION_BY_REGDMA
+#include "esp_pau.h"
+#endif
 
 static __attribute__((unused)) const char *TAG = "sleep_modem";
 
@@ -136,29 +131,6 @@ void IRAM_ATTR mac_bb_power_up_cb_execute(void)
 
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE
 
-#define PMU_RF_PWR_REG                  (0x600b0154)
-#define SARADC_TSENS_REG                (0x6000e058)
-#define SARADC_TSENS_PU                 (BIT(22))
-#define FECOEX_SET_FREQ_SET_CHAN_REG    (0x600a00c0)
-#define FECOEX_SET_CHAN_EN              (BIT(14))
-#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
-#define FECOEX_SET_CHAN_DONE            (BIT(8))
-#define FECOEX_AGC_CONF_REG             (0x600a7030)
-#define FECOEX_AGC_DIS                  (BIT(29))
-#define WDEVTXQ_BLOCK                   (0x600A4ca8)
-#define WDEV_RXBLOCK                    (BIT(12))
-#define MODEM_FE_DATA_BASE              (0x600a0400)
-#define MODEM_FE_CTRL_BASE              (0x600a0800)
-
-#define I2C_BURST_VAL(host, start, end) (((host) << 31) | ((end) << 22) | ((start) << 16))
-
-typedef struct {
-    struct {
-        uint8_t start, end; /* the start and end index of phy i2c master command memory */
-        uint8_t host_id;    /* phy i2c master host id */
-    } config[2];
-} phy_i2c_master_command_attribute_t;
-
 typedef struct sleep_modem_config {
     struct {
         void    *phy_link;
@@ -174,76 +146,15 @@ typedef struct sleep_modem_config {
 
 static sleep_modem_config_t s_sleep_modem = { .wifi.phy_link = NULL, .wifi.flags = 0 };
 
+
 esp_err_t sleep_modem_wifi_modem_state_init(void)
 {
     esp_err_t err = ESP_OK;
-    phy_i2c_master_command_attribute_t cmd;
-
-    /* get RF on or off configuration info of i2c master command memory */
-    extern void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *);
-    phy_i2c_master_mem_cfg(&cmd);
-
-    ESP_LOGD(TAG, "Modem link i2c master configuration: (%d,%d,%d), (%d,%d,%d)", cmd.config[0].host_id, cmd.config[0].start,
-            cmd.config[0].end, cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-
-    static regdma_link_config_t wifi_modem_config[] = {
-        [0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
-        [1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
-
-        [2]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG,         MODEM_LPCON_CLK_I2C_MST_EN,        MODEM_LPCON_CLK_I2C_MST_EN_M,       1, 0), /* I2C MST enable */
-        [3]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M,  MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
-
-        /* PMU or software to trigger enable RF PHY */
-        [4]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG,        0x8,                       0xc,        1, 0), /* BBPLL calibration enable */
-        [5]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG,                   0xf0000000,                0xf0000000, 1, 0),
-        [6]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG,                 SARADC_TSENS_PU,           0x400000,   1, 0),
-        [7]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 1, 0),
-        [8]  = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        1, 0),
-        [9]  = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG,     FECOEX_SET_CHAN_EN,        0x4000,     1, 0),
-        [10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     1, 0),
-        [11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_ST_REG,  FECOEX_SET_CHAN_DONE,      0x100,      1, 0),
-        [12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), MODEM_SYSCON_WIFI_BB_CFG_REG,     BIT(1),                    0x2,        1, 0),
-        [13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), FECOEX_AGC_CONF_REG,              0,                         0x20000000, 1, 0),
-
-        /* PMU to trigger enable RXBLOCK */
-        [14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), WDEVTXQ_BLOCK,                    0,                         0x1000,     1, 0),
-
-        /* PMU or software to trigger disable RF PHY */
-        [15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), FECOEX_AGC_CONF_REG,              FECOEX_AGC_DIS,            0x20000000, 0, 1),
-        [16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG,     0,                         0x2,        0, 1),
-        [17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_SET_FREQ_SET_CHAN_REG,     0,                         0x4000,     0, 1),
-        [18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_CONF_REG,   0,                         0xffffffff, 0, 1),
-        [19] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x11), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE,    0x1,        0, 1),
-        [20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), SARADC_TSENS_REG,                 0,                         0x400000,   0, 1),
-        [21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), PMU_RF_PWR_REG,                   0,                         0xf0000000, 0, 1),
-        [22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_ANA_CONF0_REG,        0x4,                       0xc,        0, 1), /* BBPLL calibration disable */
-
-        [23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), MODEM_LPCON_CLK_CONF_REG,         0,                         MODEM_LPCON_CLK_I2C_MST_EN_M,       0, 1), /* I2C MST disable */
-
-        /* PMU to trigger disable RXBLOCK */
-        [24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-        [25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), WDEVTXQ_BLOCK,                    WDEV_RXBLOCK,              0x1000,     0, 1),
-        [26] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x19), WDEVTXQ_BLOCK,                    0,                         0x6000,     0, 1),
-
-        [27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), PMU_SLP_WAKEUP_CNTL7_REG,         0x200000,                  0xffff0000, 1, 0),
-        [28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_SLP_WAKEUP_CNTL7_REG,         0x9730000,                 0xffff0000, 0, 1)
-    };
-    wifi_modem_config[7].write_wait.value  = I2C_BURST_VAL(cmd.config[1].host_id, cmd.config[1].start, cmd.config[1].end);
-    wifi_modem_config[18].write_wait.value = I2C_BURST_VAL(cmd.config[0].host_id, cmd.config[0].start, cmd.config[0].end);
 
     void *link = NULL;
     if (s_sleep_modem.wifi.phy_link == NULL) {
-        for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
-            void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
-            if (next) {
-                link = next;
-            } else {
-                regdma_link_destroy(link, 0);
-                err = ESP_ERR_NO_MEM;
-            }
-        }
+        err = sleep_modem_state_phy_link_init(&link);
         if (err == ESP_OK) {
-            pau_regdma_set_modem_link_addr(link);
             s_sleep_modem.wifi.phy_link = link;
             s_sleep_modem.wifi.flags = 0;
         }
@@ -254,7 +165,7 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
 __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
 {
     if (s_sleep_modem.wifi.phy_link) {
-        regdma_link_destroy(s_sleep_modem.wifi.phy_link, 0);
+        sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link);
         s_sleep_modem.wifi.phy_link = NULL;
         s_sleep_modem.wifi.flags = 0;
     }

components/esp_lcd/test_apps/.build-test-rules.yml

@@ -52,7 +52,3 @@ components/esp_lcd/test_apps/spi_lcd:
     - esp_driver_spi
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: test failed # TODO: ESP32C61 IDF-10953

components/esp_lcd/test_apps/spi_lcd/main/test_spi_board.h

@@ -28,6 +28,13 @@ extern "C" {
 #define TEST_LCD_DC_GPIO        1
 #define TEST_LCD_PCLK_GPIO      2
 #define TEST_LCD_DATA0_GPIO     4
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define TEST_LCD_BK_LIGHT_GPIO  3
+#define TEST_LCD_RST_GPIO       5
+#define TEST_LCD_CS_GPIO        0
+#define TEST_LCD_DC_GPIO        1
+#define TEST_LCD_PCLK_GPIO      2
+#define TEST_LCD_DATA0_GPIO     4
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TEST_LCD_BK_LIGHT_GPIO  23
 #define TEST_LCD_RST_GPIO       6

components/esp_lcd/test_apps/spi_lcd/pytest_spi_lcd.py

@@ -5,7 +5,6 @@ from pytest_embedded import Dut
 
 
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail')    # TODO: [ESP32C61] IDF-10953
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',

components/esp_phy/include/esp_private/phy.h

@@ -13,17 +13,12 @@ extern "C" {
 
 #define ESP_CAL_DATA_CHECK_FAIL 1
 
-typedef enum {
-    PHY_I2C_MST_CMD_TYPE_OFF = 0,
-    PHY_I2C_MST_CMD_TYPE_ON,
-    PHY_I2C_MST_CMD_TYPE_MAX
-} phy_i2c_master_command_type_t;
-
 typedef struct {
+    uint8_t cmd_type;   /* the command type of the current phy i2c master command memory config */
     struct {
         uint8_t start, end; /* the start and end index of phy i2c master command memory */
         uint8_t host_id;    /* phy i2c master host id */
-    } config[PHY_I2C_MST_CMD_TYPE_MAX];
+    } config;
 } phy_i2c_master_command_attribute_t;
 
 /**
@@ -88,13 +83,14 @@ void phy_xpd_tsens(void);
 void phy_init_flag(void);
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C6
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
 /**
  * @brief Get the configuration info of PHY i2c master command memory.
  *
- * @param   attr the configuration info of PHY i2c master command memory
+ * @param[out] attr  the configuration info of PHY i2c master command memory
+ * @param[out] size  the count of PHY i2c master command memory configuration
  */
-void phy_i2c_master_mem_cfg(phy_i2c_master_command_attribute_t *attr);
+void phy_i2c_master_command_mem_cfg(phy_i2c_master_command_attribute_t *attr, int *size);
 #endif
 
 /**
@@ -217,6 +213,23 @@ void phy_ant_clr_update_flag(void);
  */
 void phy_ant_update(void);
 
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+/**
+ * @brief Get the REGDMA config value of the BBPLL in analog i2c master burst mode
+ *
+ * @return  the BBPLL REGDMA configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_bbpll_config(void);
+
+/**
+ * @brief Get the REGDMA config value of the RF PHY on or off in analog i2c master burst mode
+ *
+ * @param[in] on true for enable RF PHY, false for disable RF PHY.
+ *
+ * @return  the RF on or off configure value of i2c master burst mode
+ */
+uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
+#endif
 
 #ifdef __cplusplus
 }

components/esp_phy/lib

@@ -1 +1 @@
-Subproject commit 8608fcf54d51e81f2e74ebf335fa33f61953f7c8
+Subproject commit 1f551c5367daa87a29e0c4f724d6cf809a1841ad

components/esp_phy/src/phy_common.c

@@ -294,3 +294,57 @@ esp_err_t esp_phy_get_ant(esp_phy_ant_config_t *config)
     memcpy(config, &s_phy_ant_config, sizeof(esp_phy_ant_config_t));
     return ESP_OK;
 }
+
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE
+typedef enum {
+    PHY_I2C_MST_CMD_TYPE_RF_OFF = 0,
+    PHY_I2C_MST_CMD_TYPE_RF_ON,
+    PHY_I2C_MST_CMD_TYPE_BBPLL_CFG,
+    PHY_I2C_MST_CMD_TYPE_MAX
+} phy_i2c_master_command_type_t;
+
+static uint32_t phy_ana_i2c_master_burst_config(phy_i2c_master_command_attribute_t *attr, int size, phy_i2c_master_command_type_t type)
+{
+    #define I2C1_BURST_VAL(en, start, end) (((en) << 31) | ((end) << 22) | ((start) << 16))
+    #define I2C0_BURST_VAL(en, start, end) (((en) << 15) | ((end) <<  6) | ((start) <<  0))
+
+    uint32_t brust = 0;
+    for (int i = 0; i < size; i++) {
+        if (attr[i].config.start == 0xff || attr[i].config.end == 0xff) /* ignore invalid configure */
+            continue;
+
+        if (attr[i].cmd_type == type) {
+            if (attr[i].config.host_id) {
+                brust |= I2C1_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
+            } else {
+                brust |= I2C0_BURST_VAL(1, attr[i].config.start, attr[i].config.end);
+            }
+        }
+    }
+    return brust;
+}
+
+uint32_t phy_ana_i2c_master_burst_bbpll_config(void)
+{
+    /* PHY supports 2 I2C masters, and the maximum number of configurations
+     * supported by the I2C master command memory is the command type
+     * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
+    phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
+    int size = sizeof(cmd) / sizeof(cmd[0]);
+    phy_i2c_master_command_mem_cfg(cmd, &size);
+
+    return phy_ana_i2c_master_burst_config(cmd, size, PHY_I2C_MST_CMD_TYPE_BBPLL_CFG);
+}
+
+uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on)
+{
+    /* PHY supports 2 I2C masters, and the maximum number of configurations
+     * supported by the I2C master command memory is the command type
+     * (PHY_I2C_MST_CMD_TYPE_MAX) multiplied by 2 */
+    phy_i2c_master_command_attribute_t cmd[2 * PHY_I2C_MST_CMD_TYPE_MAX];
+    int size = sizeof(cmd) / sizeof(cmd[0]);
+    phy_i2c_master_command_mem_cfg(cmd, &size);
+
+    return phy_ana_i2c_master_burst_config(cmd, size, on ? PHY_I2C_MST_CMD_TYPE_RF_ON : PHY_I2C_MST_CMD_TYPE_RF_OFF);
+}
+#endif

components/esp_phy/src/phy_init.c

@@ -45,7 +45,7 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
+#elif SOC_PM_SUPPORT_PMU_MODEM_STATE
 #include "esp_private/sleep_modem.h"
 #endif
 #include "hal/efuse_hal.h"
@@ -383,7 +383,7 @@ void esp_phy_modem_init(void)
         s_phy_digital_regs_mem = (uint32_t *)heap_caps_malloc(SOC_PHY_DIG_REGS_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
     }
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     sleep_modem_wifi_modem_state_init();
 #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     _lock_release(&s_phy_access_lock);
@@ -408,7 +408,7 @@ void esp_phy_modem_deinit(void)
         phy_init_flag();
 #endif // CONFIG_IDF_TARGET_ESP32C3
 #endif // SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
-#if CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
         sleep_modem_wifi_modem_state_deinit();
 #endif // CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
     }
@@ -431,7 +431,12 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg)
         [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b01, 0x600a7400, 0x600a7400, 14,  0, 0), .owner = BIT(0) | BIT(1) }, /* TX */
         [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b02, 0x600a7800, 0x600a7800, 136, 0, 0), .owner = BIT(0) | BIT(1) }, /* NRX */
         [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b03, 0x600a7c00, 0x600a7c00, 53,  0, 0), .owner = BIT(0) | BIT(1) }, /* BB */
-        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58,  0, 0), .owner = BIT(0) | BIT(1) }  /* FE COEX */
+        [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b05, 0x600a0000, 0x600a0000, 58,  0, 0), .owner = BIT(0) | BIT(1) }, /* FE COEX */
+#ifndef SOC_PM_RETENTION_HAS_CLOCK_BUG
+        [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x000a8000, 39,  0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */
+        [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, 41,  0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */
+        [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, 87,  0, 0), .owner = BIT(0) | BIT(1) }  /* FE CTRL */
+#endif
     };
     esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB");

components/esp_ringbuf/test_apps/pytest_esp_ringbuf.py

@@ -5,9 +5,10 @@ from pytest_embedded import Dut
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
-@pytest.mark.esp32c3
-@pytest.mark.esp32s2
+@pytest.mark.parametrize('target', [
+    'esp32',
+    'esp32s2',
+])
 @pytest.mark.parametrize('config', [
     'default',
     'ringbuf_flash',

components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld

@@ -35,18 +35,18 @@ ic_ebuf_alloc = 0x40000b4c;
 ic_reset_extra_softap_rx_ba = 0x40000b50;
 ieee80211_align_eb = 0x40000b54;
 ieee80211_ampdu_reorder = 0x40000b58;
-ieee80211_ampdu_start_age_timer = 0x40000b5c;
-ieee80211_encap_esfbuf = 0x40000b60;
+/*ieee80211_ampdu_start_age_timer = 0x40000b5c;*/
+/*ieee80211_encap_esfbuf = 0x40000b60;*/
 ieee80211_is_tx_allowed = 0x40000b64;
-ieee80211_output_pending_eb = 0x40000b68;
-ieee80211_output_process = 0x40000b6c;
+/*ieee80211_output_pending_eb = 0x40000b68;*/
+/*ieee80211_output_process = 0x40000b6c;*/
 /*ieee80211_set_tx_desc = 0x40000b70;*/
 ieee80211_classify = 0x40000b74;
 ieee80211_copy_eb_header = 0x40000b78;
 ieee80211_recycle_cache_eb = 0x40000b7c;
 ieee80211_search_node = 0x40000b80;
-ieee80211_crypto_encap = 0x40000b84;
-ieee80211_crypto_decap = 0x40000b88;
+/*ieee80211_crypto_encap = 0x40000b84;*/
+/*ieee80211_crypto_decap = 0x40000b88;*/
 ieee80211_decap = 0x40000b8c;
 ieee80211_set_tx_pti = 0x40000b90;
 ieee80211_gettid = 0x40000b94;
@@ -61,12 +61,12 @@ ieee80211_find_ie = 0x40000bb4;
 ieee80211_find_ext_ie = 0x40000bb8;
 ieee80211_merge_mbssid_profile = 0x40000bbc;
 ieee80211_encap_esfbuf_htc = 0x40000bc0;
-wifi_get_macaddr = 0x40000bc4;
-wifi_rf_phy_disable = 0x40000bc8;
-wifi_rf_phy_enable = 0x40000bcc;
-wifi_is_started = 0x40000bd0;
+/*wifi_get_macaddr = 0x40000bc4;*/
+/*wifi_rf_phy_disable = 0x40000bc8;*/
+/*wifi_rf_phy_enable = 0x40000bcc;*/
+/*wifi_is_started = 0x40000bd0;*/
 /*sta_input = 0x40000bd4;*/
-sta_rx_eapol = 0x40000bd8;
+/*sta_rx_eapol = 0x40000bd8;*/
 sta_reset_beacon_timeout = 0x40000bdc;
 sta_get_beacon_timeout = 0x40000be0;
 ampdu_process_multicast_address_qos_frame = 0x40000be4;

components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld

@@ -55,7 +55,7 @@ dbg_hal_check_clr_mplen_bitmap = 0x40000c6c;
 dbg_hal_check_set_mplen_bitmap = 0x40000c70;
 ic_get_trc = 0x40000c74;
 ic_mac_deinit = 0x40000c78;
-ic_mac_init = 0x40000c7c;
+/* ic_mac_init = 0x40000c7c; */
 ic_interface_enabled = 0x40000c80;
 is_lmac_idle = 0x40000c84;
 ic_get_he_rts_threshold_bytes = 0x40000c88;

components/esp_rom/patches/esp_rom_tlsf.c

@@ -20,91 +20,12 @@
 #include "esp_rom_caps.h"
 #include "esp_rom_tlsf.h"
 
-/*!
- * @brief Opaque types for TLSF implementation
- */
+#include "tlsf_block_functions.h"
+#include "tlsf_control_functions.h"
+
+/* Definition of types used in TLSF */
 typedef void* tlsf_t;
 typedef void* pool_t;
-typedef ptrdiff_t tlsfptr_t;
-
-/* ----------------------------------------------------------------
- * Bring certain inline functions, macro and structures from the
- * tlsf ROM implementation to be able to compile the patch.
- * ---------------------------------------------------------------- */
-
-#if !defined (tlsf_assert)
-#define tlsf_assert assert
-#endif
-
-#define tlsf_cast(t, exp)	((t) (exp))
-
-#define block_header_free_bit  (1 << 0)
-#define block_header_prev_free_bit  (1 << 1)
-#define block_header_overhead  (sizeof(size_t))
-#define block_start_offset (offsetof(block_header_t, size) + sizeof(size_t))
-
-typedef struct block_header_t
-{
-    /* Points to the previous physical block. */
-    struct block_header_t* prev_phys_block;
-
-    /* The size of this block, excluding the block header. */
-    size_t size;
-
-    /* Next and previous free blocks. */
-    struct block_header_t* next_free;
-    struct block_header_t* prev_free;
-} block_header_t;
-
-static inline __attribute__((__always_inline__)) size_t block_size(const block_header_t* block)
-{
-    return block->size & ~(block_header_free_bit | block_header_prev_free_bit);
-}
-
-static inline __attribute__((__always_inline__)) int block_is_free(const block_header_t* block)
-{
-    return tlsf_cast(int, block->size & block_header_free_bit);
-}
-
-static inline __attribute__((__always_inline__)) int block_is_prev_free(const block_header_t* block)
-{
-    return tlsf_cast(int, block->size & block_header_prev_free_bit);
-}
-
-static inline __attribute__((always_inline)) block_header_t* block_from_ptr(const void* ptr)
-{
-	return tlsf_cast(block_header_t*,
-		tlsf_cast(unsigned char*, ptr) - block_start_offset);
-}
-
-static inline __attribute__((always_inline)) block_header_t* offset_to_block(const void* ptr, size_t size)
-{
-	return tlsf_cast(block_header_t*, tlsf_cast(tlsfptr_t, ptr) + size);
-}
-
-static inline __attribute__((always_inline)) int block_is_last(const block_header_t* block)
-{
-	return block_size(block) == 0;
-}
-
-static inline __attribute__((always_inline)) void* block_to_ptr(const block_header_t* block)
-{
-	return tlsf_cast(void*,
-		tlsf_cast(unsigned char*, block) + block_start_offset);
-}
-
-static inline __attribute__((always_inline)) block_header_t* block_next(const block_header_t* block)
-{
-	block_header_t* next = offset_to_block(block_to_ptr(block),
-		block_size(block) - block_header_overhead);
-	tlsf_assert(!block_is_last(block));
-	return next;
-}
-
-/* ----------------------------------------------------------------
- * End of the environment necessary to compile and link the patch
- * defined below
- * ---------------------------------------------------------------- */
 
 static poison_check_pfunc_t s_poison_check_region = NULL;
 
@@ -237,6 +158,7 @@ struct heap_tlsf_stub_table_t {
 extern struct heap_tlsf_stub_table_t* heap_tlsf_table_ptr;
 
 /* We will copy the ROM table and modify the functions we patch */
+
 struct heap_tlsf_stub_table_t heap_tlsf_patch_table_ptr;
 
 /*!

components/esp_security/src/esp_crypto_lock.c

@@ -33,10 +33,10 @@ static _lock_t s_crypto_hmac_lock;
 static _lock_t s_crypto_mpi_lock;
 #endif /* SOC_MPI_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 /* Single lock for SHA and AES, sharing a reserved GDMA channel */
 static _lock_t s_crypto_sha_aes_lock;
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
 #ifdef SOC_ECC_SUPPORTED
 /* Lock for ECC peripheral */
@@ -83,7 +83,7 @@ void esp_crypto_ds_lock_release(void)
 }
 #endif /* SOC_DIG_SIGN_SUPPORTED */
 
-#if defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED)
+#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
 void esp_crypto_sha_aes_lock_acquire(void)
 {
     _lock_acquire(&s_crypto_sha_aes_lock);
@@ -93,9 +93,9 @@ void esp_crypto_sha_aes_lock_release(void)
 {
     _lock_release(&s_crypto_sha_aes_lock);
 }
-#endif /* defined(SOC_SHA_SUPPORTED) && defined(SOC_AES_SUPPORTED) */
+#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
 
-#if defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA)
+#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
 void esp_crypto_dma_lock_acquire(void)
 {
     _lock_acquire(&s_crypto_sha_aes_lock);
@@ -105,7 +105,7 @@ void esp_crypto_dma_lock_release(void)
 {
     _lock_release(&s_crypto_sha_aes_lock);
 }
-#endif /* defined(SOC_SHA_CRYPTO_DMA) && defined(SOC_AES_CRYPTO_DMA) */
+#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
 
 #ifdef SOC_MPI_SUPPORTED
 void esp_crypto_mpi_lock_acquire(void)

components/esp_system/port/cpu_start.c

@@ -751,7 +751,7 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif
 #endif
 
-#if SOC_DEEP_SLEEP_SUPPORTED //TODO: IDF-9245
+#if SOC_DEEP_SLEEP_SUPPORTED
     // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
     if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
         esp_deep_sleep_wakeup_io_reset();

components/esp_system/port/soc/esp32c5/clk.c

@@ -56,8 +56,14 @@ __attribute__((weak)) void esp_clk_init(void)
     assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M));
 
     rtc_clk_8m_enable(true);
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
     rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+    rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
+#else
+#error "No RTC fast clock source configured"
 #endif
+#endif //!CONFIG_IDF_ENV_FPGA
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.

components/esp_system/port/soc/esp32p4/clk.c

@@ -86,7 +86,13 @@ __attribute__((weak)) void esp_clk_init(void)
     assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
 
     rtc_clk_8m_enable(true);
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
     rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+    rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
+#else
+#error "No RTC fast clock source configured"
+#endif
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.

components/esp_wifi/Kconfig

@@ -657,28 +657,28 @@ menu "Wi-Fi"
 
         config ESP_WIFI_ENABLE_DUMP_HESIGB
             bool "Enable Wi-Fi dump HE-SIGB which is contained in DL HE MU PPDUs"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump HE-SIGB which is contained in DL HE MU PPDUs.
 
         config ESP_WIFI_ENABLE_DUMP_MU_CFO
             bool "Enable Wi-Fi dump MU CFO"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump MU CFO.
 
         config ESP_WIFI_ENABLE_DUMP_CTRL_NDPA
             bool "Enable Wi-Fi dump NDPA frames"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump NDPA frames.
 
         config ESP_WIFI_ENABLE_DUMP_CTRL_BFRP
             bool "Enable Wi-Fi dump BFRP frames"
-            depends on SOC_WIFI_HE_SUPPORT_5G
+            depends on SOC_WIFI_SUPPORT_5G
             default "n"
             help
                 Enable Wi-Fi dump BFRP frames.

components/esp_wifi/include/esp_wifi.h

@@ -677,7 +677,7 @@ esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
   * @brief     Set protocol type of specified interface
   *            The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N).
   *            if CONFIG_SOC_WIFI_HE_SUPPORT and band mode is 2.4G, the default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AX).
-  *            if CONFIG_SOC_WIFI_HE_SUPPORT_5G and band mode is 5G, the default protocol is (WIFI_PROTOCOL_11A|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AC|WIFI_PROTOCOL_11AX).
+  *            if CONFIG_SOC_WIFI_SUPPORT_5G and band mode is 5G, the default protocol is (WIFI_PROTOCOL_11A|WIFI_PROTOCOL_11N|WIFI_PROTOCOL_11AC|WIFI_PROTOCOL_11AX).
   *
   * @attention 1. When WiFi band mode is 2.4G only, support 802.11b or 802.11bg or 802.11bgn or 802.11bgnax or LR mode
   * @attention 2. When WiFi band mode is 5G only, support 802.11a or 802.11an or 802.11anac or 802.11anacax
@@ -1653,8 +1653,8 @@ esp_err_t esp_wifi_get_band(wifi_band_t* band);
   * @attention 1. When the WiFi band mode is set to 2.4G only, it operates exclusively on the 2.4GHz channels.
   * @attention 2. When the WiFi band mode is set to 5G only, it operates exclusively on the 5GHz channels.
   * @attention 3. When the WiFi band mode is set to 2.4G + 5G (WIFI_BAND_MODE_AUTO), it can operate on both the 2.4GHz and 5GHz channels.
-  * @attention 4. WiFi band mode can be set to 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO) if CONFIG_SOC_WIFI_HE_SUPPORT_5G is supported.
-  * @attention 5. If CONFIG_SOC_WIFI_HE_SUPPORT_5G is not supported, the API will return ESP_ERR_INVALID_ARG when the band mode is set to either 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO).
+  * @attention 4. WiFi band mode can be set to 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO) if CONFIG_SOC_WIFI_SUPPORT_5G is supported.
+  * @attention 5. If CONFIG_SOC_WIFI_SUPPORT_5G is not supported, the API will return ESP_ERR_INVALID_ARG when the band mode is set to either 5G only or 2.4G + 5G (WIFI_BAND_MODE_AUTO).
   * @attention 6. When a WiFi band mode change triggers a band change, if no channel is set for the current band, a default channel will be assigned: channel 1 for 2.4G band and channel 36 for 5G band.
   *
   * @param[in]    band_mode store the band mode of WiFi
@@ -1717,7 +1717,7 @@ esp_err_t esp_wifi_set_protocols(wifi_interface_t ifx, wifi_protocols_t *protoco
 /**
   * @brief     Get the current protocol of the specified interface and specified band
   *
-  * @attention 1. The 5G protocol can only be read when CONFIG_SOC_WIFI_HE_SUPPORT_5G is enabled.
+  * @attention 1. The 5G protocol can only be read when CONFIG_SOC_WIFI_SUPPORT_5G is enabled.
   * @attention 2. When the WiFi band mode is set to 2.4G only, it will not get 5G protocol
   * @attention 3. When the WiFi band mode is set to 5G only, it will not get 2.4G protocol
   *
@@ -1756,7 +1756,7 @@ esp_err_t esp_wifi_set_bandwidths(wifi_interface_t ifx, wifi_bandwidths_t* bw);
 /**
   * @brief     Get the bandwidth of specified interface and specified band
   *
-  * @attention 1. The 5G bandwidth can only be read when CONFIG_SOC_WIFI_HE_SUPPORT_5G is enabled.
+  * @attention 1. The 5G bandwidth can only be read when CONFIG_SOC_WIFI_SUPPORT_5G is enabled.
   * @attention 2. When the WiFi band mode is set to 2.4G only, it will not get 5G bandwidth
   * @attention 3. When the WiFi band mode is set to 5G only, it will not get 2.4G bandwidth
   *

components/esp_wifi/include/esp_wifi_types_generic.h

@@ -49,10 +49,16 @@ typedef enum {
 /** @brief Structure describing WiFi country-based regional restrictions. */
 typedef struct {
     char                  cc[3];   /**< country code string */
-    uint8_t               schan;   /**< start channel */
-    uint8_t               nchan;   /**< total channel number */
+    uint8_t               schan;   /**< start channel of the allowed 2.4GHz WiFi channels */
+    uint8_t               nchan;   /**< total channel number of the allowed 2.4GHz WiFi channels */
     int8_t                max_tx_power;   /**< This field is used for getting WiFi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
     wifi_country_policy_t policy;  /**< country policy */
+#if SOC_WIFI_SUPPORT_5G
+    uint32_t              wifi_5g_channel_mask;  /**< A bitmask representing the allowed 5GHz WiFi channels.
+                                                      Each bit in the mask corresponds to a specific channel as wifi_5g_channel_bit_t shown.
+                                                      Bitmask set to 0 indicates 5GHz channels are allowed according to local regulatory rules.
+                                                      Please note that configured bitmask takes effect only when policy is manual. */
+#endif
 } wifi_country_t;
 
 /* Strength of authmodes */
@@ -178,8 +184,8 @@ typedef struct {
 } wifi_scan_time_t;
 
 typedef struct {
-    uint16_t ghz_2_channels;     /**< Represents 2.4 GHz channels */
-    uint32_t ghz_5_channels;     /**< Represents 5 GHz channels */
+    uint16_t ghz_2_channels;     /**< Represents 2.4 GHz channels, that bits can be set as wifi_2g_channel_bit_t shown. */
+    uint32_t ghz_5_channels;     /**< Represents 5 GHz channels, that bits can be set as wifi_5g_channel_bit_t shown. */
 } wifi_scan_channel_bitmap_t;
 
 /** @brief Parameters for an SSID scan. */
@@ -191,7 +197,9 @@ typedef struct {
     wifi_scan_type_t scan_type;                        /**< scan type, active or passive */
     wifi_scan_time_t scan_time;                        /**< scan time per channel */
     uint8_t home_chan_dwell_time;                      /**< time spent at home channel between scanning consecutive channels. */
-    wifi_scan_channel_bitmap_t channel_bitmap;         /**< Channel bitmap for setting specific channels to be scanned. For 2.4ghz channels set ghz_2_channels from BIT(1) to BIT(14) from LSB to MSB order to indicate channels to be scanned. Currently scanning in 5ghz channels is not supported. Please note that the 'channel' parameter above needs to be set to 0 to allow scanning by bitmap. */
+    wifi_scan_channel_bitmap_t channel_bitmap;         /**< Channel bitmap for setting specific channels to be scanned.
+                                                            Please note that the 'channel' parameter above needs to be set to 0 to allow scanning by bitmap.
+                                                            Also, note that only allowed channels configured by wifi_country_t can be scaned. */
 } wifi_scan_config_t;
 
 /** @brief Parameters default scan configurations. */
@@ -305,6 +313,72 @@ typedef enum {
     WIFI_BAND_MODE_AUTO = 3,            /* WiFi band mode is 2.4G + 5G */
 } wifi_band_mode_t;
 
+#ifndef BIT
+#define BIT(nr)  (1 << (nr))
+#endif
+
+#define CHANNEL_TO_BIT_NUMBER(channel) ((channel >= 1 && channel <= 14) ? (channel) : \
+    ((channel >= 36 && channel <= 64 && (channel - 36) % 4 == 0) ? ((channel - 36) / 4 + 1) : \
+    ((channel >= 100 && channel <= 144 && (channel - 100) % 4 == 0) ? ((channel - 100) / 4 + 9) : \
+    ((channel >= 149 && channel <= 177 && (channel - 149) % 4 == 0) ? ((channel - 149) / 4 + 21) : 0))))
+
+#define BIT_NUMBER_TO_CHANNEL(bit_number, band) ((band == WIFI_BAND_2G) ? (bit_number) : \
+    ((bit_number >= 1 && bit_number <= 8) ? ((bit_number - 1) * 4 + 36) : \
+    ((bit_number >= 9 && bit_number <= 20) ? ((bit_number - 9) * 4 + 100) : \
+    ((bit_number >= 21 && bit_number <= 28) ? ((bit_number - 21) * 4 + 149) : 0))))
+
+#define CHANNEL_TO_BIT(channel) (BIT(CHANNEL_TO_BIT_NUMBER(channel)))
+
+/** Argument structure for 2.4G channels */
+typedef enum {
+    WIFI_CHANNEL_1 = BIT(1),   /**< wifi channel 1 */
+    WIFI_CHANNEL_2 = BIT(2),   /**< wifi channel 2 */
+    WIFI_CHANNEL_3 = BIT(3),   /**< wifi channel 3 */
+    WIFI_CHANNEL_4 = BIT(4),   /**< wifi channel 4 */
+    WIFI_CHANNEL_5 = BIT(5),   /**< wifi channel 5 */
+    WIFI_CHANNEL_6 = BIT(6),   /**< wifi channel 6 */
+    WIFI_CHANNEL_7 = BIT(7),   /**< wifi channel 7 */
+    WIFI_CHANNEL_8 = BIT(8),   /**< wifi channel 8 */
+    WIFI_CHANNEL_9 = BIT(9),   /**< wifi channel 9 */
+    WIFI_CHANNEL_10 = BIT(10), /**< wifi channel 10 */
+    WIFI_CHANNEL_11 = BIT(11), /**< wifi channel 11 */
+    WIFI_CHANNEL_12 = BIT(12), /**< wifi channel 12 */
+    WIFI_CHANNEL_13 = BIT(13), /**< wifi channel 13 */
+    WIFI_CHANNEL_14 = BIT(14), /**< wifi channel 14 */
+} wifi_2g_channel_bit_t;
+
+/** Argument structure for 5G channels */
+typedef enum {
+    WIFI_CHANNEL_36 = BIT(1),   /**< wifi channel 36 */
+    WIFI_CHANNEL_40 = BIT(2),   /**< wifi channel 40 */
+    WIFI_CHANNEL_44 = BIT(3),   /**< wifi channel 44 */
+    WIFI_CHANNEL_48 = BIT(4),   /**< wifi channel 48 */
+    WIFI_CHANNEL_52 = BIT(5),   /**< wifi channel 52 */
+    WIFI_CHANNEL_56 = BIT(6),   /**< wifi channel 56 */
+    WIFI_CHANNEL_60 = BIT(7),   /**< wifi channel 60 */
+    WIFI_CHANNEL_64 = BIT(8),   /**< wifi channel 64 */
+    WIFI_CHANNEL_100 = BIT(9),  /**< wifi channel 100 */
+    WIFI_CHANNEL_104 = BIT(10), /**< wifi channel 104 */
+    WIFI_CHANNEL_108 = BIT(11), /**< wifi channel 108 */
+    WIFI_CHANNEL_112 = BIT(12), /**< wifi channel 112 */
+    WIFI_CHANNEL_116 = BIT(13), /**< wifi channel 116 */
+    WIFI_CHANNEL_120 = BIT(14), /**< wifi channel 120 */
+    WIFI_CHANNEL_124 = BIT(15), /**< wifi channel 124 */
+    WIFI_CHANNEL_128 = BIT(16), /**< wifi channel 128 */
+    WIFI_CHANNEL_132 = BIT(17), /**< wifi channel 132 */
+    WIFI_CHANNEL_136 = BIT(18), /**< wifi channel 136 */
+    WIFI_CHANNEL_140 = BIT(19), /**< wifi channel 140 */
+    WIFI_CHANNEL_144 = BIT(20), /**< wifi channel 144 */
+    WIFI_CHANNEL_149 = BIT(21), /**< wifi channel 149 */
+    WIFI_CHANNEL_153 = BIT(22), /**< wifi channel 153 */
+    WIFI_CHANNEL_157 = BIT(23), /**< wifi channel 157 */
+    WIFI_CHANNEL_161 = BIT(24), /**< wifi channel 161 */
+    WIFI_CHANNEL_165 = BIT(25), /**< wifi channel 165 */
+    WIFI_CHANNEL_169 = BIT(26), /**< wifi channel 169 */
+    WIFI_CHANNEL_173 = BIT(27), /**< wifi channel 173 */
+    WIFI_CHANNEL_177 = BIT(28), /**< wifi channel 177 */
+} wifi_5g_channel_bit_t;
+
 #define WIFI_PROTOCOL_11B         0x1
 #define WIFI_PROTOCOL_11G         0x2
 #define WIFI_PROTOCOL_11N         0x4

components/esp_wifi/lib

@@ -1 +1 @@
-Subproject commit efa80057b04ade8b1412a0dedcb5572d6ccd1fcc
+Subproject commit ad8411567dc96a9d7fd13d275e6657c223287388

components/esptool_py/Kconfig.projbuild

@@ -4,7 +4,7 @@ menu "Serial flasher config"
     config ESPTOOLPY_NO_STUB
         bool "Disable download stub"
         default y if IDF_ENV_FPGA || IDF_ENV_BRINGUP
-        default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 # TODO: IDF-8631, IDF-9241 to be removed
+        default y if IDF_TARGET_ESP32C61 # TODO: IDF-9241 to be removed
         default n
 
         help

components/freertos/esp_additions/idf_additions.c

@@ -81,15 +81,44 @@ err:
 
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
 
+    static void prvTaskDeleteWithCaps( TaskHandle_t xTaskToDelete )
+    {
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
+        StaticTask_t * pxTaskBuffer;
+        StackType_t * puxStackBuffer;
+
+        /* The task to be deleted must not be running.
+         * So we suspend the task before deleting it. */
+        vTaskSuspend( xTaskToDelete );
+
+        /* Wait for the task to be suspended */
+        while( eRunning == eTaskGetState( xTaskToDelete ) )
+        {
+            taskYIELD();
+        }
+
+        configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
+
+        xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
+        configASSERT( xResult == pdTRUE );
+        configASSERT( puxStackBuffer != NULL );
+        configASSERT( pxTaskBuffer != NULL );
+
+        /* We can delete the task and free the memory buffers. */
+        vTaskDelete( xTaskToDelete );
+
+        /* Free the memory buffers */
+        heap_caps_free( puxStackBuffer );
+        vPortFree( pxTaskBuffer );
+    }
+
     static void prvTaskDeleteWithCapsTask( void * pvParameters )
     {
         TaskHandle_t xTaskToDelete = ( TaskHandle_t ) pvParameters;
 
-        /* The task to be deleted must not be running */
-        configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
-
         /* Delete the WithCaps task */
-        vTaskDeleteWithCaps( xTaskToDelete );
+        prvTaskDeleteWithCaps( xTaskToDelete );
 
         /* Delete the temporary clean up task */
         vTaskDelete( NULL );
@@ -98,7 +127,7 @@ err:
     void vTaskDeleteWithCaps( TaskHandle_t xTaskToDelete )
     {
         /* THIS FUNCTION SHOULD NOT BE CALLED FROM AN INTERRUPT CONTEXT. */
-        /*TODO: Update it to use portASSERT_IF_IN_ISR() instead. (IDF-10540) */
+        /* TODO: Update it to use portASSERT_IF_IN_ISR() instead. (IDF-10540) */
         vPortAssertIfInISR();
 
         TaskHandle_t xCurrentTaskHandle = xTaskGetCurrentTaskHandle();
@@ -151,60 +180,8 @@ err:
             }
         }
 
-        #if ( configNUM_CORES > 1 )
-            else if( eRunning == eTaskGetState( xTaskToDelete ) )
-            {
-                /* The WithCaps task is running on another core.
-                 * We suspend the task first and then delete it. */
-                vTaskSuspend( xTaskToDelete );
-
-                /* Wait for the task to be suspended */
-                while( eRunning == eTaskGetState( xTaskToDelete ) )
-                {
-                    portYIELD_WITHIN_API();
-                }
-
-                // Return value unused if asserts are disabled
-                BaseType_t __attribute__((unused)) xResult;
-                StaticTask_t * pxTaskBuffer;
-                StackType_t * puxStackBuffer;
-
-                xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
-                configASSERT( xResult == pdTRUE );
-                configASSERT( puxStackBuffer != NULL );
-                configASSERT( pxTaskBuffer != NULL );
-
-                /* Delete the task */
-                vTaskDelete( xTaskToDelete );
-
-                /* Free the memory buffers */
-                heap_caps_free( puxStackBuffer );
-                vPortFree( pxTaskBuffer );
-            }
-        #endif /* if ( configNUM_CORES > 1 ) */
-        else
-        {
-            /* The WithCaps task is not running and is being deleted
-             * from another task's context. */
-            configASSERT( eRunning != eTaskGetState( xTaskToDelete ) );
-
-            // Return value unused if asserts are disabled
-            BaseType_t __attribute__((unused)) xResult;
-            StaticTask_t * pxTaskBuffer;
-            StackType_t * puxStackBuffer;
-
-            xResult = xTaskGetStaticBuffers( xTaskToDelete, &puxStackBuffer, &pxTaskBuffer );
-            configASSERT( xResult == pdTRUE );
-            configASSERT( puxStackBuffer != NULL );
-            configASSERT( pxTaskBuffer != NULL );
-
-            /* We can delete the task and free the memory buffers. */
-            vTaskDelete( xTaskToDelete );
-
-            /* Free the memory buffers */
-            heap_caps_free( puxStackBuffer );
-            vPortFree( pxTaskBuffer );
-        } /* if( ( xTaskToDelete == NULL ) || ( xTaskToDelete == xCurrentTaskHandle ) ) */
+        /* Delete the WithCaps task */
+        prvTaskDeleteWithCaps( xTaskToDelete );
     }
 
 #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
@@ -262,8 +239,8 @@ err:
 
     void vQueueDeleteWithCaps( QueueHandle_t xQueue )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticQueue_t * pxQueueBuffer;
         uint8_t * pucQueueStorageBuffer;
 
@@ -335,8 +312,8 @@ err:
 
     void vSemaphoreDeleteWithCaps( SemaphoreHandle_t xSemaphore )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticSemaphore_t * pxSemaphoreBuffer;
 
         /* Retrieve the buffer used to create the semaphore before deleting it
@@ -408,8 +385,8 @@ err:
     void vStreamBufferGenericDeleteWithCaps( StreamBufferHandle_t xStreamBuffer,
                                              BaseType_t xIsMessageBuffer )
     {
-        // Return value unused if asserts are disabled
-        BaseType_t __attribute__((unused)) xResult;
+        /* Return value unused if asserts are disabled */
+        BaseType_t __attribute__( ( unused ) ) xResult;
         StaticStreamBuffer_t * pxStaticStreamBuffer;
         uint8_t * pucStreamBufferStorageArea;
 

components/freertos/test_apps/freertos/misc/test_idf_additions.c

@@ -89,6 +89,34 @@ TEST_CASE("IDF additions: Task creation with memory caps and self deletion", "[f
     xTaskNotifyGive(task_handle);
 }
 
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+
+TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletion stress test", "[freertos]")
+{
+#define TEST_NUM_TASKS      5
+#define TEST_NUM_ITERATIONS 1000
+    TaskHandle_t task_handle[TEST_NUM_TASKS];
+    StackType_t *puxStackBuffer;
+    StaticTask_t *pxTaskBuffer;
+
+    for (int j = 0; j < TEST_NUM_ITERATIONS; j++) {
+        for (int i = 0; i < TEST_NUM_TASKS; i++) {
+            // Create a task with caps
+            TEST_ASSERT_EQUAL(pdPASS, xTaskCreateWithCaps(task_with_caps_self_delete, "task", 4096, NULL, UNITY_FREERTOS_PRIORITY, &task_handle[i], MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT));
+            TEST_ASSERT_NOT_EQUAL(NULL, task_handle);
+            // Get the task's memory
+            TEST_ASSERT_EQUAL(pdTRUE, xTaskGetStaticBuffers(task_handle[i], &puxStackBuffer, &pxTaskBuffer));
+        }
+
+        for (int i = 0; i < TEST_NUM_TASKS; i++) {
+            // Notify the task to delete itself
+            xTaskNotifyGive(task_handle[i]);
+        }
+    }
+}
+
+#endif /* CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
+
 #if ( CONFIG_FREERTOS_NUMBER_OF_CORES > 1 )
 
 static void task_with_caps_running_on_other_core(void *arg)

components/freertos/test_apps/freertos/sdkconfig.ci.psram

@@ -5,6 +5,7 @@ CONFIG_IDF_TARGET="esp32"
 # Enable SPIRAM
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_OCCUPY_NO_HOST=y
+CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
 
 # Disable encrypted flash reads/writes to save IRAM in this build configuration
 CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=n

components/hal/esp32c61/include/hal/apm_ll.h

@@ -0,0 +1,407 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/pcr_reg.h"
+#include "soc/tee_reg.h"
+#include "soc/hp_apm_reg.h"
+#include "soc/lp_apm_reg.h"
+#include "soc/interrupts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APM_LL_CTRL_EXCEPTION_ID        0x0000001FU
+#define APM_LL_CTRL_EXCEPTION_ID_S      18
+#define APM_LL_CTRL_EXCEPTION_ID_V      0x0000001FU
+#define APM_LL_CTRL_EXCEPTION_MODE      0x00000003U
+#define APM_LL_CTRL_EXCEPTION_MODE_S    16
+#define APM_LL_CTRL_EXCEPTION_MODE_V    0x00000003U
+#define APM_LL_CTRL_EXCEPTION_REGION    0x0000FFFFU
+#define APM_LL_CTRL_EXCEPTION_REGION_S  0
+#define APM_LL_CTRL_EXCEPTION_REGION_V  0x0000FFFFU
+
+#define APM_LL_HP_MAX_REGION_NUM 15
+#define APM_LL_LP_MAX_REGION_NUM 3
+#define APM_LL_MASTER_MAX        32
+
+#define  HP_APM_MAX_ACCESS_PATH  0x4
+#define  LP_APM_MAX_ACCESS_PATH  0x1
+
+#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : \
+                                    (HP_APM_REGION_FILTER_EN_REG);  \
+    })
+
+#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
+
+#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : \
+                                    (HP_APM_REGION0_ATTR_REG + 0xC * (regn_num));  \
+    })
+
+#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) :  \
+                                    (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_CTRL_M_REGION_STATUS_CLR    (BIT(0))
+#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \
+                                    (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path));  \
+    })
+
+#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
+#define APM_LL_SEC_MODE_REGION_ATTR_V  0x00000003U
+#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
+
+#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) :  \
+                                    (HP_APM_INT_EN_REG);  \
+    })
+
+#define APM_CTRL_CLK_EN    (BIT(0))
+#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : \
+                                    (HP_APM_CLOCK_GATE_REG);  \
+    })
+
+#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \
+    ({\
+        (LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : \
+                                    (HP_APM_FUNC_CTRL_REG);  \
+    })
+
+/**
+ * @brief APM Master ID
+ */
+typedef enum {
+    APM_LL_MASTER_HPCORE       = 0,
+    APM_LL_MASTER_LPCORE       = 1,
+    APM_LL_MASTER_REGDMA       = 2,
+    APM_LL_MASTER_SDIOSLV      = 3,
+    APM_LL_MASTER_MODEM        = 4,
+    APM_LL_MASTER_MEM_MONITOR  = 5,
+    APM_LL_MASTER_TRACE        = 6,
+    APM_LL_MASTER_GDMA         = 16, // The beginning of GDMA master ID
+    APM_LL_MASTER_GDMA_SPI2    = 16,
+    APM_LL_MASTER_GDMA_UHCI0   = 18,
+    APM_LL_MASTER_GDMA_I2S0    = 19,
+    APM_LL_MASTER_GDMA_AES     = 22,
+    APM_LL_MASTER_GDMA_SHA     = 23,
+    APM_LL_MASTER_GDMA_ADC     = 24,
+    APM_LL_MASTER_GDMA_PARLIO  = 25,
+} apm_ll_master_id_t;
+
+/**
+ * @brief APM Controller
+ */
+typedef enum {
+    LP_APM_CTRL = 0,
+    HP_APM_CTRL  = 1,
+} apm_ll_apm_ctrl_t;
+
+/**
+ * @brief APM Secure Mode
+ */
+typedef enum {
+    APM_LL_SECURE_MODE_TEE  = 0, /* Trusted execution environment mode */
+    APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */
+    APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */
+    APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */
+} apm_ll_secure_mode_t;
+
+/**
+ * @brief APM Ctrl access path
+ */
+typedef enum {
+    APM_CTRL_ACCESS_PATH_M0 = 0x0,
+    APM_CTRL_ACCESS_PATH_M1 = 0x1,
+    APM_CTRL_ACCESS_PATH_M2 = 0x2,
+    APM_CTRL_ACCESS_PATH_M3 = 0x3,
+} apm_ll_ctrl_access_path_t;
+
+/**
+ * @brief APM Ctrl path.
+ */
+typedef struct {
+    apm_ll_apm_ctrl_t apm_ctrl;           /* APM Ctrl: LP APM/HP APM. */
+    apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */
+} apm_ctrl_path_t;
+
+/**
+ * @brief APM exception information
+ */
+typedef struct {
+    apm_ctrl_path_t apm_path;
+    uint8_t  excp_regn;
+    uint8_t  excp_mode;
+    uint8_t  excp_id;
+    uint8_t  excp_type;
+    uint32_t excp_addr;
+} apm_ctrl_exception_info_t;
+
+/**
+ * @brief Set secure mode
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param master_id APM master ID
+ * @param sec_mode Secure mode
+ */
+static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id,
+                                                     apm_ll_secure_mode_t sec_mode)
+{
+    if (apm_ctrl == HP_APM_CTRL) {
+        REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
+    }
+}
+
+/**
+ * @brief TEE controller clock auto gating enable
+ *
+ * @param enable Flag for HP clock auto gating enable/disable
+ */
+static inline void apm_tee_ll_clk_gating_enable(bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
+    } else {
+        REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
+    }
+}
+
+/**
+ * @brief enable/disable APM Ctrl Region access permission filter
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Memory Region number
+ * @param enable Flag for Region access filter enable/disable
+ */
+static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                        uint32_t regn_num, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
+    } else {
+        REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num));
+    }
+}
+
+/**
+ * @brief enable/disable APM Ctrl access path(M[0:n])
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access path
+ * @param enable     Flag for APM Ctrl M path filter enable/disable
+ */
+static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                 apm_ll_ctrl_access_path_t apm_m_path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path));
+    }
+}
+
+/**
+ * @brief APM Ctrl Region start address configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param addr     Region start address
+ */
+static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl,
+                                                            uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr);
+}
+
+/**
+ * @brief APM Ctrl Region end address configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param addr     Region end address
+ */
+static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl,
+                                                          uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr);
+}
+
+/**
+ * @brief HP Region pms attributes configuration
+ *
+ * @param apm_ctrl APM Ctrl (LP_APM/HP_APM)
+ * @param regn_num Region number to be configured
+ * @param sec_mode Secure mode of the Master
+ * @param regn_pms XWR permissions for the given secure mode and Region number
+ */
+static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl,
+                                                               uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
+{
+    uint32_t val = 0;
+    val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num));
+    val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode);
+    val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
+    REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val);
+}
+
+/**
+ * @brief Get APM Ctrl access path(M[0:n]) exception status
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access path
+ */
+static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl,
+                                                       apm_ll_ctrl_access_path_t apm_m_path)
+{
+    return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path));
+}
+
+/**
+ * @brief Clear APM Ctrl access path(M[0:n]) exception
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param amp_m_path APM Ctrl access path
+ */
+static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl,
+                                                   apm_ll_ctrl_access_path_t apm_m_path)
+{
+    REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path),
+                APM_CTRL_M_REGION_STATUS_CLR);
+}
+
+/**
+ * @brief Get APM Ctrl access path(M[0:n]) exception information
+ *
+ * @param excp_info  Exception related information like addr,
+ * region, apm_ctrl, apm_m_path, sec_mode and master id
+ */
+static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info)
+{
+    excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                       APM_LL_CTRL_EXCEPTION_ID);
+    excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                         APM_LL_CTRL_EXCEPTION_MODE);
+    excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path),
+                                         APM_LL_CTRL_EXCEPTION_REGION);
+    excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path);
+    excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path));
+}
+
+/**
+ * @brief Interrupt enable for APM Ctrl at access path(M[0:n])
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM/HP_APM)
+ * @param apm_m_path APM Ctrl access patch(M[0:n])
+ * @param enable     Flag for access path interrupt enable/disable
+ */
+static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl,
+                                                    apm_ll_ctrl_access_path_t apm_m_path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path));
+    }
+}
+
+/**
+ * @brief APM Ctrl clock auto gating enable
+ *
+ * @param apm_ctrl  APM Ctrl (LP_APM/HP_APM)
+ * @param enable    Flag for HP clock auto gating enable/disable
+ */
+static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
+    } else {
+        REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN);
+    }
+}
+
+/**
+ * @brief APM/TEE/HP System Reg reset event bypass enable
+ *
+ * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
+ * but also some reset events.
+ * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
+ * Some reset events will be bypassed.
+ *
+ * @param enable   Flag for event bypass enable/disable
+ */
+static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
+    } else {
+        REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
+    }
+}
+
+/**
+ * @brief Fetch the APM Ctrl interrupt source number.
+ *
+ * @param apm_ctrl   APM Ctrl (LP_APM0/HP_APM/LP_APM)
+ * @param apm_m_path APM Ctrl access patch(M[0:n])
+ */
+static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path)
+{
+    switch (apm_ctrl) {
+        case HP_APM_CTRL :
+            return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path);
+        case LP_APM_CTRL :
+            return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path);
+    }
+
+    return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c61/include/hal/sha_ll.h

@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include "soc/hwcrypto_reg.h"
+#include "soc/pcr_struct.h"
+#include "hal/sha_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Enable the bus clock for SHA peripheral module
+ *
+ * @param enable true to enable the module, false to disable the module
+ */
+static inline void sha_ll_enable_bus_clock(bool enable)
+{
+    PCR.sha_conf.sha_clk_en = enable;
+}
+
+/**
+ * @brief Reset the SHA peripheral module
+ */
+static inline void sha_ll_reset_register(void)
+{
+    PCR.sha_conf.sha_rst_en = 1;
+    PCR.sha_conf.sha_rst_en = 0;
+
+    // Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset
+    PCR.ds_conf.ds_rst_en = 0;
+    PCR.hmac_conf.hmac_rst_en = 0;
+    PCR.ecdsa_conf.ecdsa_rst_en = 0;
+}
+
+/**
+ * @brief Start a new SHA block conversions (no initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_start_block(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_START_REG, 1);
+}
+
+/**
+ * @brief Continue a SHA block conversion (initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_continue_block(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_CONTINUE_REG, 1);
+}
+
+/**
+ * @brief Start a new SHA message conversion using DMA (no initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_start_dma(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_DMA_START_REG, 1);
+}
+
+/**
+ * @brief Continue a SHA message conversion using DMA (initial hash in HW)
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_continue_dma(esp_sha_type sha_type)
+{
+    REG_WRITE(SHA_MODE_REG, sha_type);
+    REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
+}
+
+/**
+ * @brief Load the current hash digest to digest register
+ *
+ * @note Happens automatically on ESP32C6
+ *
+ * @param sha_type The SHA algorithm type
+ */
+static inline void sha_ll_load(esp_sha_type sha_type)
+{
+}
+
+/**
+ * @brief Sets the number of message blocks to be hashed
+ *
+ * @note DMA operation only
+ *
+ * @param num_blocks Number of message blocks to process
+ */
+static inline void sha_ll_set_block_num(size_t num_blocks)
+{
+    REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks);
+}
+
+/**
+ * @brief Checks if the SHA engine is currently busy hashing a block
+ *
+ * @return true SHA engine busy
+ * @return false SHA engine idle
+ */
+static inline bool sha_ll_busy(void)
+{
+    return REG_READ(SHA_BUSY_REG);
+}
+
+/**
+ * @brief Write a text (message) block to the SHA engine
+ *
+ * @param input_text Input buffer to be written to the SHA engine
+ * @param block_word_len Number of words in block
+ */
+static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
+{
+    uint32_t *data_words = (uint32_t *)input_text;
+    uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM);
+
+    for (int i = 0; i < block_word_len; i++) {
+        REG_WRITE(&reg_addr_buf[i], data_words[i]);
+    }
+}
+
+/**
+ * @brief Read the message digest from the SHA engine
+ *
+ * @param sha_type The SHA algorithm type
+ * @param digest_state Buffer that message digest will be written to
+ * @param digest_word_len Length of the message digest
+ */
+static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
+{
+    uint32_t *digest_state_words = (uint32_t *)digest_state;
+    const size_t REG_WIDTH = sizeof(uint32_t);
+
+    for (size_t i = 0; i < digest_word_len; i++) {
+        digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH));
+    }
+
+}
+
+/**
+ * @brief Write the message digest to the SHA engine
+ *
+ * @param sha_type The SHA algorithm type
+ * @param digest_state Message digest to be written to SHA engine
+ * @param digest_word_len Length of the message digest
+ */
+static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
+{
+    uint32_t *digest_state_words = (uint32_t *)digest_state;
+    uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM);
+
+    for (int i = 0; i < digest_word_len; i++) {
+        REG_WRITE(&reg_addr_buf[i], digest_state_words[i]);
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c61/modem_clock_hal.c

@@ -59,7 +59,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte
     }
 }
 
-uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
+uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
 {
     HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
     uint32_t bitmap = 0;

components/hal/test_apps/crypto/main/sha/test_sha.c

@@ -205,7 +205,7 @@ TEST_GROUP(sha);
 TEST_SETUP(sha)
 {
     test_utils_record_free_mem();
-    TEST_ESP_OK(test_utils_set_leak_level(0, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL));
+    TEST_ESP_OK(test_utils_set_leak_level(400, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL));
 }
 
 TEST_TEAR_DOWN(sha)

components/heap/CMakeLists.txt

@@ -7,16 +7,24 @@ if(${target} STREQUAL "linux")
     return()
 endif()
 
-set(srcs
-    "heap_caps_base.c"
-    "heap_caps.c"
-    "heap_caps_init.c"
-    "multi_heap.c")
+set(srcs "heap_caps_base.c"
+         "heap_caps.c"
+         "heap_caps_init.c"
+         "multi_heap.c")
 
-set(includes "include")
+# the root dir of TLSF submodule contains headers with static inline
+# functions used in the esp_rom component for TLSF patches. Therefore,
+# the tlsf/ dir must be included in the list of public includes.
+set(includes "include"
+             "tlsf")
+
+# The TLSF "public" includes should only be used
+# inside the heap component and are therefore added
+# to the list of the private includes from the heap
+# component perspective
+set(priv_includes "tlsf/include")
 
 if(NOT CONFIG_HEAP_TLSF_USE_ROM_IMPL)
-    set(priv_includes "tlsf")
     list(APPEND srcs "tlsf/tlsf.c")
 endif()
 

components/heap/linker.lf

@@ -5,9 +5,6 @@ entries:
         if HEAP_TLSF_USE_ROM_IMPL = n:
             tlsf:tlsf_block_size (noflash)
             tlsf:tlsf_size (noflash)
-            tlsf:tlsf_align_size (noflash)
-            tlsf:tlsf_block_size_min (noflash)
-            tlsf:tlsf_block_size_max (noflash)
             tlsf:tlsf_alloc_overhead (noflash)
             tlsf:tlsf_get_pool (noflash)
             tlsf:tlsf_malloc (noflash)

components/heap/multi_heap.c

@@ -15,10 +15,8 @@
 #include "multi_heap.h"
 #include "multi_heap_internal.h"
 
-#if !CONFIG_HEAP_TLSF_USE_ROM_IMPL
 #include "tlsf.h"
 #include "tlsf_block_functions.h"
-#endif
 
 /* Note: Keep platform-specific parts in this header, this source
    file should depend on libc only */
@@ -110,7 +108,7 @@ void multi_heap_in_rom_init(void)
 #else // CONFIG_HEAP_TLSF_USE_ROM_IMPL
 
 /* Check a block is valid for this heap. Used to verify parameters. */
-__attribute__((noinline)) NOCLONE_ATTR static void assert_valid_block(const heap_t *heap, const block_header_t *block)
+__attribute__((noinline)) NOCLONE_ATTR static void assert_valid_block(const heap_t *heap, const multi_heap_block_handle_t block)
 {
     pool_t pool = tlsf_get_pool(heap->heap_data);
     void *ptr = block_to_ptr(block);
@@ -175,22 +173,22 @@ multi_heap_block_handle_t multi_heap_get_first_block(multi_heap_handle_t heap)
 {
     assert(heap != NULL);
     pool_t pool = tlsf_get_pool(heap->heap_data);
-    block_header_t* block = offset_to_block(pool, -(int)block_header_overhead);
+    multi_heap_block_handle_t block = offset_to_block(pool, -(int)block_header_overhead);
 
-    return (multi_heap_block_handle_t)block;
+    return block;
 }
 
 multi_heap_block_handle_t multi_heap_get_next_block(multi_heap_handle_t heap, multi_heap_block_handle_t block)
 {
     assert(heap != NULL);
     assert_valid_block(heap, block);
-    block_header_t* next = block_next(block);
+    multi_heap_block_handle_t next = block_next(block);
 
     if(block_size(next) == 0) {
         //Last block:
         return NULL;
     } else {
-        return (multi_heap_block_handle_t)next;
+        return next;
     }
 
 }

components/heap/port/esp32c61/memory_layout.c

@@ -12,6 +12,11 @@
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
 
+/* Memory layout for ESP32C61 SoC
+ * Note that the external memory is not represented in this file since
+ * it is handled by the esp_psram component
+ */
+
 /**
  * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
  * Each type of memory map consists of one or more regions in the address space.
@@ -27,16 +32,14 @@
 
 /* Index of memory in `soc_memory_types[]` */
 enum {
-    SOC_MEMORY_TYPE_RAM     = 0,
-    SOC_MEMORY_TYPE_RTCRAM  = 1,
-    SOC_MEMORY_TYPE_NUM,
+    SOC_MEMORY_TYPE_RAM,
 };
 
 /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
-#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
+#define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
 #else
-#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
+#define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
 #endif
 
 /**
@@ -45,10 +48,9 @@ enum {
  * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
  * in turn to continue matching.
  */
-const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
+const soc_memory_type_desc_t soc_memory_types[] = {
     /*                           Mem Type Name   High Priority Matching                      Medium Priority Matching    Low Priority Matching */
-    [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
-    [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM",       { MALLOC_CAP_RTCRAM,                        ESP32C6_MEM_COMMON_CAPS,   0 }},
+    [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C61_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
 };
 
 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@@ -64,19 +66,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 /**
  * Register the shared buffer area of the last memory block into the heap during heap initialization
  */
-#define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
+#define APP_USABLE_DIRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
 const soc_memory_region_t soc_memory_regions[] = {
-    { 0x40800000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40800000,             false}, //D/IRAM level0, can be used as trace memory
-    { 0x40820000,           0x20000,                                   SOC_MEMORY_TYPE_RAM, 0x40820000,             false}, //D/IRAM level1, can be used as trace memory
-    { 0x40840000,           (APP_USABLE_DRAM_END-0x40840000),          SOC_MEMORY_TYPE_RAM, 0x40840000,             false}, //D/IRAM level2, can be used as trace memory
-    { APP_USABLE_DRAM_END,  (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END,    true},  //D/IRAM level3, can be used as trace memory (ROM reserved area)
+    { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW),  SOC_MEMORY_TYPE_RAM,     SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
+    { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM,     APP_USABLE_DIRAM_END,    true}, //D/IRAM, can be used as trace memory (ROM reserved area)
 };
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
 
 
-extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+extern int _data_start, _heap_start, _iram_start, _iram_end;
 
 /**
  * Reserved memory regions.

components/heap/test_apps/.build-test-rules.yml

@@ -3,9 +3,6 @@
 components/heap/test_apps/heap_tests:
   disable:
     - if: IDF_TARGET == "linux"
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: not support yet  # TODO: [esp32c61] IDF-9858
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
     - if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1
     # These 3 configs are build only for non-nightly, buildig for a single target is sufficient

components/heap/test_apps/heap_tests/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/heap/test_apps/heap_tests/main/test_malloc.c

@@ -176,7 +176,7 @@ TEST_CASE("test get allocated size", "[heap]")
         const size_t aligned_size = (alloc_sizes[i] + 3) & ~3;
         const size_t real_size = heap_caps_get_allocated_size(ptr_array[i]);
         printf("initial size: %d, requested size : %d, allocated size: %d\n", alloc_sizes[i], aligned_size, real_size);
-        TEST_ASSERT_EQUAL(aligned_size, real_size);
+        TEST_ASSERT(aligned_size <= real_size);
 
         heap_caps_free(ptr_array[i]);
     }

components/heap/test_apps/heap_tests/pytest_heap.py

@@ -6,7 +6,6 @@ from pytest_embedded import Dut
 
 @pytest.mark.generic
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD')  # TODO [ESP32C61] IDF-9858 IDF-10989
 @pytest.mark.nightly_run
 @pytest.mark.parametrize(
     'config',
@@ -40,7 +39,6 @@ def test_heap_poisoning_qemu(dut: Dut) -> None:
 
 @pytest.mark.generic
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD')  # TODO [ESP32C61] IDF-9858 IDF-10989
 @pytest.mark.parametrize(
     'config',
     [
@@ -52,9 +50,14 @@ def test_heap_in_flash(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
-@pytest.mark.esp32s2
-@pytest.mark.esp32s3
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+        'esp32s2',
+        'esp32s3',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [
@@ -67,7 +70,12 @@ def test_heap(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [
@@ -86,7 +94,12 @@ def test_heap_misc_options(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32
+@pytest.mark.parametrize(
+    'target',
+    [
+        'esp32',
+    ]
+)
 @pytest.mark.parametrize(
     'config',
     [

components/heap/test_multi_heap_host/Makefile

@@ -13,7 +13,7 @@ SOURCE_FILES = $(abspath \
 	main.cpp \
 	)
 
-INCLUDE_FLAGS = -I../include -I../../../tools/catch -I../tlsf
+INCLUDE_FLAGS = -I../include -I../../../tools/catch -I../tlsf -I../tlsf/include
 
 GCOV ?= gcov
 

components/heap/test_multi_heap_host/test_multi_heap.cpp

@@ -8,9 +8,9 @@
 #include "multi_heap.h"
 
 #include "../multi_heap_config.h"
-#include "../tlsf/tlsf.h"
-#include "../tlsf/tlsf_common.h"
+#include "../tlsf/include/tlsf.h"
 #include "../tlsf/tlsf_block_functions.h"
+#include "../tlsf/tlsf_control_functions.h"
 
 #include <string.h>
 #include <assert.h>
@@ -19,7 +19,7 @@
  * malloc and free and allocate memory from the host heap. Since the test
  * `TEST_CASE("multi_heap many random allocations", "[multi_heap]")`
  * calls multi_heap_allocation_impl() with sizes that can go up to 8MB,
- * an allocatation on the heap will be prefered rather than the stack which
+ * an allocatation on the heap will be preferred rather than the stack which
  * might not have the necessary memory.
  */
 static void *__malloc__(size_t bytes)
@@ -62,7 +62,7 @@ TEST_CASE("multi_heap simple allocations", "[multi_heap]")
     REQUIRE( (intptr_t)buf < (intptr_t)(small_heap + sizeof(small_heap)));
 
     REQUIRE( multi_heap_get_allocated_size(heap, buf) >= test_alloc_size );
-    REQUIRE( multi_heap_get_allocated_size(heap, buf) < test_alloc_size + 16);
+    printf("test alloc size %d\n", test_alloc_size);
 
     memset(buf, 0xEE, test_alloc_size);
 
@@ -482,7 +482,7 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
 {
     uint8_t test_heap[4 * 1024];
     multi_heap_handle_t heap = multi_heap_register(test_heap, sizeof(test_heap));
-    uint32_t aligments = 0; // starts from alignment by 4-byte boundary
+    uint32_t alignments = 0; // starts from alignment by 4-byte boundary
     size_t old_size = multi_heap_free_size(heap);
     size_t leakage = 1024;
     printf("[ALIGNED_ALLOC] heap_size before: %d \n", old_size);
@@ -491,26 +491,26 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
     multi_heap_dump(heap);
     printf("*********************\n");
 
-    for(;aligments <= 256; aligments++) {
+    for(;alignments <= 256; alignments++) {
 
         //Use some stupid size value to test correct alignment even in strange
         //memory layout objects:
-        uint8_t *buf = (uint8_t *)multi_heap_aligned_alloc(heap, (aligments + 137), aligments );
-        if(((aligments & (aligments - 1)) != 0) || (!aligments)) {
+        uint8_t *buf = (uint8_t *)multi_heap_aligned_alloc(heap, (alignments + 137), alignments );
+        if(((alignments & (alignments - 1)) != 0) || (!alignments)) {
             REQUIRE( buf == NULL );
         } else {
             REQUIRE( buf != NULL );
             REQUIRE((intptr_t)buf >= (intptr_t)test_heap);
             REQUIRE((intptr_t)buf < (intptr_t)(test_heap + sizeof(test_heap)));
 
-            printf("[ALIGNED_ALLOC] alignment required: %u \n", aligments);
+            printf("[ALIGNED_ALLOC] alignment required: %u \n", alignments);
             printf("[ALIGNED_ALLOC] address of allocated memory: %p \n\n", (void *)buf);
             //Address of obtained block must be aligned with selected value
-            REQUIRE(((intptr_t)buf & (aligments - 1)) == 0);
+            REQUIRE(((intptr_t)buf & (alignments - 1)) == 0);
 
             //Write some data, if it corrupts memory probably the heap
             //canary verification will fail:
-            memset(buf, 0xA5, (aligments + 137));
+            memset(buf, 0xA5, (alignments + 137));
 
             multi_heap_free(heap, buf);
         }
@@ -519,7 +519,7 @@ TEST_CASE("multi_heap aligned allocations", "[multi_heap]")
     /* Check that TLSF doesn't allocate a memory space smaller than required.
      * In any case, TLSF will write data in the previous block than the one
      * allocated. Thus, we should try to get/allocate this previous block. If
-     * the poisoned filled pattern has beeen overwritten by TLSF, then this
+     * the poisoned filled pattern has been overwritten by TLSF, then this
      * previous block will trigger an exception.
      * More info on this bug in !16296. */
     const size_t size = 50; /* TLSF will round the size up */

components/heap/tlsf

@@ -1 +1 @@
-Subproject commit 8fc595fe223cd0b3b5d7b29eb86825e4bd38e6e8
+Subproject commit ba64d198a845df70b481e2c55004521ca643dea6

components/mbedtls/CMakeLists.txt

@@ -292,6 +292,9 @@ if(CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN OR CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY)
 
     if(CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY)
         target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_verify")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_verify_restartable")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_read_signature")
+        target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=mbedtls_ecdsa_read_signature_restartable")
     endif()
 endif()
 

components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c

@@ -92,8 +92,12 @@ static esp_err_t crypto_shared_gdma_init(void)
     transfer_cfg.max_data_burst_size = 0;
     gdma_config_transfer(rx_channel, &transfer_cfg);
 
+#ifdef SOC_AES_SUPPORTED
     gdma_connect(rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
     gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
+#elif SOC_SHA_SUPPORTED
+    gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
+#endif
 
     return ESP_OK;
 
@@ -123,11 +127,17 @@ esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *ou
     /* Tx channel is shared between AES and SHA, need to connect to peripheral every time */
     gdma_disconnect(tx_channel);
 
+#ifdef SOC_SHA_SUPPORTED
     if (peripheral == GDMA_TRIG_PERIPH_SHA) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
-    } else if (peripheral == GDMA_TRIG_PERIPH_AES) {
+    } else
+#endif // SOC_SHA_SUPPORTED
+#ifdef SOC_AES_SUPPORTED
+    if (peripheral == GDMA_TRIG_PERIPH_AES) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
-    } else {
+    } else
+#endif // SOC_AES_SUPPORTED
+    {
         return ESP_ERR_INVALID_ARG;
     }
 
@@ -176,11 +186,17 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
     /* Tx channel is shared between AES and SHA, need to connect to peripheral every time */
     gdma_disconnect(tx_channel);
 
+#ifdef SOC_SHA_SUPPORTED
     if (peripheral == GDMA_TRIG_PERIPH_SHA) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA, 0));
-    } else if (peripheral == GDMA_TRIG_PERIPH_AES) {
+    } else
+#endif // SOC_SHA_SUPPORTED
+#ifdef SOC_AES_SUPPORTED
+    if (peripheral == GDMA_TRIG_PERIPH_AES) {
         gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
-    } else {
+    } else
+#endif // SOC_AES_SUPPORTED
+    {
         return ESP_ERR_INVALID_ARG;
     }
 

components/mbedtls/port/ecdsa/ecdsa_alt.c

@@ -15,6 +15,7 @@
 #include "esp_private/esp_crypto_lock_internal.h"
 #include "mbedtls/error.h"
 #include "mbedtls/ecdsa.h"
+#include "mbedtls/asn1.h"
 #include "mbedtls/asn1write.h"
 #include "mbedtls/platform_util.h"
 #include "ecdsa/ecdsa_alt.h"
@@ -653,6 +654,37 @@ static int esp_ecdsa_verify(mbedtls_ecp_group *grp,
     return ret;
 }
 
+/*
+ * Verify ECDSA signature of hashed message
+ */
+extern int __real_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp,
+                         const unsigned char *buf, size_t blen,
+                         const mbedtls_ecp_point *Q,
+                         const mbedtls_mpi *r,
+                         const mbedtls_mpi *s,
+                         mbedtls_ecdsa_restart_ctx *rs_ctx)
+{
+    if ((grp->id == MBEDTLS_ECP_DP_SECP192R1 || grp->id == MBEDTLS_ECP_DP_SECP256R1) && blen == ECDSA_SHA_LEN) {
+        return esp_ecdsa_verify(grp, buf, blen, Q, r, s);
+    } else {
+        return __real_mbedtls_ecdsa_verify_restartable(grp, buf, blen, Q, r, s, rs_ctx);
+    }
+}
+
 /*
  * Verify ECDSA signature of hashed message
  */
@@ -674,10 +706,84 @@ int __wrap_mbedtls_ecdsa_verify(mbedtls_ecp_group *grp,
                          const mbedtls_mpi *r,
                          const mbedtls_mpi *s)
 {
-    if (grp->id == MBEDTLS_ECP_DP_SECP192R1 || grp->id == MBEDTLS_ECP_DP_SECP256R1) {
-        return esp_ecdsa_verify(grp, buf, blen, Q, r, s);
-    } else {
-        return __real_mbedtls_ecdsa_verify(grp, buf, blen, Q, r, s);
+    return __wrap_mbedtls_ecdsa_verify_restartable(grp, buf, blen, Q, r, s, NULL);
+}
+
+
+int __real_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx);
+
+int __wrap_mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx,
+                                             const unsigned char *hash, size_t hlen,
+                                             const unsigned char *sig, size_t slen,
+                                             mbedtls_ecdsa_restart_ctx *rs_ctx)
+{
+    int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED;
+    unsigned char *p = (unsigned char *) sig;
+    const unsigned char *end = sig + slen;
+    size_t len;
+    mbedtls_mpi r, s;
+    mbedtls_mpi_init(&r);
+    mbedtls_mpi_init(&s);
+
+    if ((ret = mbedtls_asn1_get_tag(&p, end, &len,
+                                    MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE)) != 0) {
+        ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
+        goto cleanup;
     }
+
+    if (p + len != end) {
+        ret = MBEDTLS_ERROR_ADD(MBEDTLS_ERR_ECP_BAD_INPUT_DATA,
+                                MBEDTLS_ERR_ASN1_LENGTH_MISMATCH);
+        goto cleanup;
+    }
+
+    if ((ret = mbedtls_asn1_get_mpi(&p, end, &r)) != 0 ||
+        (ret = mbedtls_asn1_get_mpi(&p, end, &s)) != 0) {
+        ret += MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
+        goto cleanup;
+    }
+
+    if ((ret = __wrap_mbedtls_ecdsa_verify_restartable(&ctx->MBEDTLS_PRIVATE(grp), hash, hlen,
+                                                    &ctx->MBEDTLS_PRIVATE(Q), &r, &s, NULL)) != 0) {
+        goto cleanup;
+    }
+
+    /* At this point we know that the buffer starts with a valid signature.
+     * Return 0 if the buffer just contains the signature, and a specific
+     * error code if the valid signature is followed by more data. */
+    if (p != end) {
+        ret = MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH;
+    }
+
+cleanup:
+    mbedtls_mpi_free(&r);
+    mbedtls_mpi_free(&s);
+
+    return ret;
+}
+
+
+int __real_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen);
+
+int __wrap_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen);
+
+int __wrap_mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx,
+                                    const unsigned char *hash, size_t hlen,
+                                    const unsigned char *sig, size_t slen)
+{
+    return __wrap_mbedtls_ecdsa_read_signature_restartable(
+            ctx, hash, hlen, sig, slen, NULL);
 }
 #endif /* CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY */

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1239,6 +1239,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
     int
     default 12
 
+config SOC_PM_SUPPORT_WIFI_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_BEACON_WAKEUP
+    bool
+    default y
+
 config SOC_PM_SUPPORT_BT_WAKEUP
     bool
     default y
@@ -1283,10 +1291,18 @@ config SOC_PM_SUPPORT_HP_AON_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_MAC_BB_PD
+    bool
+    default y
+
 config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_PMU_MODEM_STATE
+    bool
+    default y
+
 config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     bool
     default y
@@ -1315,6 +1331,10 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
     bool
     default y
 
+config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
+    int
+    default 4
+
 config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
@@ -1387,7 +1407,7 @@ config SOC_WIFI_HE_SUPPORT
     bool
     default y
 
-config SOC_WIFI_HE_SUPPORT_5G
+config SOC_WIFI_SUPPORT_5G
     bool
     default y
 

components/soc/esp32c5/include/soc/retention_periph_defs.h

@@ -43,6 +43,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
     SLEEP_RETENTION_MODULE_BT_BB        = 29,
     SLEEP_RETENTION_MODULE_802154_MAC   = 30,
+    SLEEP_RETENTION_MODULE_MODEM_PHY    = 31,
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
 
@@ -57,6 +58,7 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
     SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
     SLEEP_RETENTION_MODULE_BM_802154_MAC   = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
+    SLEEP_RETENTION_MODULE_BM_MODEM_PHY    = BIT(SLEEP_RETENTION_MODULE_MODEM_PHY),
 
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
      * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */

components/soc/esp32c5/include/soc/soc_caps.h

@@ -539,8 +539,8 @@
 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
 
 /*-------------------------- Power Management CAPS ----------------------------*/
-// #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
+#define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+#define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
 #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
 #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
@@ -552,12 +552,12 @@
 #define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
 #define SOC_PM_SUPPORT_TOP_PD           (1)
 #define SOC_PM_SUPPORT_HP_AON_PD        (1)
-// #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
+#define SOC_PM_SUPPORT_MAC_BB_PD        (1)
 #define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
 
-// #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
+#define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
 /* macro redefine for pass esp_wifi headers md5sum check */
-// #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+#define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
 
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
@@ -568,6 +568,7 @@
 
 #define SOC_PM_PAU_LINK_NUM                 (5)
 #define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
+#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC  (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
 
@@ -594,7 +595,7 @@
 #define SOC_WIFI_CSI_SUPPORT                (1)    /*!< Support CSI */
 #define SOC_WIFI_MESH_SUPPORT               (1)    /*!< Support WIFI MESH */
 #define SOC_WIFI_HE_SUPPORT                 (1)    /*!< Support Wi-Fi 6 */
-#define SOC_WIFI_HE_SUPPORT_5G              (1)    /*!< Support Wi-Fi 6 in 5G */
+#define SOC_WIFI_SUPPORT_5G                 (1)    /*!< Support 5G */
 #define SOC_WIFI_MAC_VERSION_NUM            (3)    /*!< Wi-Fi MAC version num is 3 */
 
 /*---------------------------------- Bluetooth CAPS ----------------------------------*/

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -71,6 +71,10 @@ config SOC_SYSTIMER_SUPPORTED
     bool
     default y
 
+config SOC_SHA_SUPPORTED
+    bool
+    default y
+
 config SOC_ECC_SUPPORTED
     bool
     default y
@@ -91,6 +95,10 @@ config SOC_BOD_SUPPORTED
     bool
     default y
 
+config SOC_APM_SUPPORTED
+    bool
+    default y
+
 config SOC_PMU_SUPPORTED
     bool
     default y
@@ -99,6 +107,10 @@ config SOC_LP_TIMER_SUPPORTED
     bool
     default y
 
+config SOC_LP_AON_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_TREE_SUPPORTED
     bool
     default y
@@ -123,6 +135,10 @@ config SOC_LIGHT_SLEEP_SUPPORTED
     bool
     default y
 
+config SOC_DEEP_SLEEP_SUPPORTED
+    bool
+    default y
+
 config SOC_PM_SUPPORTED
     bool
     default y
@@ -287,6 +303,10 @@ config SOC_GPIO_OUT_RANGE_MAX
     int
     default 21
 
+config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+    bool
+    default y
+
 config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
     int
     default 0
@@ -467,6 +487,34 @@ config SOC_MPU_REGION_WO_SUPPORTED
     bool
     default n
 
+config SOC_SHA_DMA_MAX_BUFFER_SIZE
+    int
+    default 3968
+
+config SOC_SHA_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_RESUME
+    bool
+    default y
+
+config SOC_SHA_GDMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA1
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA224
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA256
+    bool
+    default y
+
 config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
     bool
     default y
@@ -683,6 +731,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
     bool
     default y
 
+config SOC_APM_CTRL_FILTER_SUPPORTED
+    bool
+    default y
+
 config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
     bool
     default y
@@ -743,6 +795,14 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
     int
     default 12
 
+config SOC_PM_SUPPORT_EXT1_WAKEUP
+    bool
+    default y
+
+config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
+    bool
+    default y
+
 config SOC_PM_SUPPORT_CPU_PD
     bool
     default y

components/soc/esp32c61/include/soc/hwcrypto_reg.h

@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/sha_reg.h"

components/soc/esp32c61/include/soc/reg_base.h

@@ -61,3 +61,4 @@
 #define DR_REG_INTPRI_BASE                      0x600C5000
 #define DR_REG_CACHE_BASE                       0x600C8000
 #define DR_REG_CLINT_M_BASE                     0x20000000
+#define DR_REG_TEE_BASE                         DR_REG_TEE_REG_BASE

components/soc/esp32c61/include/soc/soc.h

@@ -146,20 +146,21 @@
  * should be defined statically!
  */
 
-#define SOC_IROM_LOW    0x42000000
-#define SOC_IROM_HIGH   0x44000000
-#define SOC_EXTRAM_DATA_LOW 0x42000000
-#define SOC_EXTRAM_DATA_HIGH 0x44000000
-#define SOC_DROM_LOW    SOC_IROM_LOW
-#define SOC_DROM_HIGH   SOC_IROM_HIGH
-#define SOC_IROM_MASK_LOW  0x40000000
-#define SOC_IROM_MASK_HIGH 0x40040000
-#define SOC_DROM_MASK_LOW  0x40000000
-#define SOC_DROM_MASK_HIGH 0x40040000
-#define SOC_IRAM_LOW    0x40800000
-#define SOC_IRAM_HIGH   0x40850000
-#define SOC_DRAM_LOW    0x40800000
-#define SOC_DRAM_HIGH   0x40850000
+#define SOC_IROM_LOW            0x42000000
+#define SOC_IROM_HIGH           0x44000000
+#define SOC_EXTRAM_DATA_LOW     0x42000000
+#define SOC_EXTRAM_DATA_HIGH    0x44000000
+#define SOC_EXTRAM_DATA_SIZE    (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
+#define SOC_DROM_LOW            SOC_IROM_LOW
+#define SOC_DROM_HIGH           SOC_IROM_HIGH
+#define SOC_IROM_MASK_LOW       0x40000000
+#define SOC_IROM_MASK_HIGH      0x40040000
+#define SOC_DROM_MASK_LOW       0x40000000
+#define SOC_DROM_MASK_HIGH      0x40040000
+#define SOC_IRAM_LOW            0x40800000
+#define SOC_IRAM_HIGH           0x40850000
+#define SOC_DRAM_LOW            0x40800000
+#define SOC_DRAM_HIGH           0x40850000
 
 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
 #define SOC_DIRAM_IRAM_LOW    0x40800000
@@ -196,7 +197,7 @@
 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
-#define SOC_ROM_STACK_START         0x4084c9f0
+#define SOC_ROM_STACK_START         0x4084ea70
 #define SOC_ROM_STACK_SIZE          0x2000
 
 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.

components/soc/esp32c61/include/soc/soc_caps.h

@@ -39,16 +39,16 @@
 #define SOC_LEDC_SUPPORTED              1
 #define SOC_SYSTIMER_SUPPORTED          1
 //  \#define SOC_SUPPORT_COEXISTENCE         1
-//  \#define SOC_SHA_SUPPORTED               1    //TODO: [ESP32C61] IDF-9234
+#define SOC_SHA_SUPPORTED               1
 #define SOC_ECC_SUPPORTED               1
 #define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
 #define SOC_FLASH_ENC_SUPPORTED         1
 #define SOC_SECURE_BOOT_SUPPORTED       1
 #define SOC_BOD_SUPPORTED               1
-//  \#define SOC_APM_SUPPORTED               1    //TODO: [ESP32C61] IDF-9230
+#define SOC_APM_SUPPORTED               1 /*!< Support for APM peripheral */
 #define SOC_PMU_SUPPORTED               1
 #define SOC_LP_TIMER_SUPPORTED          1
-//  \#define SOC_LP_AON_SUPPORTED            1
+#define SOC_LP_AON_SUPPORTED            1
 //  \#define SOC_LP_PERIPHERALS_SUPPORTED    1
  #define SOC_CLK_TREE_SUPPORTED          1
 //  \#define SOC_ASSIST_DEBUG_SUPPORTED      1    //TODO: [ESP32C61] IDF-9269
@@ -61,6 +61,7 @@
 //  \#define SOC_SDIO_SLAVE_SUPPORTED        0
 //  \#define SOC_PAU_SUPPORTED               0
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
+#define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_PM_SUPPORTED                1
 #define SOC_ECDSA_SUPPORTED             1
 #define SOC_SPIRAM_SUPPORTED            1
@@ -179,7 +180,7 @@
 #define SOC_GPIO_OUT_RANGE_MAX          21
 
 // GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
-//  \#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  //TODO: IDF-9245
+#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT      (7)
 
@@ -274,19 +275,19 @@
    for SHA this means that the biggest safe amount of bytes is
    31 blocks of 128 bytes = 3968
 */
-// #define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
-// #define SOC_SHA_SUPPORT_DMA             (1)
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
 
 // /* The SHA engine is able to resume hashing from a user */
-// #define SOC_SHA_SUPPORT_RESUME          (1)
+#define SOC_SHA_SUPPORT_RESUME          (1)
 
 // /* Has a centralized DMA, which is shared with all peripherals */
-// #define SOC_SHA_GDMA             (1)
+#define SOC_SHA_GDMA             (1)
 
 // /* Supported HW algorithms */
-// #define SOC_SHA_SUPPORT_SHA1            (1)
-// #define SOC_SHA_SUPPORT_SHA224          (1)
-// #define SOC_SHA_SUPPORT_SHA256          (1)
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
 
 /*--------------------------- ECDSA CAPS ---------------------------------------*/
 #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY     (1)
@@ -374,6 +375,9 @@
 #define SOC_FLASH_ENCRYPTION_XTS_AES        1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
 
+/*-------------------------- APM CAPS ----------------------------------------*/
+#define SOC_APM_CTRL_FILTER_SUPPORTED   1 /*!< Support for APM control filter */
+
 /*------------------------ Anti DPA (Security) CAPS --------------------------*/
 #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
 
@@ -411,8 +415,8 @@
 // #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
 // #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
 // #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
+#define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
+#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
 #define SOC_PM_SUPPORT_CPU_PD           (1)
 #define SOC_PM_SUPPORT_MODEM_PD         (1)
 #define SOC_PM_SUPPORT_XTAL32K_PD       (1)
@@ -428,8 +432,6 @@
 /* macro redefine for pass esp_wifi headers md5sum check */
 #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
 
-// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
-
 #define SOC_PM_CPU_RETENTION_BY_SW          (1)
 #define SOC_PM_MODEM_RETENTION_BY_REGDMA    (0)
 #define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1)

components/soc/esp32c61/include/soc/tee_reg.h

@@ -768,7 +768,7 @@ extern "C" {
 /** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
  *  Version control register
  */
-#define TEE_DATE_REG    0x0FFFFFFFU
+#define TEE_DATE    0x0FFFFFFFU
 #define TEE_DATE_REG_M  (TEE_DATE_REG_V << TEE_DATE_REG_S)
 #define TEE_DATE_REG_V  0x0FFFFFFFU
 #define TEE_DATE_REG_S  0

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1863,6 +1863,10 @@ config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL
+    bool
+    default y
+
 config SOC_PERIPH_CLK_CTRL_SHARED
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -709,6 +709,8 @@
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
 #define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
+
 
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
 

components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -59,6 +59,16 @@ esp_err_t lp_core_uart_write_bytes(uart_port_t lp_uart_num, const void *src, siz
  */
 int lp_core_uart_read_bytes(uart_port_t lp_uart_num, void *buf, size_t size, int32_t timeout);
 
+/**
+ * @brief Flush LP UART Tx FIFO
+ *
+ * This function is automatically called before the LP core powers down once the main() function returns.
+ * It can also be called manually in the application to flush the Tx FIFO.
+ *
+ * @param lp_uart_num   LP UART port number
+ */
+void lp_core_uart_tx_flush(uart_port_t lp_uart_num);
+
 #ifdef __cplusplus
 }
 #endif

components/ulp/lp_core/lp_core/lp_core_uart.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -63,6 +63,24 @@ int lp_core_uart_tx_chars(uart_port_t lp_uart_num, const void *src, size_t size)
     return tx_len;
 }
 
+void lp_core_uart_tx_flush(uart_port_t lp_uart_num)
+{
+    (void)lp_uart_num;
+    int loop_cnt = 0;
+
+    if (uart_ll_is_enabled(LP_UART_NUM_0) && !uart_hal_is_tx_idle(&hal)) {
+        /* Wait for the Tx FIFO to be empty */
+        while (!(uart_hal_get_intraw_mask(&hal) & (LP_UART_TX_INT_FLAG | LP_UART_ERR_INT_FLAG))) {
+            loop_cnt++;
+            if (loop_cnt > 10000) {
+                /* Bail out */
+                break;
+            }
+        }
+        uart_hal_clr_intsts_mask(&hal, LP_UART_TX_INT_FLAG | LP_UART_ERR_INT_FLAG);
+    }
+}
+
 esp_err_t lp_core_uart_write_bytes(uart_port_t lp_uart_num, const void *src, size_t size, int32_t timeout)
 {
     (void)lp_uart_num;

components/ulp/lp_core/lp_core/lp_core_utils.c

@@ -30,7 +30,17 @@
 #include "esp_cpu.h"
 
 /* LP_FAST_CLK is not very accurate, for now use a rough estimate */
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
 #define LP_CORE_CPU_FREQUENCY_HZ 16000000 // For P4 TRM says 20 MHz by default, but we tune it closer to 16 MHz
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+#if SOC_XTAL_SUPPORT_48M
+#define LP_CORE_CPU_FREQUENCY_HZ 48000000
+#else
+#define LP_CORE_CPU_FREQUENCY_HZ 40000000
+#endif
+#else  // Default value in chip without rtc fast clock sel option
+#define LP_CORE_CPU_FREQUENCY_HZ 16000000
+#endif
 
 static uint32_t lp_wakeup_cause = 0;
 

components/ulp/test_apps/.build-test-rules.yml

@@ -1,6 +1,11 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
-components/ulp/test_apps/lp_core:
+components/ulp/test_apps/lp_core/lp_core_basic_tests:
+  disable:
+    - if: SOC_LP_CORE_SUPPORTED != 1
+    - if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1
+
+components/ulp/test_apps/lp_core/lp_core_hp_uart:
   disable:
     - if: SOC_LP_CORE_SUPPORTED != 1
 

components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core.c

@@ -132,6 +132,7 @@ TEST_CASE("Test LP core delay", "[lp_core]")
 #define LP_TIMER_TEST_SLEEP_DURATION_US (20000)
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
+#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_RTC_FAST_CLK_SRC_RC_FAST
 
 static void do_ulp_wakeup_deepsleep(lp_core_test_commands_t ulp_cmd)
 {
@@ -228,7 +229,8 @@ TEST_CASE_MULTIPLE_STAGES("LP Timer can wakeup lp core periodically during deep
                           do_ulp_wakeup_with_lp_timer_deepsleep,
                           check_reset_reason_and_sleep_duration);
 
-#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
+#endif //#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_RTC_FAST_CLK_SRC_RC_FAST
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
 
 TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
 {
@@ -382,5 +384,4 @@ TEST_CASE("LP core ISR tests", "[ulp]")
     printf("ULP LP IO ISR triggered %"PRIu32" times\n", ulp_io_isr_counter);
     TEST_ASSERT_EQUAL(ISR_TEST_ITERATIONS, ulp_io_isr_counter);
 #endif //SOC_RTCIO_PIN_COUNT > 0
-
 }

components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py

@@ -8,10 +8,31 @@ from pytest_embedded import Dut
 @pytest.mark.esp32c6
 @pytest.mark.esp32p4
 @pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'default',
+    ],
+    indirect=True,
+)
 def test_lp_core(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
 
+@pytest.mark.esp32c5
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'xtal',
+    ],
+    indirect=True,
+)
+def test_lp_core_xtal(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
 @pytest.mark.esp32c6
 # TODO: Enable LP I2C test for esp32p4 (IDF-9407)
 @pytest.mark.generic_multi_device

components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.xtal

@@ -0,0 +1 @@
+CONFIG_RTC_FAST_CLK_SRC_XTAL=y

components/usb/usb_helpers.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,7 +27,7 @@ const usb_standard_desc_t *usb_parse_next_descriptor(const usb_standard_desc_t *
         return NULL;    // Next descriptor is out of bounds
     }
     // Return the next descriptor, update offset
-    const usb_standard_desc_t *ret_desc = (const usb_standard_desc_t *)(((uint32_t)cur_desc) + cur_desc->bLength);
+    const usb_standard_desc_t *ret_desc = (const usb_standard_desc_t *)(((uintptr_t)cur_desc) + cur_desc->bLength);
     *offset += cur_desc->bLength;
     return ret_desc;
 }

components/wpa_supplicant/esp_supplicant/include/esp_dpp.h

@@ -17,11 +17,14 @@ extern "C" {
 #endif
 
 #define ESP_DPP_AUTH_TIMEOUT_SECS 1
+#define ESP_DPP_MAX_CHAN_COUNT 5
 
 #define ESP_ERR_DPP_FAILURE         (ESP_ERR_WIFI_BASE + 151)   /*!< Generic failure during DPP Operation */
 #define ESP_ERR_DPP_TX_FAILURE      (ESP_ERR_WIFI_BASE + 152)   /*!< DPP Frame Tx failed OR not Acked */
 #define ESP_ERR_DPP_INVALID_ATTR    (ESP_ERR_WIFI_BASE + 153)   /*!< Encountered invalid DPP Attribute */
 #define ESP_ERR_DPP_AUTH_TIMEOUT    (ESP_ERR_WIFI_BASE + 154)   /*!< DPP Auth response was not received in time */
+#define ESP_ERR_DPP_INVALID_LIST    (ESP_ERR_WIFI_BASE + 155)   /*!< Channel list given in esp_supp_dpp_bootstrap_gen() is not valid or too big */
+
 /** @brief Types of Bootstrap Methods for DPP. */
 typedef enum dpp_bootstrap_type {
     DPP_BOOTSTRAP_QR_CODE,  /**< QR Code Method */
@@ -83,6 +86,7 @@ esp_err_t esp_supp_dpp_deinit(void);
   *
   * @return
   *    - ESP_OK: Success
+  *    - ESP_ERR_DPP_INVALID_LIST: Channel list not valid
   *    - ESP_FAIL: Failure
   */
 esp_err_t

components/wpa_supplicant/esp_supplicant/src/esp_dpp.c

@@ -15,6 +15,7 @@
 #include "esp_event.h"
 #include "esp_wifi.h"
 #include "common/ieee802_11_defs.h"
+#include "common/ieee802_11_common.h"
 #include "esp_wps_i.h"
 #include "rsn_supp/wpa.h"
 #include "rsn_supp/pmksa_cache.h"
@@ -575,6 +576,7 @@ static void esp_dpp_task(void *pvParameters)
                     break;
                 }
                 channel = p->chan_list[counter++ % p->num_chan];
+                wpa_printf(MSG_DEBUG, "Listening on channel=%d", channel);
                 ret = esp_wifi_remain_on_channel(WIFI_IF_STA, WIFI_ROC_REQ, channel,
                                                  BOOTSTRAP_ROC_WAIT_TIME, s_action_rx_cb);
                 if (ret != ESP_OK) {
@@ -687,47 +689,81 @@ static void offchan_event_handler(void *arg, esp_event_base_t event_base,
 static char *esp_dpp_parse_chan_list(const char *chan_list)
 {
     struct dpp_bootstrap_params_t *params = &s_dpp_ctx.bootstrap_params;
-    char *uri_channels = os_zalloc(14 * 6 + 1);
-    const char *pos = chan_list;
-    const char *pos2;
-    char *pos3 = uri_channels;
+    size_t max_uri_len = ESP_DPP_MAX_CHAN_COUNT * 8 + strlen(" chan=") + 1;
+
+    char *uri_channels = os_zalloc(max_uri_len);
+    if (!uri_channels) {
+        wpa_printf(MSG_WARNING, "DPP: URI allocation failed");
+        return NULL;
+    }
+
+    char *uri_ptr = uri_channels;
     params->num_chan = 0;
 
-    os_memcpy(pos3, " chan=", strlen(" chan="));
-    pos3 += strlen(" chan=");
+    /* Append " chan=" at the beginning of the URI */
+    strcpy(uri_ptr, " chan=");
+    uri_ptr += strlen(" chan=");
 
-    while (pos && *pos) {
-        int channel;
-        int len = strlen(chan_list);
+    while (*chan_list && params->num_chan < ESP_DPP_MAX_CHAN_COUNT) {
+        int channel = 0;
 
-        pos2 = pos;
-        while (*pos2 >= '0' && *pos2 <= '9') {
-            pos2++;
+        /* Parse the channel number */
+        while (*chan_list >= '0' && *chan_list <= '9') {
+            channel = channel * 10 + (*chan_list - '0');
+            chan_list++;
         }
-        if (*pos2 == ',' || *pos2 == ' ' || *pos2 == '\0') {
-            channel = atoi(pos);
-            if (channel < 1 || channel > 14) {
-                os_free(uri_channels);
-                return NULL;
+
+        /* Validate the channel number */
+        if (CHANNEL_TO_BIT_NUMBER(channel) == 0) {
+            wpa_printf(MSG_WARNING, "DPP: Skipping invalid channel %d", channel);
+            /* Skip to the next valid entry */
+            while (*chan_list == ',' || *chan_list == ' ') {
+                chan_list++;
             }
-            params->chan_list[params->num_chan++] = channel;
-            os_memcpy(pos3, "81/", strlen("81/"));
-            pos3 += strlen("81/");
-            os_memcpy(pos3, pos, (pos2 - pos));
-            pos3 += (pos2 - pos);
-            *pos3++ = ',';
-
-            pos = pos2 + 1;
-        }
-        while (*pos == ',' || *pos == ' ' || *pos == '\0') {
-            pos++;
+            continue;  // Skip the bad channel and move to the next one
         }
 
-        if (((int)(pos - chan_list) >= len)) {
-            break;
+        /* Get the operating class for the channel */
+        u8 oper_class = get_operating_class(channel, 0);
+        if (oper_class == 0) {
+            wpa_printf(MSG_WARNING, "DPP: Skipping channel %d due to missing operating class", channel);
+            /* Skip to the next valid entry */
+            while (*chan_list == ',' || *chan_list == ' ') {
+                chan_list++;
+            }
+            continue;  /* Skip to the next channel if no operating class found */
+        }
+
+        /* Add the valid channel to the list */
+        params->chan_list[params->num_chan++] = channel;
+
+        /* Check if there's space left in uri_channels buffer */
+        size_t remaining_space = max_uri_len - (uri_ptr - uri_channels);
+        if (remaining_space <= 8) {  // Oper class + "/" + channel + "," + null terminator
+            wpa_printf(MSG_ERROR, "DPP: Not enough space in URI buffer");
+            os_free(uri_channels);
+            return NULL;
+        }
+
+        /* Append the operating class and channel to the URI */
+        uri_ptr += sprintf(uri_ptr, "%d/%d,", oper_class, channel);
+
+        /* Skip any delimiters (comma or space) */
+        while (*chan_list == ',' || *chan_list == ' ') {
+            chan_list++;
         }
     }
-    *(pos3 - 1) = ' ';
+
+    if (!params->num_chan) {
+        wpa_printf(MSG_ERROR, "DPP: No valid channel in the list");
+        os_free(uri_channels);
+        return NULL;
+    }
+
+    /* Replace the last comma with a space if there was content added */
+    if (uri_ptr > uri_channels && *(uri_ptr - 1) == ',') {
+        *(uri_ptr - 1) = ' ';
+    }
 
     return uri_channels;
 }
@@ -742,10 +778,16 @@ esp_supp_dpp_bootstrap_gen(const char *chan_list, enum dpp_bootstrap_type type,
     }
     struct dpp_bootstrap_params_t *params = &s_dpp_ctx.bootstrap_params;
     char *uri_chan_list = esp_dpp_parse_chan_list(chan_list);
+
+    if (params->num_chan > ESP_DPP_MAX_CHAN_COUNT) {
+        os_free(uri_chan_list);
+        return ESP_ERR_DPP_INVALID_LIST;
+    }
+
     char *command = os_zalloc(1200);
     int ret;
 
-    if (!uri_chan_list || !command || params->num_chan >= 14 || params->num_chan == 0) {
+    if (!uri_chan_list || !command || params->num_chan > ESP_DPP_MAX_CHAN_COUNT || params->num_chan == 0) {
         wpa_printf(MSG_ERROR, "Invalid Channel list - %s", chan_list);
         if (command) {
             os_free(command);

components/wpa_supplicant/esp_supplicant/src/esp_wps.c

@@ -440,9 +440,9 @@ wps_parse_scan_result(struct wps_scan_ie *scan)
                 return false;
             }
             esp_wifi_enable_sta_privacy_internal();
-            os_memset(sm->ssid[0], 0, SSID_MAX_LEN);
-            os_memcpy(sm->ssid[0], (char *)&scan->ssid[2], (int)scan->ssid[1]);
-            sm->ssid_len[0] = scan->ssid[1];
+            os_memset(sm->creds[0].ssid, 0, SSID_MAX_LEN);
+            os_memcpy(sm->creds[0].ssid, (char *)&scan->ssid[2], (int)scan->ssid[1]);
+            sm->creds[0].ssid_len = scan->ssid[1];
             if (scan->bssid && memcmp(sm->bssid, scan->bssid, ETH_ALEN) != 0) {
                 wpa_printf(MSG_INFO, "sm BSSid: "MACSTR " scan BSSID " MACSTR,
                            MAC2STR(sm->bssid), MAC2STR(scan->bssid));
@@ -468,7 +468,7 @@ wps_parse_scan_result(struct wps_scan_ie *scan)
                 }
             }
             wpabuf_free(buf);
-            wpa_printf(MSG_DEBUG, "wps discover [%s] ", (char *)sm->ssid);
+            wpa_printf(MSG_DEBUG, "wps discover [%s] ", (char *)sm->creds[0].ssid);
             sm->channel = scan->chan;
 
             return true;
@@ -793,8 +793,7 @@ static int wps_sm_init(struct wps_sm *sm)
     sm->scan_cnt = 0;
     sm->discover_ssid_cnt = 0;
     os_bzero(sm->bssid, ETH_ALEN);
-    os_bzero(sm->ssid, sizeof(sm->ssid));
-    os_bzero(sm->ssid_len, sizeof(sm->ssid_len));
+    os_bzero(sm->creds, sizeof(sm->creds));
     sm->ap_cred_cnt = 0;
 
     return 0;
@@ -845,9 +844,16 @@ int wps_finish(void)
             }
 
             esp_wifi_get_config(WIFI_IF_STA, config);
-            os_memcpy(config->sta.ssid, sm->ssid[0], sm->ssid_len[0]);
-            os_memcpy(config->sta.password, sm->key[0], sm->key_len[0]);
+            os_memcpy(config->sta.ssid, sm->creds[0].ssid, sm->creds[0].ssid_len);
+            os_memcpy(config->sta.password, sm->creds[0].key, sm->creds[0].key_len);
             os_memcpy(config->sta.bssid, sm->bssid, ETH_ALEN);
+#ifndef CONFIG_WPS_STRICT
+            /* Some APs support AES in WPA IE, enable connection with them */
+            if (sm->creds[0].auth_type == WPS_AUTH_WPAPSK &&
+                    (sm->creds[0].encr_type & WPS_ENCR_AES)) {
+                config->sta.threshold.authmode = WIFI_AUTH_WPA_PSK;
+            }
+#endif
             config->sta.bssid_set = 0;
             config->sta.sae_pwe_h2e = 0;
             esp_wifi_set_config(WIFI_IF_STA, config);
@@ -863,8 +869,7 @@ int wps_finish(void)
         if (sm->ignore_sel_reg) {
             sm->discover_ssid_cnt = 0;
             esp_wifi_disconnect();
-            os_bzero(sm->ssid, sizeof(sm->ssid));
-            os_bzero(sm->ssid_len, sizeof(sm->ssid_len));
+            os_bzero(sm->creds, sizeof(sm->creds));
             wps_add_discard_ap(sm->bssid);
         } else {
             ret = wps_stop_process(WPS_FAIL_REASON_NORMAL);
@@ -1313,8 +1318,7 @@ wifi_station_wps_msg_timeout_internal(void)
     if (sm->ignore_sel_reg) {
         esp_wifi_disconnect();
         wps_add_discard_ap(sm->bssid);
-        os_bzero(sm->ssid, sizeof(sm->ssid));
-        os_bzero(sm->ssid_len, sizeof(sm->ssid_len));
+        os_bzero(sm->creds, sizeof(sm->creds));
         os_bzero(sm->bssid, ETH_ALEN);
         sm->discover_ssid_cnt = 0;
         wifi_wps_scan(NULL, NULL);
@@ -1344,8 +1348,8 @@ void wifi_station_wps_success_internal(void)
     if (sm->ap_cred_cnt > 1) {
         evt.ap_cred_cnt = sm->ap_cred_cnt;
         for (i = 0; i < MAX_WPS_AP_CRED; i++) {
-            os_memcpy(evt.ap_cred[i].ssid, sm->ssid[i], sm->ssid_len[i]);
-            os_memcpy(evt.ap_cred[i].passphrase, sm->key[i], sm->key_len[i]);
+            os_memcpy(evt.ap_cred[i].ssid, sm->creds[i].ssid, sm->creds[i].ssid_len);
+            os_memcpy(evt.ap_cred[i].passphrase, sm->creds[i].key, sm->creds[i].key_len);
         }
         esp_event_post(WIFI_EVENT, WIFI_EVENT_STA_WPS_ER_SUCCESS, &evt,
                                 sizeof(evt), OS_BLOCK);
@@ -1383,17 +1387,13 @@ void wifi_station_wps_eapol_start_handle(void *data, void *user_ctx)
 
 static int save_credentials_cb(void *ctx, const struct wps_credential *cred)
 {
-    if (!gWpsSm || !cred || gWpsSm->ap_cred_cnt > 2) {
+    struct wps_credential *creds;
+    if (!gWpsSm || !cred || gWpsSm->ap_cred_cnt > MAX_CRED_COUNT) {
         return ESP_FAIL;
     }
 
-    os_memset(gWpsSm->ssid[gWpsSm->ap_cred_cnt], 0x00, sizeof(gWpsSm->ssid[gWpsSm->ap_cred_cnt]));
-    os_memset(gWpsSm->key[gWpsSm->ap_cred_cnt], 0x00, sizeof(gWpsSm->key[gWpsSm->ap_cred_cnt]));
-
-    os_memcpy(gWpsSm->ssid[gWpsSm->ap_cred_cnt], cred->ssid, cred->ssid_len);
-    gWpsSm->ssid_len[gWpsSm->ap_cred_cnt] = cred->ssid_len;
-    os_memcpy(gWpsSm->key[gWpsSm->ap_cred_cnt], cred->key, cred->key_len);
-    gWpsSm->key_len[gWpsSm->ap_cred_cnt] = cred->key_len;
+    creds = &gWpsSm->creds[gWpsSm->ap_cred_cnt];
+    memcpy(creds, cred, sizeof(*creds));
 
     gWpsSm->ap_cred_cnt++;
 
@@ -1646,11 +1646,11 @@ wifi_wps_scan_done(void *arg, ETS_STATUS status)
         esp_wifi_disconnect();
 
         os_memcpy(wifi_config.sta.bssid, sm->bssid, ETH_ALEN);
-        os_memcpy(wifi_config.sta.ssid, (char *)sm->ssid[0], sm->ssid_len[0]);
+        os_memcpy(wifi_config.sta.ssid, (char *)sm->creds[0].ssid, sm->creds[0].ssid_len);
         wifi_config.sta.bssid_set = 1;
         wifi_config.sta.channel = sm->channel;
         wpa_printf(MSG_INFO, "WPS: connecting to %s, bssid=" MACSTR,
-                   (char *)sm->ssid[0], MAC2STR(wifi_config.sta.bssid));
+                   (char *)sm->creds[0].ssid, MAC2STR(wifi_config.sta.bssid));
         esp_wifi_set_config(0, &wifi_config);
 
         wpa_printf(MSG_DEBUG, "WPS: neg start");

components/wpa_supplicant/esp_supplicant/src/esp_wps_i.h

@@ -6,6 +6,8 @@
 
 #include "esp_wifi_driver.h"
 #include "esp_wps.h"
+#include "wps/wps.h"
+#include "wps/wps_attr_parse.h"
 
 /* WPS message flag */
 enum wps_msg_flag {
@@ -57,15 +59,6 @@ struct discard_ap_list_t {
     u8 bssid[6];
 };
 
-#ifndef MAX_PASSPHRASE_LEN
-#define MAX_PASSPHRASE_LEN 64
-#endif
-
-#ifndef MAX_CRED_COUNT
-#define MAX_CRED_COUNT 10
-#endif
-
-#define WPS_OUTBUF_SIZE 500
 struct wps_sm {
     u8 state;
     struct wps_config *wps_cfg;
@@ -75,10 +68,7 @@ struct wps_sm {
     u8 identity_len;
     u8 ownaddr[ETH_ALEN];
     u8 bssid[ETH_ALEN];
-    u8 ssid[MAX_CRED_COUNT][SSID_MAX_LEN];
-    u8 ssid_len[MAX_CRED_COUNT];
-    char key[MAX_CRED_COUNT][MAX_PASSPHRASE_LEN];
-    u8 key_len[MAX_CRED_COUNT];
+    struct wps_credential creds[MAX_CRED_COUNT];
     u8 ap_cred_cnt;
     struct wps_device_data *dev;
     u8 uuid[16];

components/wpa_supplicant/src/common/ieee802_11_common.c

@@ -357,16 +357,54 @@ int ieee802_11_ext_capab(const u8 *ie, unsigned int capab)
 
 u8 get_operating_class(u8 chan, int sec_channel)
 {
-	u8 op_class;
+	u8 op_class = 0;
 
-	if (chan < 1 || chan > 14)
-		return 0;
-	if (sec_channel == 1)
-		op_class = 83;
-	else if (sec_channel == -1)
-		op_class = 84;
-	else
-		op_class = 81;
+	if (chan >= 1 && chan < 14) {
+		if (sec_channel == 1)
+			op_class = 83;
+		else if (sec_channel == -1)
+			op_class = 84;
+		else
+			op_class = 81;
+	}
+
+	if (chan == 14)
+		op_class = 82;
+
+#if SOC_WIFI_SUPPORT_5G
+	if (chan >= 36 && chan <= 48) {
+		if (sec_channel == 1)
+			op_class = 116;
+		else if (sec_channel == -1)
+			op_class = 117;
+		else
+			op_class = 115;
+	}
+	if (chan >= 52 && chan <= 64) {
+		if (sec_channel == 1)
+			op_class = 119;
+		else if (sec_channel == -1)
+			op_class = 120;
+		else
+			op_class = 118;
+	}
+	if (chan >= 149 && chan <= 177) {
+		if (sec_channel == 1)
+			op_class = 126;
+		else if (sec_channel == -1)
+			op_class = 127;
+		else
+			op_class = 125;
+	}
+	if (chan >= 100 && chan <= 144) {
+		if (sec_channel == 1)
+			op_class = 122;
+		else if (sec_channel == -1)
+			op_class = 123;
+		else
+			op_class = 121;
+	}
+#endif
 
 	return op_class;
 }

components/wpa_supplicant/src/wps/wps_attr_parse.h

@@ -84,7 +84,11 @@ struct wps_parse_attr {
 	u16 oob_dev_password_len;
 
 	/* attributes that can occur multiple times */
+#ifdef ESP_SUPPLICANT
+#define MAX_CRED_COUNT MAX_WPS_AP_CRED
+#else
 #define MAX_CRED_COUNT 10
+#endif
 #define MAX_REQ_DEV_TYPE_COUNT 10
 
 	unsigned int num_cred;

docs/en/api-reference/peripherals/lcd/spi_lcd.rst

@@ -5,14 +5,16 @@ SPI Interfaced LCD
 
 #. Create an SPI bus. Please refer to :doc:`SPI Master API doc </api-reference/peripherals/spi_master>` for more details.
 
+    Currently the driver supports SPI, Quad SPI and Octal SPI (simulate Intel 8080 timing) modes.
+
     .. code-block:: c
 
         spi_bus_config_t buscfg = {
             .sclk_io_num = EXAMPLE_PIN_NUM_SCLK,
             .mosi_io_num = EXAMPLE_PIN_NUM_MOSI,
             .miso_io_num = EXAMPLE_PIN_NUM_MISO,
-            .quadwp_io_num = -1, // Quad SPI LCD driver is not yet supported
-            .quadhd_io_num = -1, // Quad SPI LCD driver is not yet supported
+            .quadwp_io_num = -1,
+            .quadhd_io_num = -1,
             .max_transfer_sz = EXAMPLE_LCD_H_RES * 80 * sizeof(uint16_t), // transfer 80 lines of pixels (assume pixel is RGB565) at most in one SPI transaction
         };
         ESP_ERROR_CHECK(spi_bus_initialize(LCD_HOST, &buscfg, SPI_DMA_CH_AUTO)); // Enable the DMA feature

docs/en/api-reference/system/ulp-lp-core.rst

@@ -262,6 +262,19 @@ For example, to override the handler for the LP IO interrupt, you can define the
 
 In addition to configuring the interrupt related registers for the interrupt source you want to handle, you also need to enable the interrupts globally in the LP-Core interrupt controller. This can be done using the :cpp:func:`ulp_lp_core_intr_enable` function.
 
+ULP LP-Core Clock Configuration
+-------------------------------
+{IDF_TARGET_XTAL_FREQ:default="Not updated", esp32c5="48 MHz", esp32p4="40 MHz"}
+
+The ULP LP-Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details.
+
+.. only:: SOC_CLK_LP_FAST_SUPPORT_XTAL
+
+    On {IDF_TARGET_NAME} ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as the source for ``LP_FAST_CLK``, which allows the ULP LP-Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK`` which runs at around 20 MHz. The drawback is that this clock is normally powered down during sleep to reduce power consumption, with it selected XTAL will also stay powered on during sleep, increasing power consumption. If you only plan to use the LP-Core as a co-processor while the HP-Core is active, then this option can be used to increase both the performance and the frequency stability of the LP-Core.
+
+    To enable this feature set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``.
+
+
 Debugging ULP LP-Core Applications
 ----------------------------------
 

docs/zh_CN/api-reference/peripherals/lcd/spi_lcd.rst

@@ -5,14 +5,16 @@ SPI 接口的 LCD
 
 #. 创建 SPI 总线。详情请参阅 :doc:`SPI 主机 API 文档 </api-reference/peripherals/spi_master>`。
 
+    目前驱动支持 SPI， Quad SPI 和 Octal SPI（模拟 Intel 8080 时序）模式。
+
     .. code-block:: c
 
         spi_bus_config_t buscfg = {
             .sclk_io_num = EXAMPLE_PIN_NUM_SCLK,
             .mosi_io_num = EXAMPLE_PIN_NUM_MOSI,
             .miso_io_num = EXAMPLE_PIN_NUM_MISO,
-            .quadwp_io_num = -1, // 目前不支持 Quad SPI LCD 驱动
-            .quadhd_io_num = -1, // 目前不支持 Quad SPI LCD 驱动
+            .quadwp_io_num = -1,
+            .quadhd_io_num = -1,
             .max_transfer_sz = EXAMPLE_LCD_H_RES * 80 * sizeof(uint16_t), // 单次最多可传输 80 行像素（假设像素格式为 RGB565）
         };
         ESP_ERROR_CHECK(spi_bus_initialize(LCD_HOST, &buscfg, SPI_DMA_CH_AUTO)); // 启用 DMA

examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/sdkconfig.defaults.esp32c5

@@ -1,2 +1,2 @@
-CONFIG_BLINK_GPIO=6
+CONFIG_BLINK_GPIO=27
 CONFIG_BLINK_LED_STRIP=y

examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/sdkconfig.defaults.esp32c5

@@ -1,2 +1,2 @@
-CONFIG_BLINK_GPIO=6
+CONFIG_BLINK_GPIO=27
 CONFIG_BLINK_LED_STRIP=y

examples/bluetooth/ble_get_started/nimble/NimBLE_Security/sdkconfig.defaults.esp32c5

@@ -1,2 +1,2 @@
-CONFIG_BLINK_GPIO=6
+CONFIG_BLINK_GPIO=27
 CONFIG_BLINK_LED_STRIP=y

examples/peripherals/.build-test-rules.yml

@@ -468,7 +468,7 @@ examples/peripherals/usb/device:
   disable:
     - if: SOC_USB_OTG_SUPPORTED != 1
   disable_test:
-    - if: IDF_TARGET not in ["esp32s2"]
+    - if: IDF_TARGET not in ["esp32s2", "esp32p4"]
       temporary: true
       reason: lack of runners with usb_device tag
   depends_components:

examples/peripherals/lcd/spi_lcd_touch/main/idf_component.yml

@@ -1,6 +1,5 @@
 dependencies:
-  idf: ">=4.4"
-  lvgl/lvgl: "~8.3.0"
+  lvgl/lvgl: "~9.2.0"
   esp_lcd_ili9341: "^1.0"
   esp_lcd_gc9a01: "^1.0"
   esp_lcd_touch_stmpe610: "^1.0"

examples/peripherals/lcd/spi_lcd_touch/main/lvgl_demo_ui.c

@@ -1,86 +1,56 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
 
-// This demo UI is adapted from LVGL official example: https://docs.lvgl.io/master/widgets/extra/meter.html#simple-meter
+// This demo UI is adapted from LVGL official example: https://docs.lvgl.io/master/examples.html#loader-with-arc
 
 #include "lvgl.h"
 
-static lv_obj_t *meter;
 static lv_obj_t * btn;
-static lv_disp_rot_t rotation = LV_DISP_ROT_NONE;
-
-static void set_value(void *indic, int32_t v)
-{
-    lv_meter_set_indicator_end_value(meter, indic, v);
-}
+static lv_display_rotation_t rotation = LV_DISP_ROTATION_0;
 
 static void btn_cb(lv_event_t * e)
 {
-    lv_disp_t *disp = lv_event_get_user_data(e);
+    lv_display_t *disp = lv_event_get_user_data(e);
     rotation++;
-    if (rotation > LV_DISP_ROT_270) {
-        rotation = LV_DISP_ROT_NONE;
+    if (rotation > LV_DISP_ROTATION_270) {
+        rotation = LV_DISP_ROTATION_0;
     }
     lv_disp_set_rotation(disp, rotation);
 }
-
-void example_lvgl_demo_ui(lv_disp_t *disp)
+static void set_angle(void * obj, int32_t v)
 {
-    lv_obj_t *scr = lv_disp_get_scr_act(disp);
-    meter = lv_meter_create(scr);
-    lv_obj_center(meter);
-    lv_obj_set_size(meter, 200, 200);
+    lv_arc_set_value(obj, v);
+}
 
-    /*Add a scale first*/
-    lv_meter_scale_t *scale = lv_meter_add_scale(meter);
-    lv_meter_set_scale_ticks(meter, scale, 41, 2, 10, lv_palette_main(LV_PALETTE_GREY));
-    lv_meter_set_scale_major_ticks(meter, scale, 8, 4, 15, lv_color_black(), 10);
+void example_lvgl_demo_ui(lv_display_t *disp)
+{
+    lv_obj_t *scr = lv_display_get_screen_active(disp);
 
-    lv_meter_indicator_t *indic;
-
-    /*Add a blue arc to the start*/
-    indic = lv_meter_add_arc(meter, scale, 3, lv_palette_main(LV_PALETTE_BLUE), 0);
-    lv_meter_set_indicator_start_value(meter, indic, 0);
-    lv_meter_set_indicator_end_value(meter, indic, 20);
-
-    /*Make the tick lines blue at the start of the scale*/
-    indic = lv_meter_add_scale_lines(meter, scale, lv_palette_main(LV_PALETTE_BLUE), lv_palette_main(LV_PALETTE_BLUE), false, 0);
-    lv_meter_set_indicator_start_value(meter, indic, 0);
-    lv_meter_set_indicator_end_value(meter, indic, 20);
-
-    /*Add a red arc to the end*/
-    indic = lv_meter_add_arc(meter, scale, 3, lv_palette_main(LV_PALETTE_RED), 0);
-    lv_meter_set_indicator_start_value(meter, indic, 80);
-    lv_meter_set_indicator_end_value(meter, indic, 100);
-
-    /*Make the tick lines red at the end of the scale*/
-    indic = lv_meter_add_scale_lines(meter, scale, lv_palette_main(LV_PALETTE_RED), lv_palette_main(LV_PALETTE_RED), false, 0);
-    lv_meter_set_indicator_start_value(meter, indic, 80);
-    lv_meter_set_indicator_end_value(meter, indic, 100);
-
-    /*Add a needle line indicator*/
-    indic = lv_meter_add_needle_line(meter, scale, 4, lv_palette_main(LV_PALETTE_GREY), -10);
-
-    btn = lv_btn_create(scr);
+    btn = lv_button_create(scr);
     lv_obj_t * lbl = lv_label_create(btn);
     lv_label_set_text_static(lbl, LV_SYMBOL_REFRESH" ROTATE");
     lv_obj_align(btn, LV_ALIGN_BOTTOM_LEFT, 30, -30);
     /*Button event*/
     lv_obj_add_event_cb(btn, btn_cb, LV_EVENT_CLICKED, disp);
 
-    /*Create an animation to set the value*/
+    /*Create an Arc*/
+    lv_obj_t * arc = lv_arc_create(scr);
+    lv_arc_set_rotation(arc, 270);
+    lv_arc_set_bg_angles(arc, 0, 360);
+    lv_obj_remove_style(arc, NULL, LV_PART_KNOB);   /*Be sure the knob is not displayed*/
+    lv_obj_remove_flag(arc, LV_OBJ_FLAG_CLICKABLE);  /*To not allow adjusting by click*/
+    lv_obj_center(arc);
+
     lv_anim_t a;
     lv_anim_init(&a);
-    lv_anim_set_exec_cb(&a, set_value);
-    lv_anim_set_var(&a, indic);
+    lv_anim_set_var(&a, arc);
+    lv_anim_set_exec_cb(&a, set_angle);
+    lv_anim_set_duration(&a, 1000);
+    lv_anim_set_repeat_count(&a, LV_ANIM_REPEAT_INFINITE);    /*Just for the demo*/
+    lv_anim_set_repeat_delay(&a, 500);
     lv_anim_set_values(&a, 0, 100);
-    lv_anim_set_time(&a, 2000);
-    lv_anim_set_repeat_delay(&a, 100);
-    lv_anim_set_playback_time(&a, 500);
-    lv_anim_set_playback_delay(&a, 100);
-    lv_anim_set_repeat_count(&a, LV_ANIM_REPEAT_INFINITE);
     lv_anim_start(&a);
 }

examples/peripherals/lcd/spi_lcd_touch/main/spi_lcd_touch_example_main.c

@@ -1,13 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
 
 #include <stdio.h>
+#include <unistd.h>
+#include <sys/lock.h>
+#include <sys/param.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
-#include "freertos/semphr.h"
 #include "esp_timer.h"
 #include "esp_lcd_panel_io.h"
 #include "esp_lcd_panel_vendor.h"
@@ -60,99 +62,80 @@ static const char *TAG = "example";
 #define EXAMPLE_LCD_CMD_BITS           8
 #define EXAMPLE_LCD_PARAM_BITS         8
 
+#define EXAMPLE_LVGL_DRAW_BUF_LINES    20 // number of display lines in each draw buffer
 #define EXAMPLE_LVGL_TICK_PERIOD_MS    2
 #define EXAMPLE_LVGL_TASK_MAX_DELAY_MS 500
 #define EXAMPLE_LVGL_TASK_MIN_DELAY_MS 1
 #define EXAMPLE_LVGL_TASK_STACK_SIZE   (4 * 1024)
 #define EXAMPLE_LVGL_TASK_PRIORITY     2
 
-static SemaphoreHandle_t lvgl_mux = NULL;
-
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-esp_lcd_touch_handle_t tp = NULL;
-#endif
+// LVGL library is not thread-safe, this example will call LVGL APIs from different tasks, so use a mutex to protect it
+static _lock_t lvgl_api_lock;
 
 extern void example_lvgl_demo_ui(lv_disp_t *disp);
 
 static bool example_notify_lvgl_flush_ready(esp_lcd_panel_io_handle_t panel_io, esp_lcd_panel_io_event_data_t *edata, void *user_ctx)
 {
-    lv_disp_drv_t *disp_driver = (lv_disp_drv_t *)user_ctx;
-    lv_disp_flush_ready(disp_driver);
+    lv_display_t *disp = (lv_display_t *)user_ctx;
+    lv_display_flush_ready(disp);
     return false;
 }
 
-static void example_lvgl_flush_cb(lv_disp_drv_t *drv, const lv_area_t *area, lv_color_t *color_map)
-{
-    esp_lcd_panel_handle_t panel_handle = (esp_lcd_panel_handle_t) drv->user_data;
-    int offsetx1 = area->x1;
-    int offsetx2 = area->x2;
-    int offsety1 = area->y1;
-    int offsety2 = area->y2;
-    // copy a buffer's content to a specific area of the display
-    esp_lcd_panel_draw_bitmap(panel_handle, offsetx1, offsety1, offsetx2 + 1, offsety2 + 1, color_map);
-}
-
 /* Rotate display and touch, when rotated screen in LVGL. Called when driver parameters are updated. */
-static void example_lvgl_port_update_callback(lv_disp_drv_t *drv)
+static void example_lvgl_port_update_callback(lv_display_t *disp)
 {
-    esp_lcd_panel_handle_t panel_handle = (esp_lcd_panel_handle_t) drv->user_data;
+    esp_lcd_panel_handle_t panel_handle = lv_display_get_user_data(disp);
+    lv_display_rotation_t rotation = lv_display_get_rotation(disp);
 
-    switch (drv->rotated) {
-    case LV_DISP_ROT_NONE:
+    switch (rotation) {
+    case LV_DISPLAY_ROTATION_0:
         // Rotate LCD display
         esp_lcd_panel_swap_xy(panel_handle, false);
         esp_lcd_panel_mirror(panel_handle, true, false);
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-        // Rotate LCD touch
-        esp_lcd_touch_set_mirror_y(tp, false);
-        esp_lcd_touch_set_mirror_x(tp, false);
-#endif
         break;
-    case LV_DISP_ROT_90:
+    case LV_DISPLAY_ROTATION_90:
         // Rotate LCD display
         esp_lcd_panel_swap_xy(panel_handle, true);
         esp_lcd_panel_mirror(panel_handle, true, true);
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-        // Rotate LCD touch
-        esp_lcd_touch_set_mirror_y(tp, false);
-        esp_lcd_touch_set_mirror_x(tp, false);
-#endif
         break;
-    case LV_DISP_ROT_180:
+    case LV_DISPLAY_ROTATION_180:
         // Rotate LCD display
         esp_lcd_panel_swap_xy(panel_handle, false);
         esp_lcd_panel_mirror(panel_handle, false, true);
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-        // Rotate LCD touch
-        esp_lcd_touch_set_mirror_y(tp, false);
-        esp_lcd_touch_set_mirror_x(tp, false);
-#endif
         break;
-    case LV_DISP_ROT_270:
+    case LV_DISPLAY_ROTATION_270:
         // Rotate LCD display
         esp_lcd_panel_swap_xy(panel_handle, true);
         esp_lcd_panel_mirror(panel_handle, false, false);
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-        // Rotate LCD touch
-        esp_lcd_touch_set_mirror_y(tp, false);
-        esp_lcd_touch_set_mirror_x(tp, false);
-#endif
         break;
     }
 }
 
+static void example_lvgl_flush_cb(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map)
+{
+    example_lvgl_port_update_callback(disp);
+    esp_lcd_panel_handle_t panel_handle = lv_display_get_user_data(disp);
+    int offsetx1 = area->x1;
+    int offsetx2 = area->x2;
+    int offsety1 = area->y1;
+    int offsety2 = area->y2;
+    // because SPI LCD is big-endian, we need to swap the RGB bytes order
+    lv_draw_sw_rgb565_swap(px_map, (offsetx2 + 1 - offsetx1) * (offsety2 + 1 - offsety1));
+    // copy a buffer's content to a specific area of the display
+    esp_lcd_panel_draw_bitmap(panel_handle, offsetx1, offsety1, offsetx2 + 1, offsety2 + 1, px_map);
+}
+
 #if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-static void example_lvgl_touch_cb(lv_indev_drv_t * drv, lv_indev_data_t * data)
+static void example_lvgl_touch_cb(lv_indev_t * indev, lv_indev_data_t * data)
 {
     uint16_t touchpad_x[1] = {0};
     uint16_t touchpad_y[1] = {0};
     uint8_t touchpad_cnt = 0;
 
-    /* Read touch controller data */
-    esp_lcd_touch_read_data(drv->user_data);
-
+    esp_lcd_touch_handle_t touch_pad = lv_indev_get_user_data(indev);
+    esp_lcd_touch_read_data(touch_pad);
     /* Get coordinates */
-    bool touchpad_pressed = esp_lcd_touch_get_coordinates(drv->user_data, touchpad_x, touchpad_y, NULL, &touchpad_cnt, 1);
+    bool touchpad_pressed = esp_lcd_touch_get_coordinates(touch_pad, touchpad_x, touchpad_y, NULL, &touchpad_cnt, 1);
 
     if (touchpad_pressed && touchpad_cnt > 0) {
         data->point.x = touchpad_x[0];
@@ -170,44 +153,23 @@ static void example_increase_lvgl_tick(void *arg)
     lv_tick_inc(EXAMPLE_LVGL_TICK_PERIOD_MS);
 }
 
-bool example_lvgl_lock(int timeout_ms)
-{
-    // Convert timeout in milliseconds to FreeRTOS ticks
-    // If `timeout_ms` is set to -1, the program will block until the condition is met
-    const TickType_t timeout_ticks = (timeout_ms == -1) ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
-    return xSemaphoreTakeRecursive(lvgl_mux, timeout_ticks) == pdTRUE;
-}
-
-void example_lvgl_unlock(void)
-{
-    xSemaphoreGiveRecursive(lvgl_mux);
-}
-
 static void example_lvgl_port_task(void *arg)
 {
     ESP_LOGI(TAG, "Starting LVGL task");
-    uint32_t task_delay_ms = EXAMPLE_LVGL_TASK_MAX_DELAY_MS;
+    uint32_t time_till_next_ms = 0;
+    uint32_t time_threshold_ms = 1000 / CONFIG_FREERTOS_HZ;
     while (1) {
-        // Lock the mutex due to the LVGL APIs are not thread-safe
-        if (example_lvgl_lock(-1)) {
-            task_delay_ms = lv_timer_handler();
-            // Release the mutex
-            example_lvgl_unlock();
-        }
-        if (task_delay_ms > EXAMPLE_LVGL_TASK_MAX_DELAY_MS) {
-            task_delay_ms = EXAMPLE_LVGL_TASK_MAX_DELAY_MS;
-        } else if (task_delay_ms < EXAMPLE_LVGL_TASK_MIN_DELAY_MS) {
-            task_delay_ms = EXAMPLE_LVGL_TASK_MIN_DELAY_MS;
-        }
-        vTaskDelay(pdMS_TO_TICKS(task_delay_ms));
+        _lock_acquire(&lvgl_api_lock);
+        time_till_next_ms = lv_timer_handler();
+        _lock_release(&lvgl_api_lock);
+        // in case of triggering a task watch dog time out
+        time_till_next_ms = MAX(time_till_next_ms, time_threshold_ms);
+        usleep(1000 * time_till_next_ms);
     }
 }
 
 void app_main(void)
 {
-    static lv_disp_draw_buf_t disp_buf; // contains internal graphic buffer(s) called draw buffer(s)
-    static lv_disp_drv_t disp_drv;      // contains callback functions
-
     ESP_LOGI(TAG, "Turn off LCD backlight");
     gpio_config_t bk_gpio_config = {
         .mode = GPIO_MODE_OUTPUT,
@@ -236,8 +198,6 @@ void app_main(void)
         .lcd_param_bits = EXAMPLE_LCD_PARAM_BITS,
         .spi_mode = 0,
         .trans_queue_depth = 10,
-        .on_color_trans_done = example_notify_lvgl_flush_ready,
-        .user_ctx = &disp_drv,
     };
     // Attach the LCD to the SPI bus
     ESP_ERROR_CHECK(esp_lcd_new_panel_io_spi((esp_lcd_spi_bus_handle_t)LCD_HOST, &io_config, &io_handle));
@@ -266,6 +226,49 @@ void app_main(void)
     // user can flush pre-defined pattern to the screen before we turn on the screen or backlight
     ESP_ERROR_CHECK(esp_lcd_panel_disp_on_off(panel_handle, true));
 
+    ESP_LOGI(TAG, "Turn on LCD backlight");
+    gpio_set_level(EXAMPLE_PIN_NUM_BK_LIGHT, EXAMPLE_LCD_BK_LIGHT_ON_LEVEL);
+
+    ESP_LOGI(TAG, "Initialize LVGL library");
+    lv_init();
+
+    // create a lvgl display
+    lv_display_t *display = lv_display_create(EXAMPLE_LCD_H_RES, EXAMPLE_LCD_V_RES);
+
+    // alloc draw buffers used by LVGL
+    // it's recommended to choose the size of the draw buffer(s) to be at least 1/10 screen sized
+    size_t draw_buffer_sz = EXAMPLE_LCD_H_RES * EXAMPLE_LVGL_DRAW_BUF_LINES * sizeof(lv_color16_t);
+
+    void *buf1 = spi_bus_dma_memory_alloc(LCD_HOST, draw_buffer_sz, 0);
+    assert(buf1);
+    void *buf2 = spi_bus_dma_memory_alloc(LCD_HOST, draw_buffer_sz, 0);
+    assert(buf2);
+    // initialize LVGL draw buffers
+    lv_display_set_buffers(display, buf1, buf2, draw_buffer_sz, LV_DISPLAY_RENDER_MODE_PARTIAL);
+    // associate the mipi panel handle to the display
+    lv_display_set_user_data(display, panel_handle);
+    // set color depth
+    lv_display_set_color_format(display, LV_COLOR_FORMAT_RGB565);
+    // set the callback which can copy the rendered image to an area of the display
+    lv_display_set_flush_cb(display, example_lvgl_flush_cb);
+
+    ESP_LOGI(TAG, "Install LVGL tick timer");
+    // Tick interface for LVGL (using esp_timer to generate 2ms periodic event)
+    const esp_timer_create_args_t lvgl_tick_timer_args = {
+        .callback = &example_increase_lvgl_tick,
+        .name = "lvgl_tick"
+    };
+    esp_timer_handle_t lvgl_tick_timer = NULL;
+    ESP_ERROR_CHECK(esp_timer_create(&lvgl_tick_timer_args, &lvgl_tick_timer));
+    ESP_ERROR_CHECK(esp_timer_start_periodic(lvgl_tick_timer, EXAMPLE_LVGL_TICK_PERIOD_MS * 1000));
+
+    ESP_LOGI(TAG, "Register io panel event callback for LVGL flush ready notification");
+    const esp_lcd_panel_io_callbacks_t cbs = {
+        .on_color_trans_done = example_notify_lvgl_flush_ready,
+    };
+    /* Register done callback */
+    ESP_ERROR_CHECK(esp_lcd_panel_io_register_event_callbacks(io_handle, &cbs, display));
+
 #if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
     esp_lcd_panel_io_handle_t tp_io_handle = NULL;
     esp_lcd_panel_io_spi_config_t tp_io_config = ESP_LCD_TOUCH_IO_SPI_STMPE610_CONFIG(EXAMPLE_PIN_NUM_TOUCH_CS);
@@ -283,68 +286,27 @@ void app_main(void)
             .mirror_y = 0,
         },
     };
+    esp_lcd_touch_handle_t tp = NULL;
 
 #if CONFIG_EXAMPLE_LCD_TOUCH_CONTROLLER_STMPE610
     ESP_LOGI(TAG, "Initialize touch controller STMPE610");
     ESP_ERROR_CHECK(esp_lcd_touch_new_spi_stmpe610(tp_io_handle, &tp_cfg, &tp));
 #endif // CONFIG_EXAMPLE_LCD_TOUCH_CONTROLLER_STMPE610
-#endif // CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
 
-    ESP_LOGI(TAG, "Turn on LCD backlight");
-    gpio_set_level(EXAMPLE_PIN_NUM_BK_LIGHT, EXAMPLE_LCD_BK_LIGHT_ON_LEVEL);
-
-    ESP_LOGI(TAG, "Initialize LVGL library");
-    lv_init();
-    // alloc draw buffers used by LVGL
-    // it's recommended to choose the size of the draw buffer(s) to be at least 1/10 screen sized
-    lv_color_t *buf1 = heap_caps_malloc(EXAMPLE_LCD_H_RES * 20 * sizeof(lv_color_t), MALLOC_CAP_DMA);
-    assert(buf1);
-    lv_color_t *buf2 = heap_caps_malloc(EXAMPLE_LCD_H_RES * 20 * sizeof(lv_color_t), MALLOC_CAP_DMA);
-    assert(buf2);
-    // initialize LVGL draw buffers
-    lv_disp_draw_buf_init(&disp_buf, buf1, buf2, EXAMPLE_LCD_H_RES * 20);
-
-    ESP_LOGI(TAG, "Register display driver to LVGL");
-    lv_disp_drv_init(&disp_drv);
-    disp_drv.hor_res = EXAMPLE_LCD_H_RES;
-    disp_drv.ver_res = EXAMPLE_LCD_V_RES;
-    disp_drv.flush_cb = example_lvgl_flush_cb;
-    disp_drv.drv_update_cb = example_lvgl_port_update_callback;
-    disp_drv.draw_buf = &disp_buf;
-    disp_drv.user_data = panel_handle;
-    lv_disp_t *disp = lv_disp_drv_register(&disp_drv);
-
-    ESP_LOGI(TAG, "Install LVGL tick timer");
-    // Tick interface for LVGL (using esp_timer to generate 2ms periodic event)
-    const esp_timer_create_args_t lvgl_tick_timer_args = {
-        .callback = &example_increase_lvgl_tick,
-        .name = "lvgl_tick"
-    };
-    esp_timer_handle_t lvgl_tick_timer = NULL;
-    ESP_ERROR_CHECK(esp_timer_create(&lvgl_tick_timer_args, &lvgl_tick_timer));
-    ESP_ERROR_CHECK(esp_timer_start_periodic(lvgl_tick_timer, EXAMPLE_LVGL_TICK_PERIOD_MS * 1000));
-
-#if CONFIG_EXAMPLE_LCD_TOUCH_ENABLED
-    static lv_indev_drv_t indev_drv;    // Input device driver (Touch)
-    lv_indev_drv_init(&indev_drv);
-    indev_drv.type = LV_INDEV_TYPE_POINTER;
-    indev_drv.disp = disp;
-    indev_drv.read_cb = example_lvgl_touch_cb;
-    indev_drv.user_data = tp;
-
-    lv_indev_drv_register(&indev_drv);
+    static lv_indev_t *indev;
+    indev = lv_indev_create();  // Input device driver (Touch)
+    lv_indev_set_type(indev, LV_INDEV_TYPE_POINTER);
+    lv_indev_set_display(indev, display);
+    lv_indev_set_user_data(indev, tp);
+    lv_indev_set_read_cb(indev, example_lvgl_touch_cb);
 #endif
 
-    lvgl_mux = xSemaphoreCreateRecursiveMutex();
-    assert(lvgl_mux);
     ESP_LOGI(TAG, "Create LVGL task");
     xTaskCreate(example_lvgl_port_task, "LVGL", EXAMPLE_LVGL_TASK_STACK_SIZE, NULL, EXAMPLE_LVGL_TASK_PRIORITY, NULL);
 
     ESP_LOGI(TAG, "Display LVGL Meter Widget");
     // Lock the mutex due to the LVGL APIs are not thread-safe
-    if (example_lvgl_lock(-1)) {
-        example_lvgl_demo_ui(disp);
-        // Release the mutex
-        example_lvgl_unlock();
-    }
+    _lock_acquire(&lvgl_api_lock);
+    example_lvgl_demo_ui(display);
+    _lock_release(&lvgl_api_lock);
 }

examples/peripherals/lcd/spi_lcd_touch/sdkconfig.defaults

@@ -1,3 +1,3 @@
-CONFIG_LV_USE_USER_DATA=y
-CONFIG_LV_COLOR_16_SWAP=y
-CONFIG_LV_COLOR_DEPTH_16=y
+CONFIG_LV_CONF_SKIP=y
+CONFIG_LV_USE_OBSERVER=y
+CONFIG_LV_USE_SYSMON=y

examples/peripherals/usb/device/tusb_composite_msc_serialdevice/pytest_usb_device_composite.py

@@ -11,7 +11,7 @@ from serial.tools.list_ports import comports
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='lack of runners with usb_device tag')
+@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag')
 @pytest.mark.usb_device
 def test_usb_composite_device_serial_example(dut: Dut) -> None:
     dut.expect_exact('Hello World!')

examples/peripherals/usb/device/tusb_console/pytest_usb_device_console.py

@@ -11,7 +11,7 @@ from serial.tools.list_ports import comports
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='lack of runners with usb_device tag')
+@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag')
 @pytest.mark.usb_device
 def test_usb_device_console_example(dut: Dut) -> None:
     dut.expect_exact('USB initialization DONE')

examples/peripherals/usb/device/tusb_hid/pytest_usb_device_hid.py

@@ -7,7 +7,7 @@ from pytest_embedded import Dut
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='lack of runners with usb_device tag')
+@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag')
 @pytest.mark.usb_device
 def test_usb_device_hid_example(dut: Dut) -> None:
     dut.expect_exact('USB initialization DONE')

examples/peripherals/usb/device/tusb_midi/pytest_usb_device_midi.py

@@ -7,7 +7,7 @@ from pytest_embedded import Dut
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='lack of runners with usb_device tag')
+@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag')
 @pytest.mark.usb_device
 def test_usb_device_midi_example(dut: Dut) -> None:
     dut.expect_exact('USB initialization DONE')

examples/peripherals/usb/device/tusb_msc/main/tusb_msc_main.c

@@ -5,7 +5,7 @@
  */
 
 /* DESCRIPTION:
- * This example contains code to make ESP32-S3 based device recognizable by USB-hosts as a USB Mass Storage Device.
+ * This example contains code to make ESP32 based device recognizable by USB-hosts as a USB Mass Storage Device.
  * It either allows the embedded application i.e. example to access the partition or Host PC accesses the partition over USB MSC.
  * They can't be allowed to access the partition at the same time.
  * For different scenarios and behaviour, Refer to README of this example.
@@ -13,6 +13,7 @@
 
 #include <errno.h>
 #include <dirent.h>
+#include <stdlib.h>
 #include "esp_console.h"
 #include "esp_check.h"
 #include "esp_partition.h"
@@ -24,7 +25,19 @@
 #include "diskio_sdmmc.h"
 #endif
 
+/*
+ * We warn if a secondary serial console is enabled. A secondary serial console is always output-only and
+ * hence not very useful for interactive console applications. If you encounter this warning, consider disabling
+ * the secondary serial console in menuconfig unless you know what you are doing.
+ */
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+#if !CONFIG_ESP_CONSOLE_SECONDARY_NONE
+#warning "A secondary serial console is not useful when using the console component. Please disable it in menuconfig."
+#endif
+#endif
+
 static const char *TAG = "example_main";
+static esp_console_repl_t *repl = NULL;
 
 /* TinyUSB descriptors
    ********************************************************************* */
@@ -255,8 +268,9 @@ static int console_exit(int argc, char **argv)
 {
     tinyusb_msc_unregister_callback(TINYUSB_MSC_EVENT_MOUNT_CHANGED);
     tinyusb_msc_storage_deinit();
-    printf("Application Exiting\n");
-    exit(0);
+    tinyusb_driver_uninstall();
+    printf("Application Exit\n");
+    repl->del(repl);
     return 0;
 }
 
@@ -407,18 +421,30 @@ void app_main(void)
     ESP_ERROR_CHECK(tinyusb_driver_install(&tusb_cfg));
     ESP_LOGI(TAG, "USB MSC initialization DONE");
 
-    esp_console_repl_t *repl = NULL;
     esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT();
     /* Prompt to be printed before each line.
      * This can be customized, made dynamic, etc.
      */
     repl_config.prompt = PROMPT_STR ">";
     repl_config.max_cmdline_length = 64;
-    esp_console_register_help_command();
+
+    // Init console based on menuconfig settings
+#if defined(CONFIG_ESP_CONSOLE_UART_DEFAULT) || defined(CONFIG_ESP_CONSOLE_UART_CUSTOM)
     esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT();
     ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl));
+
+    // USJ console can be set only on esp32p4, having separate USB PHYs for USB_OTG and USJ
+#elif defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) && defined(CONFIG_IDF_TARGET_ESP32P4)
+    esp_console_dev_usb_serial_jtag_config_t hw_config = ESP_CONSOLE_DEV_USB_SERIAL_JTAG_CONFIG_DEFAULT();
+    ESP_ERROR_CHECK(esp_console_new_repl_usb_serial_jtag(&hw_config, &repl_config, &repl));
+
+#else
+#error Unsupported console type
+#endif
+
     for (int count = 0; count < sizeof(cmds) / sizeof(esp_console_cmd_t); count++) {
         ESP_ERROR_CHECK(esp_console_cmd_register(&cmds[count]));
     }
+
     ESP_ERROR_CHECK(esp_console_start_repl(repl));
 }

examples/peripherals/usb/device/tusb_msc/pytest_usb_device_msc.py

@@ -7,7 +7,7 @@ from pytest_embedded import Dut
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32p4'], reason='lack of runners with usb_device tag')
+@pytest.mark.temp_skip_ci(targets=['esp32s3'], reason='lack of runners with usb_device tag')
 @pytest.mark.usb_device
 def test_usb_device_msc_example(dut: Dut) -> None:
     dut.expect('Mount storage')