The previously used splits between memory allocated for ROM code,
2nd stage bootloader and the app were somewhat safe and conservative.
This resulted in some space being unavailable for static allocation
in the app.
This commit increases the space available for static allocation to the
maximum possible amount.
1. Some of the ROM code static allocation is only used in UART/USB/SPI
download modes. This region ("shared buffers") has been placed at
the lower end of ROM memory area, to be reusable in flash boot
mode. The 2nd stage bootloader linker script is modified to "pack"
all sections exactly up to the end but with roughly 8K margin between
startup stacks.
2. Instead of calculating the sections placement and hardcoding the
addresses in the LD script again, rewrite it to calculate the
start address of each memory region automatically based on the
logic above.
3. Adjust the app memory layout (SRAM_IRAM_END) accordingly,
increasing the space available for static allocation.
Overall these changes increase the space available for static
allocation by about 78kB.
The downside of these changes is that the 2nd stage bootloader .data
segment is now directly adjacent to the startup stack on the PRO CPU.
Previously, there was effectively about 78kB of extra stack space for
the PRO CPU, before the stack would run into the data segment.
ESP32H2 doesn't support access to RTC memory through various buses, thus .rtc.dummy section
makes no sense here. The section is used for blind padding in LD script - to provide proper section offsets)
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.
This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
This bugfix contains 3 fixes:
1. .rtc_dummy section is removed (not needed for C3)
2. .rtc_text section is padded with 16B for possible CPU prefetch
3. .rtc_text section is aligned to 4B boundary to comply with PMS Memprot requirements
PMS aware chips require prefetch padding size for instruction fetch, or
some memory alignment considerations. These settings are now exposed
through kconfig options (hidden) and used through common ld template.
This shall help to add and manage future chips support easily for
these considerations.
Closes IDF-3624
Add Kconfig option SPIRAM_ALLOW_NOINIT_EXTERNAL_MEMORY
When enabled, a new linker script rule (from esp32.extram.noinit.ld)
places any variables in the .ext_ram.noinit section in SPIRAM.
This section is exempted from the startup SPIRAM memory test and is
not zero-initialized or added to the malloc pool, making it usable
for noinit variables that persist across reset.
The EXT_RAM_NOINIT_ATTR macro places variables in this section.
IRAM section didn't contain sufficient padding for possible CPU instruction prefetch,
ie instruction fetch could happen in DRAM section which is prohibited by the Memprot module.
This is fixed by adding 16B to the end of IRAM section in LD script (C3 CPU prefetch buffer depth is 4 words)
Closes IDF-3554
* fix
