Michael (XIAO Xufeng)
d7d1dee208
system: reset dma when soft reset
2021-01-25 04:51:40 +00:00
Angus Gratton
fe8a891de9
Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master'
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bootloader/esp32c3: Support secure boot
Closes IDF-2115
See merge request espressif/esp-idf!11797
2021-01-21 08:42:49 +08:00
KonstantinKondrashov
88c5fe49b8
soc: Adds a soc_caps define for all chips to define the number of boot key digests
2021-01-19 20:51:13 +08:00
Li Shuai
aa7fd175b9
light sleep: light sleep support for esp32c3
2021-01-19 14:50:58 +08:00
ninh
27aa6c289f
components/pm: Add slp gpio configure workaround
2021-01-15 15:34:45 +08:00
Marius Vikhammer
eb788deb03
esp_hw_support: merge C3 changes to master
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Merge RTC related C3 changes to master
2020-12-30 12:20:41 +08:00
Marius Vikhammer
0a95151a75
unit_test: Refactor all performance tests that rely on cache compensated timer
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There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.
This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
2020-12-22 18:56:24 +11:00
Marius Vikhammer
457ce080ae
AES: refactor and add HAL layer
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Refactor the AES driver and add HAL, LL and caps.
Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Angus Gratton
c29d93986d
soc: Add initial ESP32-C3 support
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From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
Armando
fb8b905539
uart: add uart support on esp32s3
2020-11-24 19:12:51 +08:00
Michael (XIAO Xufeng)
14944b181e
Merge branch 'fix/soc_caps_spi_dummy_output_esp32' into 'master'
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soc_caps.h: remove spi cap that is defined to 0
See merge request espressif/esp-idf!11203
2020-11-16 10:39:27 +08:00
Michael (XIAO Xufeng)
099fca515d
Merge branch 'bugfix/move_crypto_caps' into 'master'
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SHA/RSA: moved all caps to soc_caps.h
Closes IDF-2300
See merge request espressif/esp-idf!11032
2020-11-13 11:06:44 +08:00
Angus Gratton
935e4b4d62
Merge branch 'feature/riscv_arch' into 'master'
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Add RISC-V support
Closes IDF-2359
See merge request espressif/esp-idf!11140
2020-11-13 07:50:31 +08:00
Angus Gratton
420aef1ffe
Updates for riscv support
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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
longer signed/unsigned int).
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
Cao Sen Miao
6eee601cf6
i2c: Add supports on esp32s3
2020-11-12 11:32:45 +08:00
Michael (XIAO Xufeng)
5b6c965e99
soc_caps.h: remove spi cap that is defined to 0
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According to the caps rule, for unsupported feature we don't define anything.
Remove the define 0 that violates this rule.
2020-11-12 10:29:42 +08:00
Marius Vikhammer
488f46acf5
SHA/RSA: moved all caps to soc_caps.h
2020-11-12 02:15:46 +00:00
morris
ff976867b3
rmt: split TX and RX in LL driver
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Split TX and RX function in LL driver.
Channel number is encoded in driver layer.
Added channel signal list in periph.c
2020-11-05 19:00:55 +08:00
chenjianqiang
9465af0066
rmt: support esp32s3
2020-11-05 19:00:55 +08:00
morris
e4c8ec6174
timergroup: move interrupt index into peripheral description file
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1. Added timer_group_periph.c file, describing module global signals
(e.g. interrupt index)
2. Added more caps in soc_caps.h
2020-11-03 18:16:50 +08:00
Michael (XIAO Xufeng)
35faecea1d
Merge branch 'feature/support_sigma_delta_on_s3' into 'master'
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sigma_delta: add periph signal list and support esp32-s3
See merge request espressif/esp-idf!10945
2020-10-30 17:22:02 +08:00
Michael (XIAO Xufeng)
3bacf35310
esp_flash: support high capacity flash chips (32-bit address)
2020-10-29 18:20:11 +08:00
morris
17808b3ff8
sigma_delta: add periph signal list and support esp32-s3
2020-10-29 11:06:28 +08:00
Renz Bagaporo
79887fdc6c
soc: descriptive part occupy whole component
2020-10-28 07:21:29 +08:00
Renz Christian Bagaporo
1f2e2fe8af
soc: separate abstraction, description and implementation
2020-02-11 14:30:42 +05:00
Darian Leung
a049e02d96
can: Refactor CAN to use HAL and LowLevel layers
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The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:
- Added bit field members to can_message_t as alternative
to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
2020-01-09 16:13:51 +08:00
michael
f676a3b190
driver, soc: update multichip support headers
2020-01-06 17:13:54 +08:00
Michael (XIAO Xufeng)
05739798c3
soc: s2beta support
2019-09-04 10:53:25 +10:00