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14944b181e
soc_caps.h: remove spi cap that is defined to 0 See merge request espressif/esp-idf!11203
259 lines
11 KiB
C
259 lines
11 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* Soc capabilities file, describing the following chip attributes:
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* - Peripheral or feature supported or not
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* - Number of resources (peripheral, channel, etc.)
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* - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
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* supported, etc.
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*
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* For boolean definitions:
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* - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
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* (`#define` blank string causes error when checking by `#if x`)
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* - if false: not define anything at all.
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* (`#ifdef x` is true even when `#define 0` is defined before.)
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*
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* The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
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* (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
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* x 0`, it's still a risk.)
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*
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* ECO & exceptions:
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* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
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* `#if x` and `#if !x`, making these missing definitions more obvious.
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*/
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#pragma once
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#ifdef __has_include
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# if __has_include("sdkconfig.h")
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# include "sdkconfig.h"
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# define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN
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# endif
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#endif
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#if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER)
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#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
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#endif
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#ifndef SOC_CAPS_ECO_VER
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#warning ECO version not determined. Some ECO related caps will not be available.
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#warning Define SOC_CAPS_ECO_VER before including this header.
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// Define warning strings here for ECO-ed features to show error when they are used without being
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// defined correctly
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#define SOC_BROWNOUT_RESET_SUPPORTED "Not determined"
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#define SOC_TWAI_BRP_DIV_SUPPORTED "Not determined"
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#endif
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_CAPS_ECO_VER_MAX 3
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#define SOC_MCPWM_SUPPORTED 1
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#define SOC_SDMMC_HOST_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_PCNT_SUPPORTED 1
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#define SOC_SDIO_SLAVE_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_EMAC_SUPPORTED 1
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#define SOC_RISCV_COPROC_SUPPORTED 0 //TODO: correct the caller and remove this line
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#define SOC_CPU_CORES_NUM 2
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/*-------------------------- ADC CAPS ----------------------------------------*/
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_PATT_LEN_MAX (16)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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/**
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* Check if adc support digital controller (DMA) mode.
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* @value
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* - 1 : support;
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* - 0 : not support;
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*/
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#if SOC_CAPS_ECO_VER >= 1
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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#endif
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_BREAKPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
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/*-------------------------- DAC CAPS ----------------------------------------*/
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#define SOC_DAC_PERIPH_NUM 2
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#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1)
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#define SOC_GPIO_PIN_COUNT 40
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// SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must
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// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
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// control pullup/down/capability, independent with RTC registers.
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// 0~39 except from 20, 24, 28~31 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
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// GPIO >= 34 are input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32 have 2 I2C.
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#define SOC_I2C_NUM (2)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_APB (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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// ESP32 have 2 I2S
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#define SOC_I2S_NUM (2)
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#define SOC_I2S_SUPPORTS_PDM (1) // ESP32 support PDM
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#define SOC_I2S_SUPPORTS_ADC_DAC (1) // ESP32 support ADC and DAC
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#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
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#define SOC_I2S_APLL_MIN_FREQ (250000000)
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#define SOC_I2S_APLL_MAX_FREQ (500000000)
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#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_SUPPORT_HS_MODE (1)
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#define SOC_LEDC_SUPPORT_HS_MODE (1)
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#define SOC_LEDC_CHANNEL_NUM (8)
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#define SOC_LEDC_TIMER_BIT_WIDE_NUM (20)
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/*-------------------------- MCPWM CAPS --------------------------------------*/
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#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number
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#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has
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#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has
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#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has
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#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has
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#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has
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/*-------------------------- MPU CAPS ----------------------------------------*/
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//TODO: correct the caller and remove unsupported lines
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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/*-------------------------- PCNT CAPS ---------------------------------------*/
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// ESP32 have 1 PCNT peripheral
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#define SOC_PCNT_PORT_NUM (1)
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#define SOC_PCNT_UNIT_NUM (8)
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#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
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/*-------------------------- RMT CAPS ----------------------------------------*/
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#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
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#define SOC_RMT_TX_CHANNELS_NUM (8) /*!< Number of channels that capable of Transmit */
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#define SOC_RMT_RX_CHANNELS_NUM (8) /*!< Number of channels that capable of Receive */
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#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels (each channel can be configured to either TX or RX) */
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#define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */
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#define SOC_RMT_SOURCE_CLK_INDEPENDENT (1) /*!< Can select different source clock for channels */
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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#define SOC_RTCIO_PIN_COUNT 18
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/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
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#define SOC_SIGMADELTA_NUM 1
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#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 3
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#define SOC_SPI_DMA_CHAN_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 3
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
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/*-------------------------- TIMER GROUP CAPS --------------------------------*/
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#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
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#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
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#define SOC_TIMER_GROUPS (2)
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#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
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#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
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#define SOC_TIMER_GROUP_LAYOUT {2,2}
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_SENSOR_NUM (10)
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#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
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#define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
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/*-------------------------- TWAI CAPS ---------------------------------------*/
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#define SOC_TWAI_BRP_MIN 2
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#define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1
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#define SOC_TWAI_BRP_MAX_ECO0 128
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//Any even number from 2 to 128
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#define SOC_TWAI_BRP_IS_VALID_ECO0(brp) ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0)
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#define SOC_TWAI_BRP_MAX_ECO 256
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//Any even number from 2 to 128, or multiples of 4 from 132 to 256
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#define SOC_TWAI_BRP_IS_VALID_ECO(brp) (((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) || ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0))
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#if SOC_CAPS_ECO_VER >= 2
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# define SOC_TWAI_BRP_DIV_SUPPORTED 1
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# define SOC_TWAI_BRP_DIV_THRESH 128
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# define SOC_TWAI_BRP_IS_VALID SOC_TWAI_BRP_IS_VALID_ECO
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# define SOC_TWAI_BRP_MAX SOC_TWAI_BRP_MAX_ECO
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#else
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# define SOC_TWAI_BRP_IS_VALID SOC_TWAI_BRP_IS_VALID_ECO0
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# define SOC_TWAI_BRP_MAX SOC_TWAI_BRP_MAX_ECO0
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#endif
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32 have 3 UART.
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#define SOC_UART_NUM (3)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (4096)
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/* ---------------------------- Compatibility ------------------------------- */
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#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED
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#define CAN_BRP_MIN SOC_TWAI_BRP_MIN
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#define CAN_BRP_MAX SOC_TWAI_BRP_MAX
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#define CAN_BRP_DIV_THRESH SOC_TWAI_BRP_DIV_THRESH
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#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
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