- Added LL cap macros to distinguish feature differences between the LLs of
different targets:
- '..._LL_EXT_PHY_SUPPORTED' indicates whether the USB WRAP/USJ supports
routing to an external FSLS PHY.
- Added 'usb_wrap_types.h' and 'usb_serial_jtag_types.h' to provide types used
in LLs.
- Fixed some spelling/naming issues as part of code-spell pre-commit
This commit rewrite the 'usb_wrap_ll.h' API as follows:
- All APIs renamed from 'usb_fsls_phy_ll_...()' to 'usb_wrap_ll_...()'
- APIs now match their equivalent counter parts in 'usb_serial_jtag_ll.h'
For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.
This commit does the following:
- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
This commit renames USB PHY related HAL files from "usb_phy_xxx" to
"usb_fsls_phy_xxx" since they are only designed to support Full-Speed/Low-Speed
Serial USB PHYs. This renmaing is done to accommodate future USB PHYs that use
other PHY interfaces (e.g., UTMI, ULPI etc).
There are a bunch of cases you might want some pins not exposed.
Eg.
* Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins
* Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing).
* Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins.
Removing this validation makes these cases work.
Merges https://github.com/espressif/esp-idf/pull/13103
fix(esp_pm): fix psram access failed after pd_cpu wakeup if uart driver driven console is used (backport v5.1)
See merge request espressif/esp-idf!27051
Each MCPWM operator has two Trigger (named T0 and T1), and they can be
routed to GPIO fault signal or timer sync event.Generator can be set up
to perform different action on Trigger event.
This commit add a trigger driver and a test for the driver.
MCPWM group clock pre scale was originally fixed to 2, which is
inconvenient. Set group clock prescale dynamically. Now the maximum
resolution of the MCPWM timer is up to 160MHz(when the prescale set
to 1). And add a resulotion config for MCPWM capture.
The MCPWM carrier is part of the operator and can work independently
without the MCPWM timer being enabled. This commit add the MCPWM
carrier clk source.
since the linker placement of the hal functions are controlled by the Kconfig in the driver component,
we should create the linker.lf in the driver component, not in the hal component.
