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fix(esp_pm): fix psram access faild after pd_cpu wakeup
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@ -437,8 +437,11 @@ esp_err_t esp_pm_configure(const void* vconfig)
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min_freq_mhz,
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config->light_sleep_enable ? "ENABLED" : "DISABLED");
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portENTER_CRITICAL(&s_switch_lock);
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// CPU & Modem power down initialization, which must be initialized before s_light_sleep_en set true,
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// to avoid entering idle and sleep in this function.
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esp_pm_sleep_configure(config);
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portENTER_CRITICAL(&s_switch_lock);
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bool res __attribute__((unused));
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res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]);
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assert(res);
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@ -451,8 +454,6 @@ esp_err_t esp_pm_configure(const void* vconfig)
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s_config_changed = true;
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portEXIT_CRITICAL(&s_switch_lock);
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esp_pm_sleep_configure(config);
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return ESP_OK;
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -68,6 +68,14 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr)
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);
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rtc_cntl_ll_enable_cpu_retention_clock();
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rtc_cntl_ll_enable_cpu_retention();
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#if SOC_PM_SUPPORT_TAGMEM_PD
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if (!retent->tagmem.dcache.enable) {
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// Here we only need to care for the safety of the PSRAM data in the DCache.
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// Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be
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// modified in the sleep process code after now, so it is safe to writeback here.
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Cache_WriteBack_All();
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}
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#endif
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}
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}
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}
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