Commit Graph

107 Commits

Author SHA1 Message Date
jingli
b85e5627d3 esp_hw_support/clk_cali: remove redundant check for cali value 2022-09-21 16:30:17 +08:00
wangmengyang
580b57c8b1 component/bt: reset Bluetooth hardware during controller inititalization on ESP32-C3
1. Rename MACROs SYSTEM_WIFI_RST_EN register bit fields to be more recognizable
2. reset Bluetooth baseband and MAC bits to fix the issue of task watchdog triggered during controller initialization due to invalid hardware state
2022-07-13 17:35:22 +08:00
Ivan Grokhotkov
95dbc746ed esp_system: fix garbled UART output on startup on esp32s2
Closes https://github.com/espressif/esp-idf/issues/9168
2022-07-11 02:41:46 +00:00
KonstantinKondrashov
714bc66e0e efuse: Checks errors of 4x coding scheme for BLOCK0 if so then abort 2022-06-22 18:04:11 +08:00
KonstantinKondrashov
0a71dce1ef reset_reasons: EFUSE_RST is treated as POWERON_RST
ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
2022-06-22 17:56:32 +08:00
Alexey Gerenkov
d06fac5c8b apptrace: Adds ESP32-C3 support 2022-05-13 16:23:46 +03:00
Konstantin Kondrashov
fa85714845 Systimer reset alternative on S2 (and others) (v4.3) 2021-10-28 08:00:28 +00:00
Mahavir Jain
28f8ac5f12 cpu_start: rename function to add core prefix for more clarity 2021-10-21 08:09:14 +05:30
Mahavir Jain
76e606ab32 cpu_start: let individual core clear its interrupt matrix
There was race condition where interrupt entries set by APP cpu core
could have been cleared during PRO cpu startup.

This was causing "cache access error" not being detected for ESP32 APP
CPU core.

This fix allows to NOT modify or clear any entries set by other core
(APP or PRO) and thus avoiding any race conditions during startup code.
2021-10-21 08:03:55 +05:30
Song Ruo Jing
75916a8758 Merge branch 'bugfix/cpu_reset_perip_clk_disable_v4.3' into 'release/v4.3'
esp_system: Peripheral clocks faulty become disabled during cpu reset

See merge request espressif/esp-idf!15482
2021-10-13 10:04:13 +00:00
songruojing
023bbe5cb1 esp_system: fix the bug that some peripheral clocks are being disabled during cpu reset for esp32s2, c3, s3 2021-10-12 11:37:17 +08:00
Cao Sen Miao
ea06ee1ad6 spi_flash: move the unlock patch to bootloader and add support for GD 2021-10-11 10:52:52 +08:00
Martin Vychodil
ec6745a137 System/Security: wrong check of the Memprot feature in esp_restart()/panic_restart()
esp_restart()/panic_restart() never resets the Digital system (so far required only by the Memprot feature) as there's a typo in the corresponding #define:
it checks CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE instead of CONFIG_ESP_SYSTEM_MEMPROT_FEATURE.
Issue fixed.

IDF-4094
2021-10-05 11:58:31 +02:00
Jiang Jiang Jian
3908360e46 Merge branch 'feature/support_bss_in_psram_for_esp32s2_v4.3' into 'release/v4.3'
[system] Allow .bss segment placed in external memory for ESP32-S2 ( backport v4.3)

See merge request espressif/esp-idf!14946
2021-09-15 08:09:42 +00:00
Wu Zheng Hui
4fd6d3deae Adjust the variable name &
Add mapping support for different sizes of spi ram
2021-09-15 16:09:33 +08:00
David Čermák
51f1bc3ced Merge branch 'bugfix/cmake_compiler_warn_write_string_v4.3' into 'release/v4.3'
Build: Fix CMake to pass -Wwrite-string compiler flag if enabled (v4.3)

See merge request espressif/esp-idf!14426
2021-09-09 09:49:33 +00:00
Marius Vikhammer
e741161b2e Merge branch 'bugfix/renable_unit_tests_v4.3' into 'release/v4.3'
ci: enable previously disabled unit tests (v4.3)

See merge request espressif/esp-idf!13775
2021-09-08 09:03:32 +00:00
David Cermak
dd1de21216 panic/memprot: Fix minor const string correction on panic print 2021-08-18 19:29:44 +08:00
Martin Vychodil
b04705cfe2 system/security: Memprot bypassing mitigation
Check Memprot lock bit(s) during the system startup, abort/reset on any Memprot parts found locked during this phase.
There is no legal reason to disallow the Memprot configuration by the system, so it's either a critical bug in the
application or an malicious attempt to bypass the system security.
Error message is printed before digital system reset.

Closes IDF-2700
2021-08-02 12:18:46 +02:00
Renz Bagaporo
b07276265a esp32s2: reset systimer clk on startup 2021-07-30 10:13:46 +08:00
Angus Gratton
1fc288556c esp_system: Reconfigure the WDTs at the start of the panic handler
This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.
2021-07-06 09:59:39 +08:00
Michael (XIAO Xufeng)
2bffeb7265 uart: fix misleading files for UART2
Includes: header files, ld files and clk.c

ESP32-C3 only have UART0 and UART1.
2021-04-29 14:23:13 +08:00
Shu Chen
42ae0166d7 esp32c3: fix typos of c3 path 2021-04-23 21:09:06 +08:00
Martin Vychodil
6dfff2fdbd esp32c3: memprot API upgrade and test application
Closes IDF-2641
2021-04-12 10:21:58 +10:00
Cao Sen Miao
198d350fe5 esp_system: support gpio wakeup from deep sleep on esp32c3 2021-02-26 17:08:22 +08:00
Angus Gratton
dfda84c2ab esp_system: Fix some ESP_EARLY_LOG lines not being output fully
At least on ESP32, calling esp_rom_uart_set_clock_baudrate() causes the
contents of the UART FIFO to be discarded.
2021-02-01 14:24:38 +11:00
Ivan Grokhotkov
9a20283485 Merge branch 'bugfix/scan_test_missing_build_apps_without_tests' into 'master'
ci: bugfix: scan_test missing build apps without tests

See merge request espressif/esp-idf!12138
2021-01-28 17:48:24 +08:00
Martin Vychodil
69096ddce5 Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)

Closes https://jira.espressif.com:8443/browse/IDF-2092
2021-01-27 08:44:03 +01:00
Fu Hanxi
e4e375f488 fix: add spi_flash.h for s2, s3, c3 targets in cpu_start.c
update s2, s3, c3 ld files spi_flash_attach to esp_rom_spiflash_attach
2021-01-27 12:35:49 +08:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
Chen Jian Xing
f71adec8fb Support ESP32S3 (beta2) WiFi 2021-01-25 00:18:42 +08:00
Angus Gratton
5938b9a892 Merge branch 'feature/support_esp32c3_master_cmake_reset_reason' into 'master'
esp32c3: Add UTs for reset_reason

Closes IDF-2091

See merge request espressif/esp-idf!11546
2021-01-18 07:12:21 +08:00
Konstantin Kondrashov
d23c7690f2 esp32c3: Add UTs for reset_reason 2021-01-18 07:12:21 +08:00
Michael (XIAO Xufeng)
2d3f22918f Merge branch 'feature/gdma_channel_allocator' into 'master'
gdma channel allocator

Closes IDF-2124

See merge request espressif/esp-idf!11570
2021-01-14 10:52:49 +08:00
Angus Gratton
f683db7aea Merge branch 'feature/c3_IDF-2554' into 'master'
global: Uses CCOUNT API instead of XTHAL macro

Closes IDF-2554

See merge request espressif/esp-idf!11954
2021-01-13 12:55:21 +08:00
morris
40a6a0fac6 async_mcp: apply gdma driver 2021-01-13 10:52:27 +08:00
KonstantinKondrashov
dada7cd035 global: Uses CCOUNT API instead of XTHAL macro 2021-01-12 16:24:23 +08:00
morris
753a929525 global: fix sign-compare warnings 2021-01-12 14:05:08 +08:00
Chen Jian Xing
5b44295cb9 esp_wifi: fix esp32c3 code issues
1. enable wifi clk and rm dport header
2.syn phy_init_data.h from esp32
2021-01-10 16:16:28 +08:00
Omar Chebib
c218f669ba panic on RISC-V: Take into account Merge Request comments 2020-12-31 15:46:17 +08:00
Ivan Grokhotkov
5962b1dc56 panic: print register dump on abort for RISC-V
Register values are necessary to perform host-side backtracing on
RISC-V. Print them in case of an abort as well.
2020-12-31 15:46:17 +08:00
Omar Chebib
b6a450f824 panic: Add support for SoC-level panic
SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
2020-12-31 15:46:17 +08:00
Angus Gratton
61c77d9212 esp_system: Add port-specific esp32c3 files 2020-12-24 13:40:01 +11:00
Angus Gratton
55155c3f82 esp_system: Rename _init_start symbol to _vector_table 2020-12-24 13:40:01 +11:00
Angus Gratton
cfbded2ea1 esp_system: Add extra MMU config step for ESP32-C3 2020-12-24 13:40:01 +11:00
Angus Gratton
a5aac93051 esp_rom: Small changes for esp32c3 support
Updated from internal commit 6d894813
2020-12-24 13:40:01 +11:00
morris
c39476d699 esp_rom: added esp_rom_install_uart_printf 2020-12-11 11:45:10 +08:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Renz Bagaporo
4cc6b5571b esp_system: support riscv panic 2020-11-13 07:49:11 +11:00
Angus Gratton
420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00