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esp_system: fix the bug that some peripheral clocks are being disabled during cpu reset for esp32s2, c3, s3

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This commit is contained in:
songruojing 2021-10-12 11:37:17 +08:00
parent ba15ac8634
commit 023bbe5cb1
5 changed files with 16 additions and 14 deletions
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4
components/esp_rom/include/esp32c3/rom/rtc.h
View File

@ -93,8 +93,8 @@ typedef enum {
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<11, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
} RESET_REASON;
typedef enum {

4
components/esp_system/port/soc/esp32/clk.c
View File

@ -225,9 +225,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET)
if ((rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == SW_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == SW_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET)
#endif
) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);

9
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -223,12 +223,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
if ((rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == RTC_SW_CPU_RESET ||
rst_reas[0] == RTCWDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] == TG0WDT_CPU_RESET || rst_reas[1] == RTC_SW_CPU_RESET ||
rst_reas[1] == RTCWDT_CPU_RESET || rst_reas[1] == TG1WDT_CPU_RESET)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);

7
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -219,9 +219,10 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reas[0] >= TG0WDT_CPU_RESET &&
rst_reas[0] <= TG0WDT_CPU_RESET &&
rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
if (rst_reas[0] == TG0WDT_CPU_RESET ||
rst_reas[0] == RTC_SW_CPU_RESET ||
rst_reas[0] == RTCWDT_CPU_RESET ||
rst_reas[0] == TG1WDT_CPU_RESET) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);

6
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -221,9 +221,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
if ((rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == RTC_SW_CPU_RESET ||
rst_reas[0] == RTCWDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] == TG0WDT_CPU_RESET || rst_reas[1] == RTC_SW_CPU_RESET ||
rst_reas[1] == RTCWDT_CPU_RESET || rst_reas[1] == TG1WDT_CPU_RESET)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);