Commit Graph

41 Commits

Author SHA1 Message Date
Xiao Xufeng
ca3d871a21 bootloader: fixed super watchdog not enabled issue on C3, S3, H4 2023-04-24 11:32:23 +08:00
Mahavir Jain
f22daec784 Merge branch 'feature/secure_set_efuses_to_prevent_brick_chip' into 'master'
security: write-protect DIS_ICAHE and DIS_DCACHE

Closes IDF-5177

See merge request espressif/esp-idf!22640
2023-03-29 11:51:09 +08:00
KonstantinKondrashov
a3232e4a5b bootloader: Adds an option to leave DIS_CACHE writeable 2023-03-29 00:02:25 +08:00
KonstantinKondrashov
723b2e86e5 security: write-protect DIS_ICAHE and DIS_DCACHE
Closes IDF-5177
2023-03-29 00:02:24 +08:00
Zim Kalinowski
7c090d9a42 Merge branch 'bugfix/bootloader-ignored-warnings' into 'master'
bootloader: fix and re-enable no-format warnings

Closes IDF-6789

See merge request espressif/esp-idf!22715
2023-03-16 19:57:58 +08:00
Armando
bae6680207 mmu: hal function to init, and hal function to unmap all 2023-03-15 10:59:20 +08:00
Armando
929b7717ff system: fixed ram app cannot use mmu correctly issue 2023-03-15 10:59:20 +08:00
Zim Kalinowski
f6453b7938 bootloader: fix and re-enable no-format warnings 2023-03-15 00:28:31 +01:00
wuzhenghui
c0d2fcded7 refactor: move bootloader_init_spi_flash to bootloader_flash_config_{target}.c 2023-02-01 17:57:28 +08:00
wuzhenghui
44df5b31af feature: add ram loadable app support 2023-02-01 17:57:22 +08:00
Cao Sen Miao
2c9bb4eb7d spi_flash: Support select flash mode automatically at run time(Quad flash or Octal flash) 2022-10-18 11:25:35 +08:00
Cao Sen Miao
ec6a56ed0c spi_flash: re-enable the HPM mode on several XMC chips 2022-07-22 09:54:56 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
2022-06-14 14:40:03 +08:00
Wu Zheng Hui
b98622c624 efuse: update efuse name 2022-05-28 22:03:16 +08:00
Cao Sen Miao
4418a855ba spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2 2022-04-26 15:22:37 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
rudi ;-)
f242a1705a
add support for Flash 32MB..128MB (S2, S3)
ESP32-S2 and ESP32-S3
supports up to 1 GB of external flash and RAM
add support for
-    32MB
-    64MB
-    128MB ( example NOR spiFLASH 1G-BIT W25Q01JVZEIQ Winbond 0xEF 0x40 0x21 )

Merges https://github.com/espressif/esp-idf/pull/7688

Signed-off-by: Ivan Grokhotkov <ivan@espressif.com>
2022-02-21 10:26:41 +03:00
Cao Sen Miao
3dd1cfea18 spi_flash: refactor spi_flash.h to decline duplicated code 2021-12-30 14:05:12 +08:00
Sudeep Mohanty
e22b4007d3 esp_hw_support: Removed deprecated CPU util functions
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h

The following functions are deprecated:
- get_sp()

The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()

The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()

All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
2021-12-28 16:58:37 +05:30
Aditya Patwardhan
5d61eea847 efuse_example_test: Fix the example test ( broken due to latest change
in info message)

*Unify the log messages when UART ROM Download mode is kept enabled
2021-11-23 15:21:32 +05:30
Aditya Patwardhan
be65338212 secure_boot: Fix warning when UART ROM DL mode is disabled
*Additionally use updated calls to enable rom secure download mode
2021-11-22 12:01:15 +05:30
Sachin Parekh
bf1dde7233 bootloader: Enable clock glitch detection
Reset the device when clock glitch detected. Clock glitch detection is
only active in bootloader
2021-09-02 12:25:12 +05:30
Armando (Dou Yiwen)
3e172289b0 Merge branch 'feature/support_octal_flash_120m_str_mode_on_esp32s3' into 'master'
mspi: support octal flash 120MHz STR mode on esp32s3

Closes IDF-3146

See merge request espressif/esp-idf!14668
2021-08-20 08:40:02 +00:00
Sachin Parekh
2d82560ed5 bootloader: Enable Secure boot V2 for ESP32-S3 2021-08-19 14:08:12 +05:30
Armando
d325f4d557 mspi: support octal flash 120M STR mode on esp32s3 2021-08-19 10:44:30 +08:00
Michael (XIAO Xufeng)
dd40123129 bootloader: add xmc spi_flash startup flow to improve reliability 2021-08-12 17:22:42 +08:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
KonstantinKondrashov
92448e7bd7 secure_boot: Whole 3 bits are set for SOFT_DIS_JTAG eFuse 2021-07-21 17:19:01 +05:00
Marius Vikhammer
b8a322195e flash encryption: add flash encryption support for ESP32-S3 2021-07-14 18:46:17 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Marius Vikhammer
71c1da8952 timer group: add timer group and WDT support for ESP32S3
Regenerate timer group header files and update LL, check examples
and update docs.
2021-07-06 16:21:43 +08:00
Konstantin Kondrashov
f339b3fc96 efuse(esp32): Deprecate esp_efuse_burn_new_values() & esp_efuse_write_random_key()
These functions were used only for esp32 in secure_boot and flash encryption.
Use idf efuse APIs instead of efuse regs.
2021-06-17 07:21:36 +08:00
Jan Brudný
a2686dc4eb bootloader: update copyright notice 2021-05-10 04:58:34 +02:00
Marius Vikhammer
2aead8ba57 Support ESP32S3 Beta 3 target
Update ROM API. Port changes from bringup branch.
2021-03-18 10:24:22 +08:00
KonstantinKondrashov
95564b4687 secure_boot: Secure Boot V2 verify app signature on update (without Secure boot)
- ESP32 ECO3, ESP32-S2/C3/S3
2021-03-15 12:30:20 +00:00
KonstantinKondrashov
88c5fe49b8 soc: Adds a soc_caps define for all chips to define the number of boot key digests 2021-01-19 20:51:13 +08:00
Konstantin Kondrashov
fbba2cb356 bootloader/esp32s2: Add using of efuse APIs for keys, purposes, wr/rd-protection bits for flash encryption, secure boot 2021-01-08 11:29:46 +08:00
Supreet Deshpande
e517b4953f Secure Boot v2: Fix the double padding of the image length during flash encryption
Fixes https://github.com/espressif/esp-idf/issues/6236
2020-12-21 11:32:37 +05:30
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
KonstantinKondrashov
66b9b589cb efuse: Adds support for esp32-s2 chip 2020-10-14 16:26:51 +08:00
morris
6225932201 bootloader_support: add esp32-s3 initial support 2020-09-22 15:15:03 +08:00