Commit Graph

502 Commits

Author SHA1 Message Date
Angus Gratton
8929a9cdb1 Merge branch 'feature/aes_hal' into 'master'
AES: refactor and add HAL layer

See merge request espressif/esp-idf!10979
2020-12-11 15:39:49 +08:00
morris
c39476d699 esp_rom: added esp_rom_install_uart_printf 2020-12-11 11:45:10 +08:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Angus Gratton
076be2b480 esp_rom: Refactor ROM CMakeLists.txt file
Reduce duplication and use a utility function for the "add ROM linker script"
pattern, move to a simple file structure of "one if block per target"
2020-11-30 15:23:15 +11:00
Angus Gratton
b68094199f esp_rom: Add initial ESP32-C3 support
From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
weitianhua
1de3b17192 Fix BT controller dead issue caused by clk overflow 2020-10-29 10:49:30 +08:00
morris
9de6cba434 ci: add more build test for esp32-s3 2020-10-27 17:22:17 +08:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master'
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver
Add a LL and HAL layer for SHA.
2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
chenjianqiang
f19cabb7e4 psram: support psram for esp32s3 2020-09-22 15:15:03 +08:00
morris
6225932201 bootloader_support: add esp32-s3 initial support 2020-09-22 15:15:03 +08:00
Jiang Jiang Jian
cfc4be0f06 Merge branch 'bugfix/confirmed_bugfix_from_baidu_proj' into 'master'
component_bt/bugfix: Confirmed bugfix from Baidu project

See merge request espressif/esp-idf!10450
2020-09-22 11:38:29 +08:00
Angus Gratton
033f49f974 Merge branch 'bugfix/cpp_header_rom_secure_boot' into 'master'
Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.

Closes IDFGH-3998

See merge request espressif/esp-idf!10528
2020-09-21 15:51:03 +08:00
Supreet Deshpande
0e940c80d4 Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.
Closes https://github.com/espressif/esp-idf/issues/5878
2020-09-20 22:50:44 +05:30
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
weitianhua
c598b816ba Confirmed bugfix from Baidu project 2020-09-15 19:36:20 +08:00
Jakob Hasse
20c068ef3b cmock: added cmock as component
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
2020-09-02 16:38:37 +08:00
Michael (XIAO Xufeng)
5425ef4ee4 hal: extract hal component from soc component 2020-09-01 13:25:32 +08:00
Renz Bagaporo
14902da344 esp32: move disabling rom log to esp_rom 2020-08-17 19:08:56 +08:00
Angus Gratton
a2dc60b254 Merge branch 'feature/secure_boot_esp32s2' into 'master'
Feature/secure boot esp32s2

See merge request espressif/esp-idf!8254
2020-07-28 16:39:34 +08:00
morris
2917651478 esp_rom: extract common ets apis into esp_rom_sys.h 2020-07-27 15:27:01 +08:00
Angus Gratton
a91bd4078f secure boot: Fixes for ESP32-S2 first boot logic 2020-07-27 00:01:10 +00:00
morris
ab0537c079 esp_rom: extract common MD5 hash apis into esp_rom_md5.h 2020-07-21 17:01:28 +08:00
Ivan Grokhotkov
8739282a1d Merge branch 'feature/size_info_artifacts_for_apps' into 'master'
CI: add size info for binaries

Closes IDF-1709

See merge request espressif/esp-idf!8962
2020-07-21 16:00:07 +08:00
Fu Hanxi
6885421976 CI: add size info for binaries 2020-07-21 16:00:05 +08:00
morris
345606e7f3 esp_rom: extract common uart apis into esp_rom_uart.h 2020-07-17 16:00:59 +08:00
morris
458b14a8ea esp_rom: extract common efuse apis into esp_rom_efuse.h 2020-07-15 10:40:50 +08:00
morris
a4d0033c03 esp_rom: extract common GPIO apis into esp_rom_gpio.h 2020-07-07 11:40:19 +08:00
Ivan Grokhotkov
4f8c42ca73 esp_rom: add patch to set USB device serial descriptor to MAC address 2020-06-24 15:50:51 +02:00
Ivan Grokhotkov
4901917ea3 esp_rom: add USB related headers from the ROM code 2020-06-24 15:50:51 +02:00
morris
a34409cffc esp_rom: extract common CRC apis into esp_rom_crc.h 2020-06-23 16:40:14 +08:00
wangcheng
7bad9b77cc components/bt:Fix instant reverse and add ble connect paramter check. 2020-06-18 11:21:46 +08:00
morris
0daff849a4 esp_rom: remove unsupported library on esp32s2
Closes https://github.com/espressif/esp-idf/issues/5434
2020-06-11 21:40:08 +08:00
morris
be91b7c52e esp_rom: add esp32s3 rom headers 2020-06-11 21:40:08 +08:00
morris
9cc0f33ed5 esp_rom: add esp32s3 rom symbols 2020-06-11 21:40:08 +08:00
morris
783779c870 esp_rom: move rom api test into esp_rom component 2020-06-03 13:16:13 +08:00
weitianhua
77cc105c72 Fix ld_acl schedule bug to parity shift 2020-05-18 06:51:51 +00:00
weitianhua
b20f254483 Free lmp tx buf in EM in the procedure of handling LMP_detach_Req when not received the last acknowledge from peer device and seperate them by ACL State 2020-05-18 06:51:51 +00:00
morris
5d0860f2e8 fix broken CONFIG_LEGACY_INCLUDE_COMMON_HEADERS 2020-04-20 14:01:09 +08:00
KonstantinKondrashov
9aeac7f6cb esp_rom: Fix esp32.rom.newlib-time.ld should includes all time ROM functions/data
- Added UT
Closes: https://github.com/espressif/esp-idf/issues/4925
2020-03-27 04:57:42 +00:00
baohongde
d2aa4a1e50 components/bt: Fix assert when create conntion cancel 2020-02-28 20:13:41 +08:00
Mahavir Jain
5f897fd33c Merge branch 'feat/secure_boot_v2_v41' into 'master'
feat/secure_boot_v2: Adding secure boot v2 support to ESP32-ECO3

Closes IDF-799

See merge request espressif/esp-idf!6778
2020-02-27 18:54:08 +08:00
Angus Gratton
d40c69375c bootloader: Add fault injection resistance to Secure Boot bootloader verification
Goal is that multiple faults would be required to bypass a boot-time signature check.

- Also strengthens some address range checks for safe app memory addresses
- Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32

Add some additional checks for invalid sections:

- Sections only partially in DRAM or IRAM are invalid
- If a section is in D/IRAM, allow the possibility only some is in D/IRAM
- Only pass sections that are entirely in the same type of RTC memory region
2020-02-27 14:37:19 +05:30
michael
7a3f21636f spi_flash: fix the reading issue using the ROM functions in the ROM 2020-02-26 11:12:09 +08:00
Supreet Deshpande
a9ccc5e5c8 feat/secure_boot_v2: Adding secure boot v2 support for ESP32-ECO3 2020-02-25 01:28:22 +05:30
baohongde
d11a86076f Fix bugs about role switch
Jitter in FHS
Jitter in first PULL
Receive EDR packet fail after role switch
2020-02-19 20:14:47 +08:00
Michael (XIAO Xufeng)
278634dcbd sdspi: support crc16_be for esp32s2 2020-02-12 15:15:46 +08:00
Jiang Jiang Jian
7f4309d0f1 Merge branch 'feature/esp32_5p0_code_optimize' into 'master'
controller flash code optimize

See merge request espressif/esp-idf!7409
2020-02-11 17:29:08 +08:00
Ivan Grokhotkov
e5cb972c3a Merge branch 'bugfix/fix_esp32s2_flash_rw' into 'master'
flash(esp32s2): fix setting address field in spi user mode.

See merge request espressif/esp-idf!7380
2020-02-09 18:05:22 +08:00
Wangjialin
aaf119e930 flash(esp32s2): fix setting address field in spi user mode. 2020-02-07 16:10:51 +01:00
Mahavir Jain
3803b17048 esp_rom: link newlib nano from ROM only if SPIRAM cache workaround is disabled 2020-02-07 16:17:25 +05:30
June
4f9c3e977e controller flash code optimize
fix ld file to link 3 bt rom functions
2020-01-31 06:29:46 +00:00
Ivan Grokhotkov
16e63f6a3f esp32s2: esp_rom: separate nano formatting functions, fix newlib tests 2020-01-23 18:07:37 +01:00
morris
405b0e7f06 esp_rom: splict libgcc and libc outof rom.ld bundle file 2020-01-23 00:27:47 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
Ivan Grokhotkov
cc3df01f8f rom: add header guards in rom/opi_flash.h, fix error in rom/spi_flash.h 2020-01-21 11:58:10 +01:00
Wangjialin
fad639f0d4 feature(psram): update psram initialization.
1. use spi functions in rom
2. remove unnecessary GPIO configurations.
3. remove unnecessary dummy settings.
4. enable dummy out function
5. flash and psram have independent timing setting registers.
6. no need to set 1.9v for LDO in 80Mhz
7. set IO driver ability to 1 by default.
8. no need to use GPIO matrix on esp32s2, IO MUX is recommended
9. enable spi clock mode and IO mode settings
2020-01-16 17:41:31 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
Konstantin Kondrashov
2c793cef06 idf: Support a custom toolchain with time_t wide 64-bits
Allows resolving the Y2K38 problem.

Closes: IDF-350

Closes: https://github.com/espressif/esp-idf/issues/584
2020-01-10 12:58:54 +08:00
morris
a86d741fc9 esp_rom: remove esp_rom.c 2019-12-09 09:48:31 +08:00
Ivan Grokhotkov
ea99137e62 esp32s2beta: implement esp_reset_reason API 2019-11-21 20:03:26 +01:00
Ivan Grokhotkov
9a2af7ae33 global: remove gcc 5.2 support 2019-11-20 11:17:27 +01:00
wanglei
5e55ffc95a fix dummy issue in spi mem and make some spiflash api called from idf 2019-11-15 15:59:07 +00:00
wanglei
f3424afaab bugfix: fix spi flash read when wrap enabled 2019-11-15 15:59:07 +00:00
Ivan Grokhotkov
5830f529d8 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-02 19:01:39 +02:00
Roland Dobai
5a916ce126 Support ELF files loadable with gdb 2019-09-24 07:19:50 +00:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Angus Gratton
f23b3fdbe4 rom: Add warnings for miniz functions that won't work due to missing malloc
Closes https://github.com/espressif/esp-idf/issues/4024
2019-09-06 11:01:34 +10:00
Michael (XIAO Xufeng)
9f1c8f0c76 spi_flash: support esp32s2beta 2019-09-04 10:53:25 +10:00
Angus Gratton
18c5cfadae Fix function prototypes 2019-08-13 17:14:16 +10:00
Angus Gratton
8f74271d5d esp_rom: Fail immediately if the wrong SoC's header file is included 2019-08-12 16:57:40 +10:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00
chenjianqiang
d77c74770a bugfix(flash): add flash config in app startup
We fixed some flash bugs in bootloader, but for the users used the old
vrsion bootloader, they can not fix these bugs via OTA, the solution is
add these updates in app startup.

These updates include:
1. SPI flash gpio matrix and drive strength configuration
2. SPI flash clock configuration
3. SPI flash read dummy configuration
4. SPI flash cs timing configuration
5. Update flash id of g_rom_flashchip
2019-07-18 14:40:59 +08:00
chenjianqiang
fd8b526f7c add two APIs into esp32beta.rom.spiflash.ld to fix compile error
When config flash mode as QIO mode, the error that esp_rom_spiflash_wait_idle
and esp_rom_spiflash_config_readmode are undefined happens when compile, so
add these two APIs to fix the error.
2019-06-21 21:50:48 +08:00
Renz Christian Bagaporo
9eccd7c082 components: use new component registration api 2019-06-21 19:53:29 +08:00
Wang Jia Lin
e2d1c6234f Merge branch 'bugfix/improve_flash_dio_read_timing' into 'master'
bugfix(flash): fix flash dio read mode configuration error on SPI0

See merge request idf/esp-idf!5086
2019-06-14 12:10:46 +08:00
Ivan Grokhotkov
7c723e121c esp_rom: update ld scripts to export strong symbols
Similar to commits for esp32 target: e84b26f5, 8c2f2867, 5719cd6f
2019-06-13 19:34:40 +08:00
Renz Christian Bagaporo
3882e48e8a cmake: use new signature form of target_link_library to link components
!4452 used setting LINK_LIBRARIES and INTERFACE_LINK_LIBRARIES to link
components built under ESP-IDF build system. However, LINK_LIBRARIES does
not produce behavior same as linking PRIVATE. This MR uses the new
signature for target_link_libraries directly instead. This also moves
setting dependencies during component registration rather than after all
components have been processed.

The consequence is that internally, components have to use the new
signature form as well. This does not affect linking the components to
external targets, such as with idf_as_lib example. This only affects
linking additional libraries to ESP-IDF libraries outside component processing (after
idf_build_process), which is not even possible for CMake<v3.13 as
target_link_libraries is not valid for targets not created in current
directory. See https://cmake.org/cmake/help/v3.13/policy/CMP0079.html#policy:CMP0079
2019-06-11 18:09:26 +08:00
suda-morris
84b2f9f14d build and link hello-world for esp32s2beta 2019-06-11 13:07:37 +08:00
suda-morris
61ce868396 make bootloader_support support esp32s2beta 2019-06-11 13:07:02 +08:00
suda-morris
cc98b9ef60 add rom for esp32s2beta 2019-06-11 13:06:32 +08:00
Angus Gratton
045aaf6fb0 Merge branch 'feature/add_xxx_periph_h' into 'master'
soc: Add xxx_periph.h for all modules

Closes IDF-192

See merge request idf/esp-idf!4952
2019-06-04 13:24:14 +08:00
Angus Gratton
db6a30b446 Merge branch 'bugfix/libgcc_fpu_functions' into 'master'
esp32: Use FPU for floating point divide, power, complex multiplications

See merge request idf/esp-idf!5005
2019-06-04 08:41:58 +08:00
Konstantin Kondrashov
399d2d2605 all: Using xxx_periph.h
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .

Cleaned up header files from unnecessary headers (releated to soc/... headers).
2019-06-03 14:15:08 +08:00
Angus Gratton
d9a5c8f387 esp32: Use FPU for floating point divide, power, complex multiplications
* Linker was choosing ROM symbols for these, which use integer soft-float
  operations and are much slower.
* _divsf3() moved to IRAM to avoid regressions with any code that does
  integer float division in IRAM interrupt handlers (+88 bytes IRAM)
* Thanks to michal for reporting:
  https://esp32.com/viewtopic.php?f=14&t=10540&p=43367
2019-05-29 10:14:31 +10:00
chenjianqiang
d68f1907ef bugfix(flash): improve flash dio read timing
When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).
2019-05-28 14:51:04 +08:00
Angus Gratton
22514c1dd9 cmake: For gcc8 use linker to find paths to libc, libm, libstdc++, etc
Removes the need to know/guess the paths to these libraries. Once we are gcc 8 only, we
can remove -nostdlib and no additional arguments are needed for system libraries.

The catch is: any time IDF overrides a symbol in the toolchain sysroot, we need
an undefined linker marker to make sure this symbol is seen by linker.
2019-05-28 12:54:37 +08:00
Renz Christian Bagaporo
ffec9d4947 components: update with build system changes 2019-05-13 19:59:17 +08:00
Konstantin Kondrashov
bbdeff1da1 esp32: Rewrite esp_sha function
It removes using a STALL_OTHER_CPU while sha operations.
It improves performance with SHA.
2019-05-13 12:32:45 +08:00
Michael (XIAO Xufeng)
562af8f65e global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.

Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.

In CMAKE, we have two kinds of header visibilities (set by include path visibility):

(Assume component A --(depends on)--> B, B is the current component)

1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)

and we have two kinds of depending ways:

(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)

1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)

1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)

This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:

- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h

The major broken include chain includes:

1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h

some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h

BREAKING CHANGE
2019-04-16 13:21:15 +08:00
Ivan Grokhotkov
5719cd6fac newlib: when compiling with GCC8, use newlib headers and libraries from toolchain 2019-04-10 13:52:30 +08:00
Ivan Grokhotkov
8c2f2867d8 esp_rom: don’t include locale functions when compiling with newlib 3 2019-04-10 13:52:30 +08:00
Ivan Grokhotkov
e84b26f531 esp_rom: export newlib functions as strong symbols 2019-04-10 13:52:30 +08:00
morris
709a320f33 move hwcrypto from esp32 to mbedtls 2019-03-26 16:24:22 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00