mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feature(psram): update psram initialization.
1. use spi functions in rom 2. remove unnecessary GPIO configurations. 3. remove unnecessary dummy settings. 4. enable dummy out function 5. flash and psram have independent timing setting registers. 6. no need to set 1.9v for LDO in 80Mhz 7. set IO driver ability to 1 by default. 8. no need to use GPIO matrix on esp32s2, IO MUX is recommended 9. enable spi clock mode and IO mode settings
This commit is contained in:
Wangjialin
morris
parent
0ad7602efe
commit
fad639f0d4
@ -41,12 +41,12 @@ void bootloader_flash_update_id()
|
||||
|
||||
void IRAM_ATTR bootloader_flash_cs_timing_config()
|
||||
{
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
|
||||
SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
|
||||
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
|
||||
@ -71,43 +71,14 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
|
||||
esp_rom_spiflash_config_clk(spi_clk_div, 0);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_set_dummy_out(void)
|
||||
{
|
||||
REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
|
||||
REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
|
||||
}
|
||||
|
||||
void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
|
||||
{
|
||||
int spi_cache_dummy = 0;
|
||||
int drv = 2;
|
||||
switch (pfhdr->spi_mode) {
|
||||
case ESP_IMAGE_SPI_MODE_QIO:
|
||||
spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_DIO:
|
||||
spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_QOUT:
|
||||
case ESP_IMAGE_SPI_MODE_DOUT:
|
||||
default:
|
||||
spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
|
||||
break;
|
||||
}
|
||||
|
||||
/* dummy_len_plus values defined in ROM for SPI flash configuration */
|
||||
extern uint8_t g_rom_spiflash_dummy_len_plus[];
|
||||
switch (pfhdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_80M:
|
||||
g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
|
||||
g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
|
||||
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
|
||||
SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
drv = 3;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_40M:
|
||||
g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
|
||||
g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
|
||||
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
|
||||
SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
bootloader_configure_spi_pins(drv);
|
||||
bootloader_configure_spi_pins(1);
|
||||
bootloader_flash_set_dummy_out();
|
||||
}
|
||||
|
||||
@ -40,52 +40,38 @@
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include <string.h>
|
||||
|
||||
static const char *TAG = "boot.esp32s2";
|
||||
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
|
||||
#define FLASH_SPID_IO SPI_D_GPIO_NUM
|
||||
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
|
||||
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
|
||||
|
||||
void bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = ets_efuse_get_spiconfig();
|
||||
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
|
||||
gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
|
||||
gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
|
||||
gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
|
||||
gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
|
||||
gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
|
||||
//select pin function gpio
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO);
|
||||
// flash clock signal should come from IO MUX.
|
||||
// set drive ability for clock
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, drv, FUN_DRV_S);
|
||||
|
||||
#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64
|
||||
uint32_t flash_id = g_rom_flashchip.device_id;
|
||||
if (flash_id == FLASH_ID_GD25LQ32C) {
|
||||
// Set drive ability for 1.8v flash in 80Mhz.
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
}
|
||||
#endif
|
||||
uint8_t wp_pin = ets_efuse_get_wp_pad();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
clk_gpio_num = spiconfig & 0x3f;
|
||||
q_gpio_num = (spiconfig >> 6) & 0x3f;
|
||||
d_gpio_num = (spiconfig >> 12) & 0x3f;
|
||||
cs0_gpio_num = (spiconfig >> 18) & 0x3f;
|
||||
hd_gpio_num = (spiconfig >> 24) & 0x3f;
|
||||
wp_gpio_num = wp_pin;
|
||||
}
|
||||
gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
gpio_pad_set_drv(q_gpio_num, drv);
|
||||
gpio_pad_set_drv(d_gpio_num, drv);
|
||||
gpio_pad_set_drv(cs0_gpio_num, drv);
|
||||
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
gpio_pad_set_drv(hd_gpio_num, drv);
|
||||
}
|
||||
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
gpio_pad_set_drv(wp_gpio_num, drv);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -152,6 +152,37 @@ menu "ESP32S2-specific"
|
||||
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
|
||||
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
|
||||
default 0
|
||||
menu "PSRAM clock and cs IO for ESP32S2"
|
||||
depends on ESP32S2_SPIRAM_SUPPORT
|
||||
config DEFAULT_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 30
|
||||
help
|
||||
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
|
||||
|
||||
config DEFAULT_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 26
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
|
||||
endmenu
|
||||
config SPIRAM_SPIWP_SD3_PIN
|
||||
int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
|
||||
depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
|
||||
range 0 33
|
||||
default 28
|
||||
help
|
||||
This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
|
||||
overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
|
||||
|
||||
Different from esp32 chip, on esp32s2, the WP pin would also be defined in efuse. This value would only
|
||||
be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid.
|
||||
|
||||
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in
|
||||
bootloader.
|
||||
|
||||
|
||||
config SPIRAM_FETCH_INSTRUCTIONS
|
||||
bool "Cache fetch instructions from SPI RAM"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -28,8 +28,9 @@ typedef enum {
|
||||
} psram_cache_mode_t;
|
||||
|
||||
typedef enum {
|
||||
PSRAM_SIZE_32MBITS = 0,
|
||||
PSRAM_SIZE_64MBITS = 1,
|
||||
PSRAM_SIZE_16MBITS = 0,
|
||||
PSRAM_SIZE_32MBITS = 1,
|
||||
PSRAM_SIZE_64MBITS = 2,
|
||||
PSRAM_SIZE_MAX,
|
||||
} psram_size_t;
|
||||
|
||||
|
||||
291
components/esp_rom/include/esp32s2beta/rom/opi_flash.h
Normal file
291
components/esp_rom/include/esp32s2beta/rom/opi_flash.h
Normal file
@ -0,0 +1,291 @@
|
||||
/*
|
||||
* copyright (c) Espressif System 2019
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ROM_OPI_FLASH_H_
|
||||
#define _ROM_OPI_FLASH_H_
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include "spi_flash.h"
|
||||
|
||||
typedef struct {
|
||||
uint16_t cmd; /*!< Command value */
|
||||
uint16_t cmdBitLen; /*!< Command byte length*/
|
||||
uint32_t *addr; /*!< Point to address value*/
|
||||
uint32_t addrBitLen; /*!< Address byte length*/
|
||||
uint32_t *txData; /*!< Point to send data buffer*/
|
||||
uint32_t txDataBitLen; /*!< Send data byte length.*/
|
||||
uint32_t *rxData; /*!< Point to recevie data buffer*/
|
||||
uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/
|
||||
uint32_t dummyBitLen;
|
||||
} esp_rom_spi_cmd_t;
|
||||
|
||||
#define ESP_ROM_OPIFLASH_MUX_TAKE()
|
||||
#define ESP_ROM_OPIFLASH_MUX_GIVE()
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
|
||||
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
|
||||
|
||||
// Definition of MX25UM25645G Octa Flash
|
||||
// SPI status register
|
||||
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
|
||||
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
|
||||
#define ESP_ROM_SPIFLASH_BP0 BIT2
|
||||
#define ESP_ROM_SPIFLASH_BP1 BIT3
|
||||
#define ESP_ROM_SPIFLASH_BP2 BIT4
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
|
||||
#define ESP_ROM_SPIFLASH_QE BIT9
|
||||
|
||||
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
|
||||
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
|
||||
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
|
||||
#define ESP_ROM_FLASH_PAGE_SIZE 256
|
||||
|
||||
// FLASH commands
|
||||
#define ROM_FLASH_CMD_RDID 0x9F
|
||||
#define ROM_FLASH_CMD_WRSR 0x01
|
||||
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_WREN 0x06
|
||||
#define ROM_FLASH_CMD_WRDI 0x04
|
||||
#define ROM_FLASH_CMD_RDSR 0x05
|
||||
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_ERASE_SEC 0x20
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
|
||||
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
|
||||
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
|
||||
#define ROM_FLASH_CMD_RSTEN 0x66
|
||||
#define ROM_FLASH_CMD_RST 0x99
|
||||
|
||||
#define ROM_FLASH_CMD_SE4B 0x21
|
||||
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
|
||||
#define ROM_FLASH_CMD_BE4B 0xDC
|
||||
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
|
||||
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
|
||||
#define ROM_FLASH_CMD_RST_OCT 0x6699
|
||||
|
||||
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
|
||||
#define ROM_FLASH_CMD_FSTRD4B 0x0C
|
||||
#define ROM_FLASH_CMD_PP4B 0x12
|
||||
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
|
||||
|
||||
#define ROM_FLASH_CMD_RDID_OCT 0x609F
|
||||
#define ROM_FLASH_CMD_WREN_OCT 0xF906
|
||||
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
|
||||
#define ROM_FLASH_CMD_RDCR2 0x71
|
||||
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
|
||||
#define ROM_FLASH_CMD_WRCR2 0x72
|
||||
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
|
||||
|
||||
// Definitions for GigaDevice GD25LX256E Flash
|
||||
#define ROM_FLASH_CMD_RDFSR_GD 0x70
|
||||
#define ROM_FLASH_CMD_RD_GD 0x03
|
||||
#define ROM_FLASH_CMD_RD4B_GD 0x13
|
||||
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
|
||||
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
|
||||
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
|
||||
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
|
||||
|
||||
#define ROM_FLASH_CMD_PP_GD 0x02
|
||||
#define ROM_FLASH_CMD_PP4B_GD 0x12
|
||||
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
|
||||
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
|
||||
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
|
||||
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
|
||||
|
||||
#define ROM_FLASH_CMD_SE_GD 0x20
|
||||
#define ROM_FLASH_CMD_SE4B_GD 0x21
|
||||
#define ROM_FLASH_CMD_BE32K_GD 0x52
|
||||
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
|
||||
#define ROM_FLASH_CMD_BE64K_GD 0xD8
|
||||
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
|
||||
|
||||
#define ROM_FLASH_CMD_EN4B_GD 0xB7
|
||||
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
|
||||
|
||||
// spi user mode command config
|
||||
|
||||
/**
|
||||
* @brief Config the spi user command
|
||||
* @param spi_num spi port
|
||||
* @param pcmd pointer to accept the spi command struct
|
||||
*/
|
||||
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
|
||||
|
||||
/**
|
||||
* @brief Start a spi user command sequence
|
||||
* @param spi_num spi port
|
||||
* @param rx_buf buffer pointer to receive data
|
||||
* @param rx_len receive data length in byte
|
||||
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
|
||||
* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
|
||||
*/
|
||||
void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
|
||||
|
||||
/**
|
||||
* @brief Config opi flash pads according to efuse settings.
|
||||
*/
|
||||
void esp_rom_opiflash_pin_config(void);
|
||||
|
||||
// set SPI read/write mode
|
||||
/**
|
||||
* @brief Set SPI operation mode
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
*/
|
||||
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Set data swap mode in DTR(DDR) mode
|
||||
* @param spi_num spi port
|
||||
* @param wr_swap to decide whether to swap fifo data in dtr write operation
|
||||
* @param rd_swap to decide whether to swap fifo data in dtr read operation
|
||||
*/
|
||||
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
|
||||
|
||||
|
||||
/**
|
||||
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
*/
|
||||
void esp_rom_opiflash_mode_reset(int spi_num);
|
||||
|
||||
#if 0
|
||||
// MX25UM25645G opi flash interface
|
||||
/**
|
||||
* @brief To execute a flash operation command
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Read Mode
|
||||
* @param cmd data to send in command field
|
||||
* @param cmd_bit_len bit length of command field
|
||||
* @param addr data to send in address field
|
||||
* @param addr_bit_len bit length of address field
|
||||
* @param dummy_bits bit length of dummy field
|
||||
* @param mosi_data data buffer to be sent in mosi field
|
||||
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
|
||||
* @param miso_data data buffer to accept data in miso field
|
||||
* @param miso_bit_len bit length of data buffer to accept data in miso field
|
||||
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
|
||||
* @param is_write_erase_operation to indicate whether this a write or erase flash operation
|
||||
*/
|
||||
void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
|
||||
uint32_t cmd, int cmd_bit_len,
|
||||
uint32_t addr, int addr_bit_len,
|
||||
int dummy_bits,
|
||||
uint8_t* mosi_data, int mosi_bit_len,
|
||||
uint8_t* miso_data, int miso_bit_len,
|
||||
uint32_t cs_mask,
|
||||
bool is_write_erase_operation);
|
||||
|
||||
/**
|
||||
* @brief send reset command to opi flash
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
*/
|
||||
void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to read opi flash ID(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
* @return opi flash id
|
||||
*/
|
||||
uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to read opi flash status register(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
* @return opi flash status value
|
||||
*/
|
||||
uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief wait opi flash status register to be idle
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
*/
|
||||
void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to read the config register2(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
* @param addr the address of configure register
|
||||
* @return value of config register2
|
||||
*/
|
||||
uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr);
|
||||
|
||||
/**
|
||||
* @brief to write the config register2(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode Flash Operation Mode
|
||||
* @param addr the address of config register
|
||||
* @param val the value to write
|
||||
*/
|
||||
void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val);
|
||||
|
||||
/**
|
||||
* @brief to erase flash sector(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param address the sector address to be erased
|
||||
* @param mode Flash operation mode
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to erase flash block(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param address the block address to be erased
|
||||
* @param mode Flash operation mode
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to erase a flash area define by start address and length(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param start_addr the start address to be erased
|
||||
* @param area_len the erea length to be erased
|
||||
* @param mode flash operation mode
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief to read data from opi flash(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode flash operation mode
|
||||
* @param flash_addr flash address to read data from
|
||||
* @param data_addr data buffer to accept the data
|
||||
* @param len data length to be read
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len);
|
||||
|
||||
/**
|
||||
* @brief to write data to opi flash(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param mode flash operation mode
|
||||
* @param flash_addr flash address to write data to
|
||||
* @param data_addr data buffer to write to flash
|
||||
* @param len data length to write
|
||||
* @return flash operation result
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief to set opi flash operation mode(for MX25UM25645G)
|
||||
* @param spi_num spi port
|
||||
* @param cur_mode current operation mode
|
||||
* @param target the target operation mode to be set
|
||||
*/
|
||||
void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -19,7 +19,6 @@
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "esp_attr.h"
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -125,7 +124,12 @@ typedef enum {
|
||||
ESP_ROM_SPIFLASH_DIO_MODE,
|
||||
ESP_ROM_SPIFLASH_DOUT_MODE,
|
||||
ESP_ROM_SPIFLASH_FASTRD_MODE,
|
||||
ESP_ROM_SPIFLASH_SLOWRD_MODE
|
||||
ESP_ROM_SPIFLASH_SLOWRD_MODE,
|
||||
ESP_ROM_SPIFASH_OPI_STR_MODE,
|
||||
ESP_ROM_SPIFASH_OPI_DTR_MODE,
|
||||
ESP_ROM_SPIFASH_OOUT_MODE,
|
||||
ESP_ROM_SPIFASH_OIO_STR_MODE,
|
||||
ESP_ROM_SPIFASH_OIO_DTR_MODE,
|
||||
} esp_rom_spiflash_read_mode_t;
|
||||
|
||||
typedef enum {
|
||||
|
||||
@ -139,6 +139,7 @@
|
||||
#define U0RXD_GPIO_NUM 44
|
||||
#define U0TXD_GPIO_NUM 43
|
||||
|
||||
#define SPI_CS1_GPIO_NUM 26
|
||||
#define SPI_HD_GPIO_NUM 27
|
||||
#define SPI_WP_GPIO_NUM 28
|
||||
#define SPI_CS0_GPIO_NUM 29
|
||||
|
||||
Loading…
Reference in New Issue
Block a user