1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
GCC compiler can generate 8-bit stores when modifying bitfields of
volatile structs (https://github.com/espressif/esp-idf/issues/597).
In the specific case of I2C driver, this resulted in byte_num field
to be written using s8i. However the peripheral requires 32-bit
writes, and ignores 8-bit writes. This change modifies the code to
compose the 32-bit command register value first, and then write the
complete value to the hardware.
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2S if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2C if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
Removed as much branching (if statements) from the
gpio_intr_service ISR, as possible and split the while loop into
two. Also forced writing the two status*_w1tc variables only once,
instead of every time after calling the external function hooks.
The measurements below, was done using the following tools:
Toolchain version: crosstool-ng-1.22.0-80-g6c4433a
Compiler version: 5.2.0
Here follows a comparison of the gpio_intr_service ISR's
execution time, using a DS1054 oscilloscope. All the time spent
calling external functions, via the function pointers
gpio_isr_func[gpio_num].fn, were disregarded.
With OPTIMIZATION_FLAGS = -Og, 1.34 uSeconds faster:
3.22 uSec (with this patch)
4.56 uSec (with commit 71c90ac4)
100 - (100 * 4.56 / 3.22) = 42% faster
With OPTIMIZATION_FLAGS = -Os, 1.65 uSeconds faster:
2.89 uSec (with this patch)
4.54 uSec (with commit 71c90ac4)
100 - (100 * 4.54 / 2.89) = 57% faster
Signed-off-by: Konstantin Kondrashov <konstantin@espressif.com>
Merges https://github.com/espressif/esp-idf/pull/2861
This commits adds the functions can_clear_transmit_queue() and
can_clear_receive_queue(). Closes#2906
The following bug are fixed:
- CAN_IO_UNUSED is now explicitly cast to enum type. Closes#2825
- Fix multiple documentation errors. Closes#2898, Closes#2794
- can_reconfigure_alerts() returns incorrect current_alerts. Closes#3028
- Add missing header file. Closes#3065
The requirements of pin capabilites is different for spi master and
slave. The master needs CS, SCLK, MOSI to be output-able, while slave
needs MISO to be output-able.
Previous code is for master only.
This commit allows to place other 3 pins than MISO on input-only pins
for slaves. Refactoring for spi_common is also included.
Resolves https://github.com/espressif/esp-idf/issues/2455
New unit tests added
------------------------
**Local:** Local test uses the GPIO matrix to connect the master and the
slave on the same board. When the master needs the iomux, the master
uses the GPIOs of its own, the slave connect to the pins by GPIO matrix;
When the slave needs the iomux, the slave uses the GPIOs of its own, the
master connects to the pins by GPIO matrix.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
**M & S**: Master & slave tests performs the test with two boards. The
master and slave use iomux or gpio matrix according to the config.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
- Provide a new unit test which performs mode test with significant
frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum
frequency allowed.
Paremeterized Test Framework
-----------------------------
The SPI has a lot of parameters, which works in the same process.
This framework provides a way to easily test different parameter sets.
The framework can work in two different ways:
- local test: which requires only one board to perform the test - master
& slave test: which generates two sub test items which uses the same
config set to cooperate to perform the test.
The user defines a (pair if master/slave) set of init/deinit/loop
functions. Then the test framework will call init once, then call loop
several times with different configurations, then call deinit.
Then a unit test can be appended by add a parameter group, and pass it into
a macro.
1. fix error when fading is too fast
2. fix error when setting duty and update immediately
3. update register header file to be in accord with TRM
closes https://github.com/espressif/esp-idf/issues/2903
1. Add missing get function to RMT API: rmt_get_idle_level().
2. Suppress error message from rmt_wait_tx_done() if wait_time==0 (allows for polling).
3. Remove the blank lines between parameter lists.
Merges https://github.com/espressif/esp-idf/pull/2666
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496
1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
I am stealing this delay coding from @jeremyherbert #2493 pr.
2. Change Bus Reset to handle interrupted READ sequences.
The current code does not handle interrupted READ cycles.
If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.
The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.
So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
3. fix typo
correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it. This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
