alex/esp-idf
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85 Commits

Author SHA1 Message Date
jingli
4223427127 hal/gpio_ll: fix digital gpio can not disable hold during deep sleep 2022-12-02 12:24:52 +00:00
jingli
21c9ec5eee esp_hw_support/sleep: fix current leakage when hold digital io during deep sleep 2022-12-02 12:24:52 +00:00
liuning
eb61f5835a esp_wifi: add protection for mac reset (backport 5.0) 2022-10-31 17:55:03 +08:00
Jiang Jiang Jian
fdb2550da0 Merge branch 'bugfix/spi_hd_quad_issue_5.0' into 'release/v5.0' 
SPI : fix wrong dummy cycle on quad mode and put get-command function in spi_ll.h(backport v5.0)

See merge request espressif/esp-idf!19799
 2022-09-14 13:49:42 +08:00
gaoxu
1148e4e77f SPI: Fixed Quad SPI wrong dummy cycle issue on ESP32C2/ESP32C3/ESP32S3 and put get-command/dummy-bits functions in spi_ll.h 2022-09-07 18:48:05 +08:00
KonstantinKondrashov
72de8349a6 efuse(es32c2): Supports 26MHz XTAL 2022-09-02 10:05:20 +00:00
Michael (XIAO Xufeng)
69be7c4cc2 Merge branch 'feat/support_esp32c2_uart_v5.0' into 'release/v5.0' 
uart: update console docs about frequency for ESP32-C2, move frequency of clock sources out of HAL (v5.0)

See merge request espressif/esp-idf!19690
 2022-08-25 02:03:26 +08:00
Michael (XIAO Xufeng)
6ed15178b6 uart: move frequency of clock sources out of HAL 2022-08-22 14:28:12 +08:00
zlq
3dc89437cc support auto adjust LDO voltage based on pvt-dig 2022-08-17 17:25:59 +08:00
morris
cf4cfc69ed esp_adc: add test with -O0 2022-08-02 23:07:06 +08:00
morris
031adc01c4 gpio: add test with -O0 2022-08-02 23:07:06 +08:00
morris
7faf1bee73 gptimer: add test with -O0 2022-08-02 22:53:36 +08:00
Armando
f325ad2211 mmu: fix wrong mmu end check 
In mmu code, we follow the rule that the `end` address shouldn't be
touched. This commit fix wrong end address check in mmu_ll.h
 2022-07-27 10:22:09 +00:00
morris
d94432fea8 systimer: refactor hal to accomodate more xtal choices 2022-07-25 16:08:52 +08:00
Song Ruo Jing
4734b1433b Merge branch 'bugfix/gpio_hal_coverity_fix' into 'master' 
gpio: Fix ESP32S3 GPIO48 does not support hold function bug and Fix coverity report

Closes IDF-4901

See merge request espressif/esp-idf!18805
 2022-07-19 21:37:15 +08:00
Armando (Dou Yiwen)
9f6f61345b Merge branch 'feature/adc_driver_ng' into 'master' 
ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
 2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5 I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2 2022-07-19 11:41:42 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
songruojing
0c4b9a0101 gpio: Fix HAL bad bit shift operation on gpio_num_t reported from coverity 
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
 2022-07-15 16:51:25 +08:00
Ivan Grokhotkov
2e37218ce5 soc, hal: remove XTAL_CLK_FREQ 
XTAL_CLK_FREQ now depends on the actual XTAL used, remove this macro
and get the XTAL frequency from the RTC register instead.
No uses of XTAL_CLK_FREQ found, other than in the UART LL.
 2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency 
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
 2022-07-11 12:24:37 +08:00
Michael (XIAO Xufeng)
a58362a429 Merge branch 'feature/efuse_rev_major_minor' into 'master' 
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
 2022-07-07 11:48:54 +08:00
Song Ruo Jing
b662f4b74f Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master' 
support c2 26M/32M xtal for bbpll

Closes IDF-5485

See merge request espressif/esp-idf!18769
 2022-07-06 21:17:52 +08:00
Cao Sen Miao
e218723e0e I2C: Make I2C clock frequency accurate 2022-07-06 11:58:08 +08:00
cje
e16165f263 support c2 26M/32M xtal for bbpll 2022-07-05 17:45:03 +08:00
KonstantinKondrashov
0f8ff5aa15 efuse: Adds major and minor versions and others 2022-07-05 14:38:27 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
Armando
31b3f31ef4 ext_mem: make memory region check strict 2022-06-28 14:17:44 +08:00
Cao Sen Miao
2c0651a671 Add regi2c enable/disable reference count 2022-06-23 15:36:44 +08:00
Cao Sen Miao
3a820462ac temperature_sensor: Add temperature sensor support for ESP32-C2 2022-06-23 15:36:43 +08:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Omar Chebib
2fd784c97a G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h" 2022-06-14 15:00:53 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung
a8a3756b38 hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls 
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:

- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead

Also updated soc_hal.h as follows:

- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.

This commit also updates the XCHAL_ERRATUM_572 workaround by

- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
 2022-06-14 14:40:03 +08:00
Darian Leung
149872131a hal: Move dedicated GPIO LL and HAL 
This commit moves the dedicated GPIO LL and HAL functions from
cpu_ll.h to dedic_gpio_cpu_ll.h.

- cpu_ll_enable_cycle_count() has also been removed due to lack of feasible usage scenarios
 2022-06-14 14:38:29 +08:00
songruojing
c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00
Cao Sen Miao
6589daabb9 MMU: Add configurable mmu page size support on ESP32C2 2022-06-08 19:34:31 +08:00
Michael (XIAO Xufeng)
773715d900 Merge branch 'feature/support_refresh_brownout_v1' into 'master' 
spi_flash: send reset when brownout detected on XMC flash

Closes IDF-3882

See merge request espressif/esp-idf!16873
 2022-06-06 16:27:58 +08:00
Geng Yuchao
c1505d045c Add periph_module needed for BT 2022-06-03 21:47:58 +08:00
Cao Sen Miao
6a2d3509dc spi_flash: Making XMC flash works more stable when brownout detected 2022-06-02 10:38:55 +08:00
Konstantin Kondrashov
b824f68b35 Merge branch 'feature/move_dport_workaround_to_g0' into 'master' 
dport_access: Move DPORT workaround to G0

Closes IDF-2177

See merge request espressif/esp-idf!17961
 2022-06-01 12:11:12 +08:00
KonstantinKondrashov
0b22839925 hal(ecp32c2): Adds spi_flash_encrypted_ll 2022-05-31 11:12:21 +00:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
morris
4352c39e3e Merge branch 'feature/cache_c2_support' into 'master' 
cache: access error & illegal error ll functions

Closes IDF-3820

See merge request espressif/esp-idf!18203
 2022-05-30 11:40:11 +08:00
Jiang Jiang Jian
f3922f1b7f Merge branch 'feature/flash_mmap_refactor' into 'master' 
flash mmap: abstract R/W of MMU table instead of reg access

See merge request espressif/esp-idf!16882
 2022-05-29 13:56:37 +08:00
morris
7642be45ef Merge branch 'bugfix/c2_efuse_fix_error_reg' into 'master' 
efuse_hal(esp32c2): Fix error bits for BLOCK0

See merge request espressif/esp-idf!18219
 2022-05-25 04:24:55 +08:00
KonstantinKondrashov
c74d442d03 efuse_hal: Fix error bits for BLOCK0 
eFuse BLOCK0 has only one error reg.
 2022-05-24 03:28:57 +08:00
Armando
8532d09259 cache: access error & illegal error ll functions 2022-05-23 15:00:47 +08:00
jiangguangming
9c6afee12f flash mmap: abstract R/W MMU table instead of reg access 2022-05-20 16:46:27 +08:00