Commit Graph

18 Commits

Author SHA1 Message Date
Shang Zhou
172aca432a docs: Update CN translation for out-of-sync api-reference files 2022-12-16 19:19:39 +08:00
wanlei
3aeedc2ad3 spi: bringup c6 spi master & slave driver support 2022-11-18 15:54:14 +08:00
wanlei
df5e1a2ff0 doc/spi: add chapter about IOMUX and GPIO matrix in SPI Driver Usage 2022-10-17 16:25:59 +08:00
Shang Zhou
2cfce11fb8 docs: provide CN translation for spi_slave and spi_features 2022-06-14 14:31:42 +08:00
morris
dce0993ce5 doc: apply wavedrom extension 2022-05-01 22:58:19 +08:00
Marius Vikhammer
a6543f0d21 docs: fix broken references to misc API functions and types. 2022-03-27 16:46:57 +08:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Armando
6a74cb695d spi: support spi on 8684 2022-01-12 11:30:29 +08:00
Armando
fa34cfcc0c spi: update spi master / slave programming guide on s3 2021-09-03 16:44:19 +08:00
Wang Fang
9b4e23ab0b docs: Fix ADC pad and MOSI typo, update esp32c3 rom elf link 2021-07-28 17:02:28 +08:00
Armando
9aa9939406 spi: update esp32c3 programming guide 2021-04-15 21:20:19 +08:00
Armando
725a8e6de0 docs: remove no longer existent limitation of spi slave 2020-08-26 09:00:34 +00:00
Marius Vikhammer
105567d077 doc: updated peripherals api-reference for s2 2020-02-07 16:37:44 +11:00
Angus Gratton
e6211c7864 docs: add new top-level docs builder that builds docs for a single chip 2020-02-07 16:37:43 +11:00
Kirill Chalov
2c7165f783 Review the file api-reference/peripherals/spi_slave.rst 2019-10-15 22:13:03 +08:00
michael
58955a79a2 spi_slave: improve the timing configuration
SPI Slave
===========

- Correct the configuration of mode 0~3 using new config in the TRM
- Split the workaround for DMA in mode 0/2 out of normal config, to make it clear.
- Update timing and speed document for the SPI slave.

Resolves https://github.com/espressif/esp-idf/issues/1346, https://github.com/espressif/esp-idf/issues/2393
2019-01-26 00:10:41 +08:00
michael
cfba157fdd spi_slave: add valid check for DMA buffers
The DMA cannot receive data correctly when the buffer address is not
WORD aligned. Currently we only check whether the buffer is in the DRAM
region.

The DMA always write in WORDs, so the length arguments should also be
multiples of 32 bits.

A check is added to see whether the buffer is WORD aligned and has valid
length.
2018-11-26 03:49:26 +00:00
krzychb
097adc3a33 Moved files into separate folders per 'en' and 'zh_CN' language version and linked 'zh_CN' files back to 'en' files if translation is not yet available 2018-03-13 21:57:08 +01:00