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docs: Update CN translation for out-of-sync api-reference files
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Shang Zhou
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172aca432a
@ -21,7 +21,6 @@ GPIO Summary
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:SOC_ULP_SUPPORTED: - The :doc:`Ultra Low Power co-processor <../../api-reference/system/ulp>` is running
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- Analog functions such as ADC/DAC/etc are in use.
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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GPIO Glitch Filter
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@ -31,7 +30,7 @@ GPIO Summary
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
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Each GPIO can be configured with a glitch filter, which can be used to filter out pulses shorter than **two** sample clock cycles. The duration of the filter is not configurable. The sample clock is the clock source of the IO-MUX. In the driver, we call this kind of filter as "pin glitch filter". You can create the filter handle by calling :cpp:func:`gpio_new_pin_glitch_filter`. All the configurations for a pin glitch filter are listed in the :cpp:type:`gpio_pin_glitch_filter_config_t` structure.
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Each GPIO can be configured with a glitch filter, which can be used to filter out pulses shorter than **two** sample clock cycles. The duration of the filter is not configurable. The sample clock is the clock source of the IO_MUX. In the driver, we call this kind of filter as ``pin glitch filter``. You can create the filter handle by calling :cpp:func:`gpio_new_pin_glitch_filter`. All the configurations for a pin glitch filter are listed in the :cpp:type:`gpio_pin_glitch_filter_config_t` structure.
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- :cpp:member:`gpio_pin_glitch_filter_config_t::gpio_num` sets the GPIO number to enable the glitch filter.
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@ -39,14 +38,14 @@ GPIO Summary
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{IDF_TARGET_FLEX_GLITCH_FILTER_NUM:default="8"}
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{IDF_TARGET_NAME} provides {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} flexible glitch filters, whose duration is configurable. We refer to this kind of filter as "flex flitch filter". Each of them can be applied to any input GPIO. However, applying multiple filters to the same GPIO doesn't make difference from one. You can create the filter handle by calling :cpp:func:`gpio_new_flex_glitch_filter`. All the configurations for a flexible glitch filter are listed in the :cpp:type:`gpio_flex_glitch_filter_config_t` structure.
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{IDF_TARGET_NAME} provides {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} flexible glitch filters, whose duration is configurable. We refer to this kind of filter as ``flex flitch filter``. Each of them can be applied to any input GPIO. However, applying multiple filters to the same GPIO doesn't make difference from one. You can create the filter handle by calling :cpp:func:`gpio_new_flex_glitch_filter`. All the configurations for a flexible glitch filter are listed in the :cpp:type:`gpio_flex_glitch_filter_config_t` structure.
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- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` sets the GPIO that will be applied the flex glitch filter.
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- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` sets the GPIO that will be applied to the flex glitch filter.
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- :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` and :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` are the key parameters of the glitch filter. During :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`, any pulse whose width is shorter than :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` will be discarded. Please note that, you can't set :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` bigger than :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`.
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER and SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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Please note, the "pin glitch filter" and "flex glitch filter" are independent. You can enable both of them for the same GPIO.
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Please note, the ``pin glitch filter`` and ``flex glitch filter`` are independent. You can enable both of them for the same GPIO.
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The glitch filter is disabled by default, and can be enabled by calling :cpp:func:`gpio_glitch_filter_enable`. To recycle the filter, you can call :cpp:func:`gpio_del_glitch_filter`. Please note, before deleting the filter, you should disable it first by calling :cpp:func:`gpio_glitch_filter_disable`.
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@ -71,7 +70,6 @@ API Reference - Normal GPIO
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.. include-build-file:: inc/rtc_io.inc
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.. include-build-file:: inc/rtc_io_types.inc
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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API Reference - GPIO Glitch Filter
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@ -43,6 +43,7 @@ A GPTimer instance is represented by :cpp:type:`gptimer_handle_t`. The driver be
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To install a timer instance, there is a configuration structure that needs to be given in advance: :cpp:type:`gptimer_config_t`:
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- :cpp:member:`gptimer_config_t::clk_src` selects the source clock for the timer. The available clocks are listed in :cpp:type:`gptimer_clock_source_t`, you can only pick one of them. For the effect on power consumption of different clock source, please refer to Section :ref:`gptimer-power-management`.
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- :cpp:member:`gptimer_config_t::direction` sets the counting direction of the timer, supported directions are listed in :cpp:type:`gptimer_count_direction_t`, you can only pick one of them.
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- :cpp:member:`gptimer_config_t::resolution_hz` sets the resolution of the internal counter. Each count step is equivalent to **1 / resolution_hz** seconds.
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@ -7,13 +7,13 @@ SPI Slave driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
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Overview of {IDF_TARGET_NAME}'s SPI peripherals
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-----------------------------------------------
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On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has independent signal bus with the same name.
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On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has an independent signal bus with the same name.
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.. only:: esp32
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.. note::
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On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
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On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
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Terminology
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-----------
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@ -120,91 +120,102 @@ GPIO Matrix and IO_MUX
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The IO_MUX pins for SPI buses are given below.
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+----------+------+------+
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| Pin Name | SPI2 | SPI3 |
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+ +------+------+
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| | GPIO Number |
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+==========+======+======+
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| CS0* | 15 | 5 |
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+----------+------+------+
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| SCLK | 14 | 18 |
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+----------+------+------+
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| MISO | 12 | 19 |
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+----------+------+------+
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| MOSI | 13 | 23 |
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+----------+------+------+
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| QUADWP | 2 | 22 |
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+----------+------+------+
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| QUADHD | 4 | 21 |
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+----------+------+------+
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.. list-table::
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:widths: 40 30 30
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:header-rows: 1
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* - Pin Name
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- GPIO Number (SPI2)
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- GPIO Number (SPI3)
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* - CS0*
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- 15
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- 5
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* - SCLK
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- 14
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- 18
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* - MISO
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- 12
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- 19
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* - MOSI
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- 13
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- 23
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* - QUADWP
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- 2
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- 22
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* - QUADHD
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- 4
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- 21
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.. only:: not esp32
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Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
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When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
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When an SPI Host is set to 80 MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same compared to routing them via IO_MUX.
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The IO_MUX pins for SPI buses are given below.
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.. only:: esp32s2 or esp32s3
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+----------+------+------+
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| Pin Name | SPI2 | SPI3 |
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+ +------+------+
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| | GPIO Number |
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+==========+======+======+
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| CS0* | 10 | N/A |
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+----------+------+------+
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| SCLK | 12 | N/A |
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+----------+------+------+
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| MISO | 13 | N/A |
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+----------+------+------+
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| MOSI | 11 | N/A |
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+----------+------+------+
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| QUADWP | 14 | N/A |
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+----------+------+------+
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| QUADHD | 9 | N/A |
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+----------+------+------+
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.. list-table::
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:widths: 40 30
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:header-rows: 1
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* - Pin Name
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- GPIO Number (SPI2)
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* - CS0*
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- 10
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* - SCLK
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- 12
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* - MISO
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- 13
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* - MOSI
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- 11
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* - QUADWP
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- 14
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* - QUADHD
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- 9
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.. only:: esp32c2 or esp32c3
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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| | GPIO Number |
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+==========+=============+
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| CS0* | 10 |
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+----------+-------------+
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| SCLK | 6 |
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+----------+-------------+
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| MISO | 2 |
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+----------+-------------+
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| MOSI | 7 |
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+----------+-------------+
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| QUADWP | 5 |
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+----------+-------------+
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| QUADHD | 4 |
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+----------+-------------+
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.. list-table::
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:widths: 40 30
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:header-rows: 1
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* - Pin Name
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- GPIO Number (SPI2)
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* - CS0*
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- 10
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* - SCLK
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- 6
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* - MISO
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- 2
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* - MOSI
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- 7
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* - QUADWP
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- 5
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* - QUADHD
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- 4
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.. only:: esp32c6
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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| | GPIO Number |
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+==========+=============+
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| CS0* | 16 |
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+----------+-------------+
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| SCLK | 6 |
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+----------+-------------+
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| MISO | 2 |
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+----------+-------------+
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| MOSI | 7 |
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+----------+-------------+
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| QUADWP | 5 |
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+----------+-------------+
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| QUADHD | 4 |
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+----------+-------------+
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.. list-table::
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:widths: 40 30
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:header-rows: 1
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* - Pin Name
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- GPIO Number (SPI2)
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* - CS0*
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- 16
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* - SCLK
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- 6
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* - MISO
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- 2
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* - MOSI
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- 7
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* - QUADWP
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- 5
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* - QUADHD
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- 4
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* Only the first Device attached to the bus can use the CS0 pin.
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@ -95,7 +95,7 @@ GPIO 捆绑包操作
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- 清除 GPIO 位：``clr_bit_gpio_out imm[7:0]``
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- 注意：立即数宽度取决于专用 GPIO 通道的数量
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.. only:: esp32c2 or esp32c3
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.. only:: esp32c2 or esp32c3 or esp32c6
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- 设置 GPIO 位：``csrrsi rd, csr, imm[4:0]``
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- 清除 GPIO 位：``csrrci rd, csr, imm[4:0]``
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@ -109,9 +109,11 @@ GPIO 捆绑包操作
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有关支持的专用 GPIO 指令的详细信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *处理器指令拓展 (PIE)（稍后发布）* [`PDF <{IDF_TARGET_TRM_CN_URL}#pie>`__].
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.. only:: esp32c2 or esp32c3
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.. only:: esp32c2 or esp32c3 or esp32c6
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有关支持的专用 GPIO 指令的详细信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_CN_URL}#riscvcpu>`__].
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通过汇编操作专用 GPIO 的示例代码存放在 ESP-IDF 示例项目的 :example:`peripherals/dedicated_gpio` 目录下。示例演示了如何通过汇编操作专用 GPIO 来模拟 UART、I2C 和 SPI 总线。
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有关支持的专用 GPIO 指令的详细信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *ESP-RISC-V CPU* [`PDF <{IDF_TARGET_TRM_CN_URL}#riscvcpu>`__]。
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一些专用的 CPU 指令也包含在 `hal/dedic_gpio_cpu_ll.h` 中，作为辅助内联函数。
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@ -13,7 +13,7 @@ GPIO 汇总
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.. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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当 GPIO 连接到 "RTC" 低功耗和模拟子系统时，{IDF_TARGET_NAME} 芯片还单独支持 "RTC GPIO"。可在以下情况时使用这些管脚功能：
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当 GPIO 连接到 RTC 低功耗和模拟子系统时，{IDF_TARGET_NAME} 芯片还单独支持 RTC GPIO。可在以下情况时使用这些管脚功能：
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.. list::
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@ -26,28 +26,28 @@ GPIO 汇总
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GPIO 毛刺过滤器
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---------------
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{IDF_TARGET_NAME} 内置硬件的过滤器可以帮助过滤掉 GPIO 输入端口上的毛刺信号, 这可以一定程度上避免错误地触发中断或者是错把噪声当成有效的外设信号。
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{IDF_TARGET_NAME} 内置硬件的过滤器可以过滤掉 GPIO 输入端口上的毛刺信号，在一定程度上避免错误触发中断或者是错把噪声当成有效的外设信号。
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
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每个 GPIO 都可以使用独立的毛刺过滤器，该过滤器可以将那些脉冲宽度窄于 **2** 个采样时钟的信号剔除掉， 并且这个宽度是无法配置的。GPIO 对输入信号的采样时钟通常是 IO-MUX 的时钟源。在驱动中， 我们将此类过滤器称为 “pin glitch filter“。 你可以调用 :cpp:func:`gpio_new_pin_glitch_filter` 函数来创建一个过滤器句柄。过滤器的相关配置保存在 :cpp:type:`gpio_pin_glitch_filter_config_t` 结构体中。
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每个 GPIO 都可以使用独立的毛刺过滤器，该过滤器可以将那些脉冲宽度窄于 **2** 个采样时钟的信号剔除掉，该宽度无法配置。GPIO 对输入信号的采样时钟通常是 IO_MUX 的时钟源。在驱动中，此类过滤器称为 ``管脚毛刺过滤器``。可以调用 :cpp:func:`gpio_new_pin_glitch_filter` 函数创建一个过滤器句柄。过滤器的相关配置保存在 :cpp:type:`gpio_pin_glitch_filter_config_t` 结构体中。
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- :cpp:member:`gpio_pin_glitch_filter_config_t::gpio_num` 设置哪个 GPIO 需要开启毛刺过滤器。
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- :cpp:member:`gpio_pin_glitch_filter_config_t::gpio_num` 设置启用毛刺过滤器的 GPIO 编号。
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.. only:: SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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{IDF_TARGET_FLEX_GLITCH_FILTER_NUM:default="8"}
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{IDF_TARGET_NAME} 提供了 {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} 个灵活的毛刺过滤器， 被过滤信号的脉冲宽度可以由软件进行配置。我们称此类过滤器为 "flex flitch filter"。每个过滤器可以分配给任意一个 GPIO, 但是将多个过滤器应用在同一个 GPIO 上并不能带来更好的效果。你可以调用 :cpp:func:`gpio_new_flex_glitch_filter` 函数来创建一个过滤器句柄。过滤器的相关配置保存在 :cpp:type:`gpio_flex_glitch_filter_config_t` 结构体中。
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{IDF_TARGET_NAME} 提供了 {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} 个灵活的毛刺过滤器，被过滤信号的脉冲宽度可以由软件进行配置。此类过滤器则称为 ``灵活毛刺过滤器``。每个过滤器都可以应用于任意 GPIO 输入，然而，将多个过滤器应用于同一 GPIO 上效果并不会叠加。可以调用 :cpp:func:`gpio_new_flex_glitch_filter` 函数来创建一个过滤器句柄。过滤器的相关配置保存在 :cpp:type:`gpio_flex_glitch_filter_config_t` 结构体中。
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- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` 设置哪个 GPIO 需要使用毛刺过滤器。
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- :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` 和 :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` 是毛刺过滤器的关键参数。在:cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` 时间内，任何脉冲信号，如果它的宽度小于 :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns`, 那么该脉冲信号就会被滤除掉。:cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` 的值不能大于 :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`。
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- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` 设置启用毛刺过滤器的 GPIO 编号。
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- :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` 和 :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` 是毛刺过滤器的关键参数。在:cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` 时间内，任何脉冲信号，如果它的宽度小于 :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` ，那么该脉冲信号就会被滤除掉。:cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` 的值不能大于 :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`。
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER and SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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请注意， "pin glitch filter" 和 "flex glitch filter" 是各自独立的，你可以给同一个 GPIO 同时启用他们两种滤波器。
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请注意，``管脚毛刺过滤器`` 和 ``灵活毛刺过滤器`` 是各自独立的，支持为同一 GPIO 同时启用这两种过滤器。
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毛刺滤波器默认情况下是处于关闭状态的， 你需要调用 :cpp:func:`gpio_glitch_filter_enable` 去使能它。如果要回收这个过滤器，你可以调用 :cpp:func:`gpio_del_glitch_filter` 函数。注意， 在你回收过滤器句柄之前， 请确保它是处于关闭状态的，如果不是，你需要调用 :cpp:func:`gpio_glitch_filter_disable`。
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毛刺过滤器默认关闭，可调用 :cpp:func:`gpio_glitch_filter_enable` 使能过滤器。如需回收这个过滤器，可以调用 :cpp:func:`gpio_del_glitch_filter` 函数。在回收句柄前，请确保过滤器处于关闭状态，否则需调用 :cpp:func:`gpio_glitch_filter_disable`。
|
||||
|
||||
|
||||
应用示例
|
||||
|
||||
@ -7,21 +7,13 @@ SPI 从机驱动程序控制在 {IDF_TARGET_NAME} 中作为从机的 SPI 外设
|
||||
{IDF_TARGET_NAME} 中 SPI 外设概述
|
||||
-----------------------------------------------
|
||||
|
||||
.. only:: esp32 or esp32s2 or esp32s3
|
||||
{IDF_TARGET_NAME} 集成了 {SOC_SPI_PERIPH_NUM} 个通用的 SPI 控制器。该控制器具有与之同名的独立总线信号。
|
||||
|
||||
{IDF_TARGET_NAME} 集成了 2 个通用的 SPI 控制器，可用作片外 SPI 主机驱动的从机节点。
|
||||
.. only:: esp32
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
- SPI2，有时也称为 HSPI
|
||||
- SPI3，有时也称为 VSPI
|
||||
|
||||
SPI2 和 SPI3 各自具有一个与之同名的独立总线信号。
|
||||
|
||||
.. only:: esp32c3 or esp32c2
|
||||
|
||||
{IDF_TARGET_NAME} 集成了 1 个通用的 SPI 控制器，可用作片外 SPI 主机驱动的从机节点。该控制器为 SPI2，具有一个与之同名的独立总线信号。
|
||||
.. note::
|
||||
|
||||
在 ESP32 中，HSPI 为 SPI2，VSPI 为 SPI3。
|
||||
|
||||
术语
|
||||
-----------
|
||||
@ -111,16 +103,14 @@ SPI 传输事务
|
||||
|
||||
如果传输长度超过缓存区长度，则只有在 :cpp:member:`spi_slave_transaction_t::length` 中指定的初始比特数会被发送和接收。此时， :cpp:member:`spi_slave_transaction_t::trans_len` 被设置为 :cpp:member:`spi_slave_transaction_t::length` 而非实际传输事务长度。若需满足实际传输事务长度的要求，请将 :cpp:member:`spi_slave_transaction_t::length` 设置为大于 :cpp:member:`spi_slave_transaction_t::trans_len` 预期最大值的值。如果传输长度短于缓存区长度，则只传输与缓存区长度相等的数据。
|
||||
|
||||
.. only:: esp32
|
||||
GPIO 交换矩阵和 IO_MUX
|
||||
----------------------
|
||||
|
||||
GPIO 交换矩阵和 IO_MUX
|
||||
----------------------
|
||||
.. only:: esp32
|
||||
|
||||
{IDF_TARGET_NAME} 的大多数外设信号都直接连接到其专用的 IO_MUX 管脚。不过，也可以使用 GPIO 交换矩阵，将信号路由到任何可用的其他管脚。
|
||||
|
||||
如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。GPIO 交换矩阵以 80 MHz 的频率对所有信号进行采样，并在 GPIO 和外设之间进行传输。
|
||||
|
||||
如果已经配置过驱动程序，所有的 SPI 信号都已路由到专用的 IO_MUX 管脚，或者根本没有连接到任何管脚，那么 GPIO 交换矩阵将被绕过。
|
||||
如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。如果已经配置过驱动程序，所有 SPI 信号都已路由到专用 IO_MUX 管脚，或者没有连接到任何管脚，那么 GPIO 交换矩阵将被绕过。
|
||||
|
||||
GPIO 交换矩阵提高了信号传输的灵活性，但也增大了 MISO 信号的输入延迟，导致违反 MISO 设置时间的可能性更高。如需 SPI 高速运行，请使用专用的 IO_MUX 管脚。
|
||||
|
||||
@ -130,35 +120,104 @@ SPI 传输事务
|
||||
|
||||
下表列出了 SPI 总线的 IO_MUX 管脚。
|
||||
|
||||
.. only:: esp32
|
||||
.. list-table::
|
||||
:widths: 40 30 30
|
||||
:header-rows: 1
|
||||
|
||||
.. list-table::
|
||||
:widths: 40 30 30
|
||||
:header-rows: 1
|
||||
* - 管脚名称
|
||||
- GPIO 编号 (SPI2)
|
||||
- GPIO 编号 (SPI3)
|
||||
* - CS0*
|
||||
- 15
|
||||
- 5
|
||||
* - SCLK
|
||||
- 14
|
||||
- 18
|
||||
* - MISO
|
||||
- 12
|
||||
- 19
|
||||
* - MOSI
|
||||
- 13
|
||||
- 23
|
||||
* - QUADWP
|
||||
- 2
|
||||
- 22
|
||||
* - QUADHD
|
||||
- 4
|
||||
- 21
|
||||
|
||||
* - 管脚名称
|
||||
- GPIO 编号 (SPI2)
|
||||
- GPIO 编号 (SPI3)
|
||||
* - CS0*
|
||||
- 15
|
||||
- 5
|
||||
* - SCLK
|
||||
- 14
|
||||
- 18
|
||||
* - MISO
|
||||
- 12
|
||||
- 19
|
||||
* - MOSI
|
||||
- 13
|
||||
- 23
|
||||
* - QUADWP
|
||||
- 2
|
||||
- 22
|
||||
* - QUADHD
|
||||
- 4
|
||||
- 21
|
||||
.. only:: not esp32
|
||||
|
||||
* 只有连接到总线上的第一个从机设备可以使用 CS0 管脚。
|
||||
{IDF_TARGET_NAME} 的大多数外设信号都直接连接到其专用的 IO_MUX 管脚。不过，也可以使用 GPIO 交换矩阵，将信号路由到任何可用的其他管脚。如果通过 GPIO 交换矩阵路由了至少一个信号，则所有信号都将通过 GPIO 交换矩阵路由。
|
||||
|
||||
当 SPI 主机频率配置为 80 MHz 或更低时，则通过 GPIO 交换矩阵或 IO_MUX 路由 SPI 管脚效果相同。
|
||||
|
||||
下表列出了 SPI 总线的 IO_MUX 管脚。
|
||||
|
||||
.. only:: esp32s2 or esp32s3
|
||||
|
||||
.. list-table::
|
||||
:widths: 40 30
|
||||
:header-rows: 1
|
||||
|
||||
* - 管脚名称
|
||||
- GPIO 编号 (SPI2)
|
||||
* - CS0*
|
||||
- 10
|
||||
* - SCLK
|
||||
- 12
|
||||
* - MISO
|
||||
- 13
|
||||
* - MOSI
|
||||
- 11
|
||||
* - QUADWP
|
||||
- 14
|
||||
* - QUADHD
|
||||
- 9
|
||||
|
||||
.. only:: esp32c2 or esp32c3
|
||||
|
||||
.. list-table::
|
||||
:widths: 40 30
|
||||
:header-rows: 1
|
||||
|
||||
* - 管脚名称
|
||||
- GPIO 编号 (SPI2)
|
||||
* - CS0*
|
||||
- 10
|
||||
* - SCLK
|
||||
- 6
|
||||
* - MISO
|
||||
- 2
|
||||
* - MOSI
|
||||
- 7
|
||||
* - QUADWP
|
||||
- 5
|
||||
* - QUADHD
|
||||
- 4
|
||||
|
||||
.. only:: esp32c6
|
||||
|
||||
.. list-table::
|
||||
:widths: 40 30
|
||||
:header-rows: 1
|
||||
|
||||
* - 管脚名称
|
||||
- GPIO 编号 (SPI2)
|
||||
* - CS0*
|
||||
- 16
|
||||
* - SCLK
|
||||
- 6
|
||||
* - MISO
|
||||
- 2
|
||||
* - MOSI
|
||||
- 7
|
||||
* - QUADWP
|
||||
- 5
|
||||
* - QUADHD
|
||||
- 4
|
||||
|
||||
* 只有连接到总线上的第一个从机设备可以使用 CS0 管脚。
|
||||
|
||||
|
||||
速度与时钟
|
||||
@ -196,7 +255,7 @@ SPI 从机的工作频率最高可达 {IDF_TARGET_MAX_FREQ} MHz。如果时钟
|
||||
.. list-table::
|
||||
:widths: 30 40 40
|
||||
:header-rows: 1
|
||||
|
||||
|
||||
* - /
|
||||
- MISO 输出延迟 (ns)
|
||||
- 频率限制 (MHz)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user