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spi: bringup c6 spi master & slave driver support

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This commit is contained in:
wanlei 2022-11-15 15:40:34 +08:00
parent 6a8f528e08
commit 3aeedc2ad3
28 changed files with 160 additions and 168 deletions
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11
components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
View File

@ -115,6 +115,17 @@
#define GPIO_DELAY 0
#define ESP_SPI_SLAVE_TV 0
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32C6
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI2_HOST
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS 10 //the IOMUX pin of SPI2 CS0&CS1 is Pin_16&17 which is same from UART Tx&Rx Pin
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#endif
#define GET_DMA_CHAN(HOST) (HOST)

3
components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
View File

@ -11,7 +11,6 @@
#include "esp_rom_gpio.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
int test_freq_default[]=TEST_FREQ_DEFAULT();
const char MASTER_TAG[] = "test_master";
@ -250,5 +249,3 @@ void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_
master_send_buf[i] = rand() % 256;
}
}
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)

53
components/driver/test_apps/spi/master/main/test_spi_master.c
View File

@ -24,7 +24,6 @@
#include "test_spi_utils.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
const static char TAG[] = "test_spi";
// There is no input-only pin except on esp32 and esp32s2
@ -597,8 +596,7 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)"
TEST_ESP_OK(spi_bus_free(host));
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
//IDF-5146
DRAM_ATTR static uint32_t data_dram[80] = {0};
//force to place in code area.
static const uint8_t data_drom[320 + 3] = {
@ -631,18 +629,8 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
ESP_LOGI(TAG, "dram: %p", data_dram);
ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc);
#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
uint32_t *data_iram = (uint32_t *)heap_caps_malloc(324, MALLOC_CAP_EXEC);
TEST_ASSERT(data_iram != NULL);
TEST_ASSERT(esp_ptr_executable(data_iram) || esp_ptr_in_iram(data_iram) || esp_ptr_in_diram_iram(data_iram));
ESP_LOGI(TAG, "iram: %p", data_iram);
#endif
srand(52);
for (int i = 0; i < 320 / 4; i++) {
#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
data_iram[i] = rand();
#endif
data_dram[i] = rand();
data_malloc[i] = rand();
}
@ -660,42 +648,24 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
//connect MOSI to two devices breaks the output, fix it.
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
#define TEST_REGION_SIZE 5
#define TEST_REGION_SIZE 2
static spi_transaction_t trans[TEST_REGION_SIZE];
int x;
memset(trans, 0, sizeof(trans));
#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
trans[0].length = 320 * 8,
trans[0].tx_buffer = data_iram;
trans[0].rx_buffer = data_malloc + 1;
trans[0].tx_buffer = data_malloc + 2;
trans[0].rx_buffer = data_dram;
trans[1].length = 320 * 8,
trans[1].tx_buffer = data_dram;
trans[1].rx_buffer = data_iram;
trans[2].length = 320 * 8,
trans[2].tx_buffer = data_drom;
trans[2].rx_buffer = data_iram;
#endif
trans[3].length = 320 * 8,
trans[3].tx_buffer = data_malloc + 2;
trans[3].rx_buffer = data_dram;
trans[4].length = 4 * 8,
trans[4].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
uint32_t *ptr = (uint32_t *)trans[4].rx_data;
trans[1].length = 4 * 8,
trans[1].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
uint32_t *ptr = (uint32_t *)trans[1].rx_data;
*ptr = 0x54545454;
ptr = (uint32_t *)trans[4].tx_data;
ptr = (uint32_t *)trans[1].tx_data;
*ptr = 0xbc124960;
//Queue all transactions.
#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
for (x = 0; x < TEST_REGION_SIZE; x++) {
#else
for (x = 3; x < TEST_REGION_SIZE; x++) {
#endif
ESP_LOGI(TAG, "transmitting %d...", x);
ret = spi_device_transmit(spi, &trans[x]);
TEST_ASSERT(ret == ESP_OK);
@ -708,11 +678,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK);
free(data_malloc);
#ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
free(data_iram);
#endif
}
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
//this part tests 3 DMA issues in master mode, full-duplex in IDF2.1
// 1. RX buffer not aligned (start and end)
@ -1459,7 +1425,7 @@ TEST_CASE("spi_speed", "[spi]")
#define DUMMY_CS_PINS() {0, 1, 4, 5, 8, 9}
#endif //CONFIG_IDF_TARGET_ESP32
#define CS_REAL_DEV SPI2_IOMUX_PIN_NUM_CS
#define CS_REAL_DEV PIN_NUM_CS
#define TEST_TRANS_LEN 48
void test_add_device_master(void)
@ -1559,4 +1525,3 @@ void test_add_device_slave(void)
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test multiple devices", "[spi_ms][test_env=generic_multi_device]", test_add_device_master, test_add_device_slave);
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)

1
components/driver/test_apps/spi/master/pytest_spi_master.py
View File

@ -5,6 +5,7 @@ import pytest
# If `test_env` is define, should not run on generic runner
@pytest.mark.esp32c6
@pytest.mark.supported_targets
@pytest.mark.generic
def test_master_single_dev(case_tester) -> None: # type: ignore

1
components/driver/test_apps/spi/master/sdkconfig.defaults.esp32
View File

@ -2,6 +2,7 @@ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
CONFIG_XTAL_FREQ_AUTO=y
CONFIG_SPI_FLASH_SHARE_SPI1_BUS=y
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_esp32_flash.csv"
CONFIG_PARTITION_TABLE_FILENAME="partition_table_esp32_flash.csv"

4
components/driver/test_apps/spi/slave/main/test_spi_slave.c
View File

@ -262,7 +262,7 @@ TEST_CASE("test slave send unaligned","[spi]")
#endif // #if (TEST_SPI_PERIPH_NUM >= 2)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2, ESP32C6)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
#if (TEST_SPI_PERIPH_NUM == 1)
//These tests are for chips which only have 1 SPI controller
/********************************************************************************
@ -386,4 +386,4 @@ static void unaligned_test_slave(void)
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][test_env=generic_multi_device][timeout=120]", unaligned_test_master, unaligned_test_slave);
#endif //#if (TEST_SPI_PERIPH_NUM == 1)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)

2
components/driver/test_apps/spi/slave/main/test_spi_slave_queue.c
View File

@ -22,7 +22,6 @@
#define TEST_BUF_SIZE 32
#define TEST_TIMES 4
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
static void test_master(void)
{
@ -216,4 +215,3 @@ static void test_slave(void)
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Reset_Queue_Test", "[spi_ms][timeout=120]", test_master, test_slave);
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)

1
components/driver/test_apps/spi/slave/pytest_spi_slave.py
View File

@ -5,6 +5,7 @@ import pytest
# If `test_env` is define, should not run on generic runner
@pytest.mark.esp32c6
@pytest.mark.supported_targets
@pytest.mark.generic
def test_slave_single_dev(case_tester) -> None: # type: ignore

4
components/driver/test_apps/spi/slave_hd/main/test_spi_slave_hd.c
View File

@ -589,7 +589,7 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
#if (TEST_SPI_PERIPH_NUM == 1)
//These tests are for chips which only have 1 SPI controller
/********************************************************************************
@ -883,6 +883,4 @@ TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=generic_multi
#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2

1
components/driver/test_apps/spi/slave_hd/pytest_spi_slave_hd.py
View File

@ -5,6 +5,7 @@ import pytest
# If `test_env` is define, should not run on generic runner
@pytest.mark.esp32c6
@pytest.mark.supported_targets
@pytest.mark.generic
def test_slave_hd_single_dev(case_tester) -> None: # type: ignore

10
components/hal/esp32c6/include/hal/spi_ll.h
View File

@ -24,6 +24,7 @@
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#include "soc/pcr_struct.h"
#ifdef __cplusplus
extern "C" {
@ -111,9 +112,8 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
hw->slave.val = 0;
hw->user.val = 0;
hw->clk_gate.clk_en = 1;
hw->clk_gate.mst_clk_active = 1;
hw->clk_gate.mst_clk_sel = 1;
PCR.spi2_clkm_conf.spi2_clkm_en = 1;
PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
hw->dma_conf.val = 0;
hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
@ -1044,7 +1044,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw)
*/
static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
{
hw->dma_int_raw.trans_done = 0;
hw->dma_int_clr.trans_done = 1;
}
/**
@ -1054,7 +1054,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
{
hw->dma_int_raw.trans_done = 1;
hw->dma_int_set.trans_done_int_set = 1;
}
/**

5
components/idf_test/include/esp32c6/idf_performance_target.h
View File

@ -14,3 +14,8 @@
#define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 18000
#define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 27000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 45
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 40
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 115
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 110

14
components/soc/esp32c6/include/soc/spi_pins.h
View File

@ -8,12 +8,12 @@
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 12
#define SPI_IOMUX_PIN_NUM_CS 14
#define SPI_IOMUX_PIN_NUM_MOSI 16
#define SPI_IOMUX_PIN_NUM_CLK 15
#define SPI_IOMUX_PIN_NUM_MISO 17
#define SPI_IOMUX_PIN_NUM_WP 13
#define SPI_IOMUX_PIN_NUM_CS 24
#define SPI_IOMUX_PIN_NUM_CLK 29
#define SPI_IOMUX_PIN_NUM_MOSI 30
#define SPI_IOMUX_PIN_NUM_MISO 25
#define SPI_IOMUX_PIN_NUM_WP 26
#define SPI_IOMUX_PIN_NUM_HD 28
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
@ -21,6 +21,6 @@
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 10
#define SPI2_IOMUX_PIN_NUM_CS 16
#endif

4
docs/docs_not_updated/esp32c6.txt
View File

@ -100,7 +100,6 @@ api-reference/peripherals/hmac
api-reference/peripherals/usb_device
api-reference/peripherals/sdspi_host
api-reference/peripherals/dac
api-reference/peripherals/spi_slave
api-reference/peripherals/gptimer
api-reference/peripherals/pcnt
api-reference/peripherals/touch_element
@ -108,17 +107,14 @@ api-reference/peripherals/lcd
api-reference/peripherals/secure_element
api-reference/peripherals/ledc
api-reference/peripherals/temp_sensor
api-reference/peripherals/spi_features
api-reference/peripherals/sdio_slave
api-reference/peripherals/clk_tree
api-reference/peripherals/sdm
api-reference/peripherals/touch_pad
api-reference/peripherals/adc_calibration
api-reference/peripherals/spi_slave_hd
api-reference/peripherals/ds
api-reference/peripherals/dedic_gpio
api-reference/peripherals/sd_pullup_requirements
api-reference/peripherals/spi_master
api-reference/peripherals/index
api-reference/peripherals/sdmmc_host
api-reference/peripherals/uart

47
docs/en/api-reference/peripherals/spi_master.rst
View File

@ -7,7 +7,7 @@ SPI Master driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
Overview of {IDF_TARGET_NAME}'s SPI peripherals
-----------------------------------------------
{IDF_TARGET_MAX_PERIPH_NUM:default="4", esp32c3="3", esp32c2="3"}
{IDF_TARGET_MAX_PERIPH_NUM:default="4", esp32c3="3", esp32c2="3", esp32c6="3"}
{IDF_TARGET_SPI2_CS_NUM:default="6", esp32="3"}
{IDF_TARGET_SPI3_CS_NUM:default="3"}
@ -32,7 +32,7 @@ Overview of {IDF_TARGET_NAME}'s SPI peripherals
- SPI2 and SPI3 are general purpose SPI controllers. They are open to users. SPI2 and SPI3 have independent signal buses with the same respective names. SPI2 has {IDF_TARGET_SPI2_CS_NUM} CS lines. SPI3 has {IDF_TARGET_SPI3_CS_NUM} CS lines. Each CS line can be used to drive one SPI slave.
.. only:: esp32c3 or esp32c2
.. only:: esp32c3 or esp32c2 or esp32c6
- SPI2 is a general purpose SPI controller. It has an independent signal bus with the same name. The bus has {IDF_TARGET_SPI2_CS_NUM} CS lines to drive up to {IDF_TARGET_SPI2_CS_NUM} SPI slaves.
@ -230,7 +230,7 @@ If using more than one data lines to transmit, please set `SPI_DEVICE_HALFDUPLEX
Half-duplex transactions with both read and write phases are not supported when using DMA. For details and workarounds, see :ref:`spi_known_issues`.
.. only:: esp32s3 or esp32c3 or esp32c2
.. only:: esp32s3 or esp32c3 or esp32c2 or esp32c6
.. note::
@ -423,7 +423,7 @@ GPIO Matrix and IO_MUX
* Only the first Device attached to the bus can use the CS0 pin.
.. only:: esp32s2 or esp32s3
.. only:: not esp32
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
@ -431,6 +431,8 @@ GPIO Matrix and IO_MUX
The IO_MUX pins for SPI buses are given below.
.. only:: esp32s2 or esp32s3
+----------+------+------+
| Pin Name | SPI2 | SPI3 |
+ +------+------+
@ -449,16 +451,8 @@ GPIO Matrix and IO_MUX
| QUADHD | 9 | N/A |
+----------+------+------+
* Only the first Device attached to the bus can use the CS0 pin.
.. only:: esp32c2 or esp32c3
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
The IO_MUX pins for SPI buses are given below.
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
@ -468,18 +462,39 @@ GPIO Matrix and IO_MUX
+----------+-------------+
| SCLK | 6 |
+----------+-------------+
| MISO | 2 |
+----------+-------------+
| MOSI | 7 |
+----------+-------------+
| QUADWP | 5 |
| MISO | 2 |
+----------+-------------+
| QUADHD | 4 |
+----------+-------------+
| QUADWP | 5 |
+----------+-------------+
.. only:: esp32c6
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
| | GPIO Number |
+==========+=============+
| CS0* | 16 |
+----------+-------------+
| SCLK | 6 |
+----------+-------------+
| MOSI | 7 |
+----------+-------------+
| MISO | 2 |
+----------+-------------+
| QUADHD | 4 |
+----------+-------------+
| QUADWP | 5 |
+----------+-------------+
.. only:: not esp32
* Only the first Device attached to the bus can use the CS0 pin.
.. _speed_considerations:
Transfer Speed Considerations

46
docs/en/api-reference/peripherals/spi_slave.rst
View File

@ -7,21 +7,13 @@ SPI Slave driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
Overview of {IDF_TARGET_NAME}'s SPI peripherals
-----------------------------------------------
.. only:: esp32 or esp32s2 or esp32s3
On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has independent signal bus with the same name.
{IDF_TARGET_NAME} integrates two general purpose SPI controllers which can be used as slave nodes driven by an off-chip SPI master.
.. only:: esp32
.. only:: esp32
- SPI2, sometimes referred to as HSPI
- SPI3, sometimes referred to as VSPI
SPI2 and SPI3 have independent signal buses with the same respective names.
.. only:: esp32c3 or esp32c2
{IDF_TARGET_NAME} integrates one general purpose SPI controller which can be used as a slave node driven by an off-chip SPI master. The controller is called SPI2 and has an independent signal bus with the same name.
.. note::
On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
Terminology
-----------
@ -146,7 +138,7 @@ GPIO Matrix and IO_MUX
| QUADHD | 4 | 21 |
+----------+------+------+
.. only:: esp32s2 or esp32s3
.. only:: not esp32
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
@ -154,6 +146,8 @@ GPIO Matrix and IO_MUX
The IO_MUX pins for SPI buses are given below.
.. only:: esp32s2 or esp32s3
+----------+------+------+
| Pin Name | SPI2 | SPI3 |
+ +------+------+
@ -174,12 +168,6 @@ GPIO Matrix and IO_MUX
.. only:: esp32c2 or esp32c3
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
The IO_MUX pins for SPI buses are given below.
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
@ -198,6 +186,26 @@ GPIO Matrix and IO_MUX
| QUADHD | 4 |
+----------+-------------+
.. only:: esp32c6
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
| | GPIO Number |
+==========+=============+
| CS0* | 16 |
+----------+-------------+
| SCLK | 6 |
+----------+-------------+
| MISO | 2 |
+----------+-------------+
| MOSI | 7 |
+----------+-------------+
| QUADWP | 5 |
+----------+-------------+
| QUADHD | 4 |
+----------+-------------+
* Only the first Device attached to the bus can use the CS0 pin.

35
examples/peripherals/.build-test-rules.yml
View File

@ -164,30 +164,6 @@ examples/peripherals/sigma_delta:
disable:
- if: SOC_SDM_SUPPORTED != 1
examples/peripherals/spi_master/hd_eeprom:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target(s) not supported yet
examples/peripherals/spi_master/lcd:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target(s) not supported yet
examples/peripherals/spi_slave/receiver:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target(s) not supported yet
examples/peripherals/spi_slave/sender:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target(s) not supported yet
examples/peripherals/spi_slave_hd/append_mode/master:
disable:
- if: IDF_TARGET == "esp32c6"
@ -200,20 +176,11 @@ examples/peripherals/spi_slave_hd/append_mode/slave:
temporary: true
reason: the other targets are not tested yet
examples/peripherals/spi_slave_hd/segment_mode/seg_master:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target(s) not supported yet
examples/peripherals/spi_slave_hd/segment_mode/seg_slave:
disable:
- if: IDF_TARGET == "esp32"
temporary: true
reason: not tested yet
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target esp32c6 is not supported yet
reason: not supported
examples/peripherals/temp_sensor:
disable:

24
examples/peripherals/spi_master/hd_eeprom/README.md
View File

@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
## SPI master half duplex EEPROM example
@ -11,16 +11,16 @@
For different chip and host used, the connections may be different.
| | ESP32 | ESP32 | ESP32S2 | ESP32C2 | ESP32C3 | ESP32S3 |
| ---- | ----- | ----- | ------- | ------- | ------- | ------- |
| Host | SPI1 | HSPI | SPI2 | SPI2 | SPI2 | SPI2 |
| VCC | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V |
| GND | GND | GND | GND | GND | GND | GND |
| DO | 7 | 18 | 37 | 2 | 2 | 13 |
| DI | 8 | 23 | 35 | 7 | 7 | 11 |
| SK | 6 | 19 | 36 | 6 | 6 | 12 |
| CS | 13 | 13 | 34 | 10 | 10 | 10 |
| ORG | GND | GND | GND | GND | GND | GND |
| | ESP32 | ESP32 | ESP32S2 | ESP32C2 | ESP32C3 | ESP32C6 | ESP32S3 |
| ---- | ----- | ----- | ------- | ------- | ------- | ------- | ------- |
| Host | SPI1 | HSPI | SPI2 | SPI2 | SPI2 | SPI2 | SPI2 |
| VCC | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V | 3.3V |
| GND | GND | GND | GND | GND | GND | GND | GND |
| DO | 7 | 18 | 37 | 2 | 2 | 2 | 13 |
| DI | 8 | 23 | 35 | 7 | 7 | 7 | 11 |
| SK | 6 | 19 | 36 | 6 | 6 | 6 | 12 |
| CS | 13 | 13 | 34 | 10 | 10 | 10 | 10 |
| ORG | GND | GND | GND | GND | GND | GND | GND |
### Notes

2
examples/peripherals/spi_master/hd_eeprom/main/spi_eeprom_main.c
View File

@ -45,7 +45,7 @@
# define PIN_NUM_MOSI 35
# define PIN_NUM_CLK 36
# define PIN_NUM_CS 34
#elif defined CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
#elif defined CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
# define EEPROM_HOST SPI2_HOST
# define PIN_NUM_MISO 2

4
examples/peripherals/spi_master/lcd/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
# SPI Host Driver Example

2
examples/peripherals/spi_master/lcd/main/spi_master_example_main.c
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@ -51,7 +51,7 @@
#define PIN_NUM_DC 4
#define PIN_NUM_RST 5
#define PIN_NUM_BCKL 6
#elif defined CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
#elif defined CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
#define LCD_HOST SPI2_HOST
#define PIN_NUM_MISO 2

18
examples/peripherals/spi_slave/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
## SPI slave example
@ -7,13 +7,13 @@ These two projects illustrate the SPI Slave driver. They're supposed to be flash
The default GPIOs used in the example are the following:
| Signal | ESP32 | ESP32-S2 | ESP32-C3 |
|-----------|--------|----------|----------|
| Handshake | GPIO2 | GPIO2 | GPIO3 |
| MOSI | GPIO12 | GPIO12 | GPIO7 |
| MISO | GPIO13 | GPIO13 | GPIO2 |
| SCLK | GPIO15 | GPIO15 | GPIO6 |
| CS | GPIO14 | GPIO14 | GPIO10 |
| Signal | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-C6 |
|-----------|--------|----------|----------|----------|
| Handshake | GPIO2 | GPIO2 | GPIO3 | GPIO15 |
| MOSI | GPIO12 | GPIO12 | GPIO7 | GPIO20 |
| MISO | GPIO13 | GPIO13 | GPIO2 | GPIO19 |
| SCLK | GPIO15 | GPIO15 | GPIO6 | GPIO18 |
| CS | GPIO14 | GPIO14 | GPIO10 | GPIO9 |
Please run wires between the following GPIOs between the slave and master to make the example function:

7
examples/peripherals/spi_slave/receiver/main/app_main.c
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@ -48,6 +48,13 @@ Pins in use. The SPI Master can use the GPIO mux, so feel free to change these i
#define GPIO_SCLK 6
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C6
#define GPIO_HANDSHAKE 15
#define GPIO_MOSI 19
#define GPIO_MISO 20
#define GPIO_SCLK 18
#define GPIO_CS 9
#elif CONFIG_IDF_TARGET_ESP32S3
#define GPIO_HANDSHAKE 2
#define GPIO_MOSI 11

7
examples/peripherals/spi_slave/sender/main/app_main.c
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@ -49,6 +49,13 @@ Pins in use. The SPI Master can use the GPIO mux, so feel free to change these i
#define GPIO_SCLK 6
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C6
#define GPIO_HANDSHAKE 15
#define GPIO_MOSI 19
#define GPIO_MISO 20
#define GPIO_SCLK 18
#define GPIO_CS 9
#elif CONFIG_IDF_TARGET_ESP32S3
#define GPIO_HANDSHAKE 2
#define GPIO_MOSI 11

4
examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
See README.md in the parent directory

7
examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c
View File

@ -20,11 +20,18 @@
#define GPIO_MISO 13
#define GPIO_SCLK 12
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
#define GPIO_MOSI 7
#define GPIO_MISO 2
#define GPIO_SCLK 6
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C6
#define GPIO_MOSI 19
#define GPIO_MISO 20
#define GPIO_SCLK 18
#define GPIO_CS 9
#endif
#define MASTER_HOST SPI2_HOST

4
examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- |

7
examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c
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@ -21,11 +21,18 @@
#define GPIO_MISO 13
#define GPIO_SCLK 12
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4
#define GPIO_MOSI 7
#define GPIO_MISO 2
#define GPIO_SCLK 6
#define GPIO_CS 10
#elif CONFIG_IDF_TARGET_ESP32C6
#define GPIO_MOSI 19
#define GPIO_MISO 20
#define GPIO_SCLK 18
#define GPIO_CS 9
#endif
#define SLAVE_HOST SPI2_HOST