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spi: update spi master / slave programming guide on s3

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This commit is contained in:
Armando 2021-09-03 16:44:19 +08:00
parent 81391fb18c
commit fa34cfcc0c
2 changed files with 7 additions and 8 deletions
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10
docs/en/api-reference/peripherals/spi_master.rst
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@ -28,7 +28,7 @@ Overview of {IDF_TARGET_NAME}'s SPI peripherals
- SPI2 and SPI3 are general purpose SPI controllers, sometimes referred to as HSPI and VSPI, respectively. They are open to users. SPI2 and SPI3 have independent bus signals with the same respective names. Each bus has three CS lines to drive up to same number of SPI slaves.
.. only:: esp32s2
.. only:: esp32s2 or esp32s3
- SPI2 and SPI3 are general purpose SPI controllers. They are open to users. SPI2 and SPI3 have independent signal buses with the same respective names. SPI2 has {IDF_TARGET_SPI2_CS_NUM} CS lines. SPI3 has {IDF_TARGET_SPI3_CS_NUM} CS lines. Each CS line can be used to drive one SPI slave.
@ -439,10 +439,10 @@ The main parameter that determines the transfer speed for large transactions is
Transaction Duration
^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="28", esp32="28", esp32s2="23", esp32c3="28"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="10", esp32="10", esp32s2="9", esp32c3="10"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="25", esp32="25", esp32s2="22", esp32c3="27"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="8", esp32="8", esp32s2="8", esp32c3="9"}
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="28", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="10", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="25", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="8", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9"}
Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transaction.

5
docs/en/api-reference/peripherals/spi_slave.rst
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@ -7,7 +7,7 @@ SPI Slave driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
Overview of {IDF_TARGET_NAME}'s SPI peripherals
-----------------------------------------------
.. only:: esp32 or esp32s2
.. only:: esp32 or esp32s2 or esp32s3
{IDF_TARGET_NAME} integrates two general purpose SPI controllers which can be used as slave nodes driven by an off-chip SPI master
@ -158,7 +158,7 @@ You can also configure a GPIO pin through which the Device will signal to the Ho
SCLK Frequency Requirements
^^^^^^^^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_MAX_FREQ:default="40", esp32="10", esp32s2="40", esp32c3="60"}
{IDF_TARGET_MAX_FREQ:default="40", esp32="10", esp32s2="40", esp32c3="60", esp32s3="60}
The SPI slaves are designed to operate at up to {IDF_TARGET_MAX_FREQ} MHz. The data cannot be recognized or received correctly if the clock is too fast or does not have a 50% duty cycle.
@ -216,4 +216,3 @@ API Reference
-------------
.. include-build-file:: inc/spi_slave.inc