1. Regression introduced when refactoring on clock sources selection (0d07f859).
If channel configuration is called before timer configuration on C6, PWM signal may not be able to output.
2. Missing the improper fade parameter fix inside ledc_set_duty_and_update() function.
modem retention: Support esp32c6 wifi MAC and baseband sleep retention
sleep_modem: wifi MAC modem wakeup protect in modem state before PMU trigger sleep enable request
sleep modem: provide a interface to get whether the Modem power domain is allowed to power off during sleep
add i2c_ana master header file to project
auto beacon: release PMU's lock on root clock source (it is locked in the PLL)
wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL
clock, PMU will forcibly lock the root clock source as PLL, when the root
clock source of the software system is selected as PLL, we need to release
the root clock source locking.
When it is judged that the PLL is locked by PMU after wakeing up from the PMU
modem state, switch the root clock source to the PLL in the sleep process (a
critical section).
auto beacon: fix the failure to receive broadcast/multicast frames in modem state
When the multicast field in the beacon frame received in the PMU modem state is
True, the PMU switches to the PMU active state (the PMU waits for the HP LDO to
stabilize and then restores the MAC context) and starts to receive
broadcast/multicast frames (Broadcast/Multicast frames will be sent after a
minimum delay of 48 us after the beacon frame), because the PMU waits for the HP
LDO to stabilize too long (~154 us), which will cause broadcast/multicast frame
reception to be missed.
auto beacon: select the PLL clock source as the REGDMA backup clock source when the PMU switches to ACTIVE from MODEM state
update Digital Peripheral (M2A switch) REGDMA restore time parameter
auto beacon: fix the issue that only channel 1 can connect to AP in modem state
usb_serial_jtag: Improve the code for the issue of usb cdc device unable to work during sleep
Closes IDFGH-6887
See merge request espressif/esp-idf!20973
1. Remove RTC_CLOCK_BBPLL_POWER_ON_WITH_USB Kconfig option
During sleep, BBPLL clock always gets disabled
esp_restart does not disable BBPLL clock, so that first stage bootloader log can be printed
2. Add a new Kconfig option PM_NO_AUTO_LS_ON_USJ_CONNECTED
When this option is selected, IDF will constantly monitor USB CDC port connection status.
As long as it gets connected to a HOST, automatic light-sleep will not happen.
Closes https://github.com/espressif/esp-idf/issues/8507
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
In ESP32-C6, every peripheral reset enable bit is in different register
(unlike some of the previous SoCs) and hence they must be handled with
multiple register write operations.
This allows AES, MPI peripherals to works correctly after DS peripheral
has done some operations.
1. Concurrency might cause ESP_ERR_TIMEOUT when calling uart_wait_tx_done
2. Concurrency might cause RTS line being de-assreted during tx transmission for rs485 mode
