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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/esp32c6_h2_clk_gate_periph_rst' into 'master'
clk_gate_ll: fix issue with DS peripheral clk reset Closes IDF-6740 See merge request espressif/esp-idf!22301
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commit
f4fb62eee7
@ -10,7 +10,7 @@
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#include <stdbool.h>
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#include "soc/periph_defs.h"
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#include "soc/pcr_reg.h"
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#include "soc/dport_access.h"
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#include "soc/soc.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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@ -139,29 +139,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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case PERIPH_TEMPSENSOR_MODULE:
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return PCR_TSENS_RST_EN;
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case PERIPH_AES_MODULE:
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset also.
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return (PCR_AES_RST_EN | PCR_DS_RST_EN);
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} else {
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//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
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return PCR_AES_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_AES_RST_EN;
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case PERIPH_SHA_MODULE:
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
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} else {
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// Don't assert reset on secure boot, otherwise AES is held in reset
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return PCR_SHA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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}
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return PCR_SHA_RST_EN;
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case PERIPH_RSA_MODULE:
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if (enable == true) {
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/* also clear reset on digital signature, otherwise RSA is held in reset */
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return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
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} else {
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/* don't reset digital signature unit, as this resets AES also */
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return PCR_RSA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise RSA is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_RSA_RST_EN;
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case PERIPH_HMAC_MODULE:
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return PCR_HMAC_RST_EN;
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case PERIPH_DS_MODULE:
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@ -319,26 +314,26 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
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static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
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{
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DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
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SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
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}
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static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
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{
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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}
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static inline void periph_ll_reset(periph_module_t periph)
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{
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DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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}
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static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
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{
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return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
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DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
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return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
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REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
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}
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#ifdef __cplusplus
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@ -10,7 +10,7 @@
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#include <stdbool.h>
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#include "soc/periph_defs.h"
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#include "soc/pcr_reg.h"
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#include "soc/dport_access.h"
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -133,29 +133,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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case PERIPH_TEMPSENSOR_MODULE:
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return PCR_TSENS_RST_EN;
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case PERIPH_AES_MODULE:
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset also.
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return (PCR_AES_RST_EN | PCR_DS_RST_EN);
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} else {
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//Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
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return PCR_AES_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise AES unit is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_AES_RST_EN;
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case PERIPH_SHA_MODULE:
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
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} else {
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// Don't assert reset on secure boot, otherwise AES is held in reset
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return PCR_SHA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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}
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return PCR_SHA_RST_EN;
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case PERIPH_RSA_MODULE:
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if (enable == true) {
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/* also clear reset on digital signature, otherwise RSA is held in reset */
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return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
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} else {
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/* don't reset digital signature unit, as this resets AES also */
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return PCR_RSA_RST_EN;
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}
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if (enable == true) {
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// Clear reset on digital signature, otherwise RSA is held in reset
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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}
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return PCR_RSA_RST_EN;
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case PERIPH_HMAC_MODULE:
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return PCR_HMAC_RST_EN;
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case PERIPH_DS_MODULE:
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@ -304,14 +299,14 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
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static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
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{
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DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
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SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
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}
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static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
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{
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
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SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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}
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static inline void periph_ll_wifi_bt_module_enable_clk_clear_rst(void)
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@ -328,14 +323,14 @@ static inline void periph_ll_wifi_bt_module_disable_clk_set_rst(void)
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static inline void periph_ll_reset(periph_module_t periph)
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{
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DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
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}
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static inline bool periph_ll_periph_enabled(periph_module_t periph)
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{
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return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
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DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
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return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
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REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
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}
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static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
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