alex/esp-idf
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89 Commits

Author SHA1 Message Date
Marius Vikhammer
32fd9d6c63 s2 crypto: update perf test to use cache comp timer 
Updated S2 hardware accelerated crypto to use the cache compensated timer.

Re-enabled RSA performance test and set lower targets now that results are more stable

Closes: IDF-1174
 2020-03-23 11:30:55 +08:00
Marius Vikhammer
7e824508a9 mpi: refactor bignum into common and hw specific components 
Closes IDF-1174
 2020-03-16 19:44:30 +08:00
Marius Vikhammer
3351376a11 AES: optimize AES-GCM 
HW acceleration for GCM is now enabled by default

Closes IDF-1443
 2020-03-12 10:20:24 +08:00
Roland Dobai
15884eccf2 Add multi-target support for performance tests 2020-03-09 13:41:56 +01:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
Felipe Neves
2c612ec1dc components/freertos: using the optimized task selection on esp32s2beta 
components/freertos: cleaned up multicore option scheduler.

components/freertos:  more cleanup and test optimization to present realistic results

components/freertos: remove unused macros of optimized task selection when multicore is used
 2020-01-14 09:58:14 -03:00
Felipe Neves
77bf1ff1c0 freertos/tests: added test to evaluate scheduling time 
freertos/Kconfig: fix trailing space on optimized scheduler option

freertos/tests: moved test context variables inside of test task.

The public variables used on scheduling time test now were packed into a structure allocated on  test case task stack and passed to tasks as arguments saving RAM comsumption.
 2020-01-14 09:58:14 -03:00
Shubham Kulkarni
563175d90a mbedtls: Use SPIRAM strategy in example_test.py 2020-01-03 15:30:03 +05:30
Michael (XIAO Xufeng)
41e37ebabe ci: decrease the performance threshold for sdio throughput 2019-12-24 16:50:08 +08:00
michael
2dd12ae5f8 spi: fix speed test issues on esp32s2beta 
Also support performance value for different targets.
 2019-12-23 10:23:01 +08:00
Marius Vikhammer
c63684cf6c hw crypto: activated hardware acceleration for esp32s2beta 
Activated AES, RSA and SHA hardware acceleration for esp32s2 and enabled related unit tests.

Updated with changes made for ESP32 from 0a04034, 961f59f and caea288.

Added performance targets for esp32s2beta

Closes IDF-757
 2019-12-12 12:37:29 +08:00
Felipe Neves
f119cc58cf components/freertos: tuned performance value for ISR exit cycles to pass in test in -Og 2019-12-04 10:39:22 -03:00
Felipe Neves
bcdc35be59 components/freertos: refactor of isr_latency tests to perform full measurement 2019-12-04 10:39:22 -03:00
Felipe Neves
346b12e29a freertos/test: added spill register timer measurement test 2019-12-04 10:39:22 -03:00
Michael (XIAO Xufeng)
d158fa3f5c sdio: add unit test between host and slave 2019-12-03 22:58:42 +08:00
Angus Gratton
5b33d6cf94 Merge branch 'feature/mbedtls_add_faster_modexp' into 'master' 
mbedtls: Add a new (X^Y) mod M implementation (HAC 14.94)

Closes IDF-965

See merge request espressif/esp-idf!6418
 2019-11-06 15:51:28 +08:00
KonstantinKondrashov
e8d3b80e4b mbedtls: Add an UT for performance RSA key operations 
(New) - Montgomery exponentiation: Z = X ^ Y mod M  (HAC 14.94)
keysize = 2048 bits
RSA key operation (performance): public [21894 us], private [199119 us]
RSA key operation (performance): public [18768 us], private [189051 us]
RSA key operation (performance): public [16242 us], private [190821 us]
keysize = 3072 bits
RSA key operation (performance): public [39762 us], private [437480 us]
RSA key operation (performance): public [36550 us], private [449422 us]
RSA key operation (performance): public [40536 us], private [443451 us]
keysize = 4096 bits
RSA key operation (performance): public [65671 us], private [885215 us]
RSA key operation (performance): public [60770 us], private [880936 us]
RSA key operation (performance): public [68951 us], private [872027 us]

(Old) - Sliding-window exponentiation: Z = X ^ Y mod M  (HAC 14.85)
keysize = 2048 bits
RSA key operation (performance): public [93206 us], private [280189 us]
RSA key operation (performance): public [93060 us], private [278893 us]
RSA key operation (performance): public [97520 us], private [283252 us]
keysize = 3072 bits
RSA key operation (performance): public [293614 us], private [858157 us]
RSA key operation (performance): public [289902 us], private [843701 us]
RSA key operation (performance): public [291495 us], private [845232 us]
keysize = 4096 bits
RSA key operation (performance): public [653192 us], private [1912126 us]
RSA key operation (performance): public [656661 us], private [1901792 us]
RSA key operation (performance): public [641390 us], private [1938911 us]
 2019-11-05 16:33:11 +08:00
Ivan Grokhotkov
589a1f216f mbedtls: add SHA performance test 
Results with this revision:

SHA256 rate 2.599MB/sec Debug 240MHz SW
SHA256 rate 1.147MB/sec Release 80MHz SW
SHA256 rate 3.469MB/sec Release 240MHz SW
SHA256 rate 2.687MB/sec Release 240MHz SW + PSRAM workaround

SHA256 rate 9.433MB/sec Debug 240MHz HW rev1
SHA256 rate 3.727MB/sec Release 80MHz HW rev1
SHA256 rate 10.961MB/sec Release 240MHz HW rev1
SHA256 rate 9.966MB/sec Release 240MHz HW rev1 + PRAM workaround

SHA256 rate 10.974MB/sec Debug 240MHz HW rev3
SHA256 rate 4.362MB/sec Release 80MHz HW rev3
SHA256 rate 13.207MB/sec Release 240MHz HW rev3

Debug = Og, assertions enabled
Release = O2, assertions disabled
 2019-11-04 10:48:08 +01:00
Angus Gratton
caea2889c8 aes: Add fault injection checks when writing key to hardware 
Vulnerability reported by LimitedResults under Espressif Bug Bounty Program.
 2019-08-11 11:16:33 +10:00
xueyunfei
fa02598b5c lwip_2.1.2 for idf_4.0 2019-07-07 01:51:45 +00:00
Angus Gratton
0b70dfc27f Add floating point performance test 2019-05-30 10:09:24 +10:00
Angus Gratton
c9edb7c8a9 mbedtls: Add AES-CBC performance test 
Hardware AES engine gets 11.0MB/sec on Release config
Software AES is around 2.3MB/sec on Release config
 2019-05-21 12:41:40 +10:00
Angus Gratton
12bdf8e45b esp32: Chunk input blocks for esp_sha() function performance, add perf test 2019-03-14 05:56:06 +00:00
Roland Dobai
738c56e84a Fix VFS_OPEN_WRITE_CLOSE_TIME unit test issue 
Closes idf/esp-idf#44
 2018-11-28 20:36:08 +01:00
qiyueixa
86fedc3cbb utest: increase IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME to 50000 2018-11-21 19:14:07 +08:00
Ivan Grokhotkov
6091021e83 unity: separate common and IDF specific functionality 
New unity component can be used for testing other applications.
Upstream version of Unity is included as a submodule.
Utilities specific to ESP-IDF unit tests (partitions, leak checking
setup/teardown functions, etc) are kept only in unit-test-app.
Kconfig options are added to allow disabling certain Unity features.
 2018-11-19 12:36:31 +08:00
Ivan Grokhotkov
d28c99d36c esp_event: lower test performance threshold for PSRAM config 2018-11-01 13:50:08 +08:00
Renz Christian Bagaporo
5a83347bec event: Implement event loop library 2018-10-26 13:14:19 +08:00
Michael (Xiao Xufeng)
4af51833f3 spi_master: add new polling mode to decrease time cost each transaction 2018-09-20 19:46:46 +08:00
Ivan Grokhotkov
964087b7c8 freertos: bump limit for spinlock performance test to 300 cycles 2018-07-24 09:56:40 +03:00
Angus Gratton
a2241fb4bc tests: Increase performance threshold for VFS running with PSRAM 
Cache effects on microbenchmarks in cached flash can be significant, depending on linker layout in flash.
 2018-05-17 21:02:47 +08:00
He Yin Ling
e8dd203e47 example test: add test case for iperf example 2018-05-15 13:42:26 +08:00
Roland Dobai
5129bca67c VFS: Use smaller numbers as file descriptors 2018-05-07 09:01:56 +02:00
Michael (Xiao Xufeng)
15be0829fa test(spi_master): test spi master speed performance by median value. 
also increase the boundary of SPI limit by a little.
 2018-03-16 16:37:19 +08:00
Ivan Grokhotkov
62f924544d Merge branch 'test/spi_performance' into 'master' 
test(spi_master): add performance display for spi master.

See merge request idf/esp-idf!1923
 2018-02-08 22:59:40 +08:00
Michael (Xiao Xufeng)
a151767426 test(spi_master): add performance display for spi master. 2018-02-07 17:50:13 +08:00
Jeroen Domburg
70ab924dbb Especially when internal memory fills up, some FreeRTOS structures (queues etc) get allocated in psram. These structures also contain a spinlock, which needs an atomic-compare-swap operation to work. The psram hardware, however, does not support this operation. As a workaround, this patch detects these spinlocks and will, instead of S32C1I, use equivalent C-code to simulate the behaviour, with an (internal) mux for atomicity. 2018-02-02 17:11:06 +08:00
He Yin Ling
63a401057c test: enlarge https bin size threshold: 
use performance matrix to tracking bin size is not convenient. bin size
do change for a lot reasons.

we'll implement a new method to track it. before that, set a large
enough threshold, so we can still keep tracking it.
 2018-02-01 09:57:00 +08:00
He Yin Ling
9395a702ef test: check and collect performance via CI 2017-11-16 17:48:30 +08:00