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Add floating point performance test
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@ -1,8 +1,10 @@
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#include <math.h>
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#include <stdio.h>
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#include "soc/cpu.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "unity.h"
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#include "test_utils.h"
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/* Note: these functions are included here for unit test purposes. They are not needed for writing
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* normal code. If writing standard C floating point code, libgcc should correctly include implementations
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@ -195,3 +197,70 @@ TEST_CASE("context switch saves FP registers", "[fp]")
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}
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TEST_ASSERT(state.fail == 0);
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}
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/* Note: not static, to avoid optimisation of const result */
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float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles)
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{
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float f = MAXFLOAT;
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uint32_t before, after;
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RSR(CCOUNT, before);
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for (int i = 0; i < counts; i++) {
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f /= 1.000432f;
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}
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RSR(CCOUNT, after);
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*cycles = (after - before) / counts;
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return f;
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}
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TEST_CASE("floating point division performance", "[fp]")
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{
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const unsigned COUNTS = 1000;
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unsigned cycles = 0;
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// initialize fpu
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volatile __attribute__((unused)) float dummy = sqrtf(rand());
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float f = test_fp_benchmark_fp_divide(COUNTS, &cycles);
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printf("%d divisions from %f = %f\n", COUNTS, MAXFLOAT, f);
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printf("Per division = %d cycles\n", cycles);
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TEST_PERFORMANCE_LESS_THAN(ESP32_CYCLES_PER_DIV, "%d cycles", cycles);
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}
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/* Note: not static, to avoid optimisation of const result */
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float IRAM_ATTR test_fp_benchmark_fp_sqrt(int counts, unsigned *cycles)
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{
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float f = MAXFLOAT;
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uint32_t before, after;
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RSR(CCOUNT, before);
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for (int i = 0; i < counts; i++) {
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f = sqrtf(f);
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}
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RSR(CCOUNT, after);
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*cycles = (after - before) / counts;
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return f;
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}
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TEST_CASE("floating point square root performance", "[fp]")
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{
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const unsigned COUNTS = 200;
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unsigned cycles = 0;
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// initialize fpu
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volatile float __attribute__((unused)) dummy = sqrtf(rand());
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float f = test_fp_benchmark_fp_sqrt(COUNTS, &cycles);
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printf("%d square roots from %f = %f\n", COUNTS, MAXFLOAT, f);
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printf("Per sqrt = %d cycles\n", cycles);
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TEST_PERFORMANCE_LESS_THAN(ESP32_CYCLES_PER_SQRT, "%d cycles", cycles);
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}
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@ -27,4 +27,7 @@
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#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB 4500
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// AES-CBC hardware throughput (accounts for worst-case performance with PSRAM workaround)
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#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 8.5
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// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_DIV 70
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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