alex/esp-idf
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34,836 Commits 20 Branches 148 Tags 384 MiB
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330 Commits

Author SHA1 Message Date
Wu Zheng Hui
55f04b3326 Merge branch 'feature/clean_up_retention_context_definitions' into 'master' 
refactor(esp_hw_support): move sleep retention context definition to soc target folder

Closes PM-10

See merge request espressif/esp-idf!26753
 2024-01-24 20:24:02 +08:00
wuzhenghui
f3f12e973c
refactor(esp_hw_support): separate different chip system peripheral regs context defs to target folder 2024-01-23 13:30:01 +08:00
wuzhenghui
9b3dc69908
refactor(esp_hw_support): move regdma structure defination to soc components 2024-01-23 11:51:44 +08:00
Mahavir Jain
9ecd2fd7e3 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-22 13:34:32 +08:00
Konstantin Kondrashov
261651fc19 Merge branch 'feature/efuse_update' into 'master' 
feat(efuse): Adds new efuses for H2 and C6 chips

See merge request espressif/esp-idf!27672
 2024-01-20 03:10:44 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
KonstantinKondrashov
ba0842a552 feat(efuse): Adds new efuses for esp32c6 2024-01-16 17:46:50 +08:00
Cao Sen Miao
0bf2b35b33 fix(i2c): Use hardware fsm reset on esp32c6/h2/p4 2024-01-16 10:05:05 +08:00
Kevin (Lao Kaiyao)
83d5797967 Merge branch 'feature/parlio_rx_driver' into 'master' 
driver: add parallel IO RX driver

Closes IDF-7002 and IDF-6984

See merge request espressif/esp-idf!23488
 2023-12-29 16:36:24 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4 
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
 2023-12-29 00:37:26 +08:00
laokaiyao
04d267b023 feat(parlio_rx): implement parallel io rx driver 2023-12-27 19:32:12 +08:00
Cao Sen Miao
439bc719fe feat(temperature_sensor): Add temperature sensor support on esp32p4 2023-12-26 16:45:20 +08:00
Xu Si Yu
6cef08c03d feat(ieee802154): add tx/rx report for IEEE802.15.4 debug 2023-12-14 12:29:57 +08:00
laokaiyao
2b44d62e43 feat(esp32c5): support esp32c5 g0 components 2023-12-08 15:12:24 +08:00
Armando
2c32bd209a change(fpga): added bypass rng configuration 2023-12-05 11:38:35 +08:00
Jakob Hasse
5f4865e838 Merge branch 'doc/soc_cap_tool' into 'master' 
Doc/soc cap tool

See merge request espressif/esp-idf!27154
 2023-11-23 10:47:01 +08:00
morris
72e414105d Merge branch 'contrib/github_pr_12559' into 'master' 
fix(spi): correct macro REG_SPI_BASE(i) for all targets (GitHub PR)

Closes IDFGH-11421 and IDFGH-11424

See merge request espressif/esp-idf!27085
 2023-11-20 15:55:41 +08:00
Mahavir Jain
9fb38d82a3 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets' into 'master' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2

Closes DOC-5161 and DOC-5175

See merge request espressif/esp-idf!27212
 2023-11-20 10:53:09 +08:00
Jakob Hasse
46e44ee154 docs(soc): improved soc caps generation documentation 2023-11-17 10:43:59 +08:00
wanlei
4dcd6d7913 fix(spi): correct some signals and dummy bits docs 2023-11-17 02:39:28 +00:00
TD-er
90eada6993 fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-11-17 02:39:28 +00:00
harshal.patil
798059ace1
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy 2023-11-16 17:49:26 +05:30
wuzhenghui
161bd8bfed change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 18:11:57 +08:00
Song Ruo Jing
46d33e46ef fix(console): enable to select UART1 port for console output 
This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
 2023-11-09 22:32:49 +08:00
C.S.M
4111b07076 Merge branch 'bugfix/flash_enc_plaintext' into 'master' 
fix(flash_encryption): Fix the issue that XTS_AES Plain text memory size wrong

See merge request espressif/esp-idf!26640
 2023-10-27 18:23:00 +08:00
Cao Sen Miao
420ac840ff fix(flash_encryption): Fix the issue that XTS_AES Plain text memory size wrong 2023-10-26 19:38:42 +08:00
morris
418494800c fix(i2c): read write FIFO memory by volatile 2023-10-26 14:40:07 +08:00
Cao Sen Miao
8d639492f2 feat(i2c_slave): Add new implementation and API for I2C slave 2023-10-24 18:44:49 +08:00
wuzhenghui
6a436286dc feat(esp_hw_support): add api to gpio driver to support output internal clock on GPIO 2023-10-20 14:35:26 +08:00
Mahavir Jain
2407813a67 Merge branch 'feature/update_esp32c6-h2_apm_api' into 'master' 
apm: updated APM HAL/LL APIs.

See merge request espressif/esp-idf!26368
 2023-10-18 12:26:38 +08:00
Sachin Billore
c106f5caf6 apm: updated APM HAL/LL APIs. 2023-10-17 18:20:36 +05:30
Armando
17063b51e0 feat(soc): added flash operation range macros in ext_mem_defs.h 2023-10-16 17:19:04 +08:00
Michael (XIAO Xufeng)
2308292ca3 Merge branch 'bugfix/revert_pvt' into 'master' 
Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2"

See merge request espressif/esp-idf!26425
 2023-10-16 12:53:07 +08:00
Song Ruo Jing
d73bf72885 Merge branch 'feature/gpio_dump_io_info' into 'master' 
feat(gpio): add a dump API to dump IO configurations

Closes IDFGH-10987

See merge request espressif/esp-idf!26158
 2023-10-13 22:35:59 +08:00
Song Ruo Jing
321f628ff5 feat(gpio): add a dump API to dump IO configurations 
Closes https://github.com/espressif/esp-idf/issues/12176
 2023-10-12 17:34:20 +08:00
Xiao Xufeng
28ba080c5e Revert "feat(volt): chip auto adjust volt for esp32c6 & esp32h2" 
This reverts commit b221f87e00.
 2023-10-12 14:51:54 +08:00
morris
66497af276 feat(hal): enable hal host test 2023-10-11 11:23:24 +08:00
gaoxu
4f24f805cc feat(uart): add LP-UART GPIO support 2023-10-08 10:10:02 +08:00
wuzhenghui
c8083b07bf feat(modem_clock): separate management of modem_adc_common_fe clock and modem_private_fe 2023-09-28 17:41:42 +00:00
Kevin (Lao Kaiyao)
4c6f4b39f1 Merge branch 'feature/support_i2s_on_p4' into 'master' 
feat(i2s): support i2s on esp32p4

Closes IDF-6508

See merge request espressif/esp-idf!24280
 2023-09-29 00:50:04 +08:00
laokaiyao
0b0f25c30d feat(i2s): supported getting the tx sync count and specify interrupt flags 2023-09-28 15:03:27 +08:00
laokaiyao
cf889f3c6d feat(i2s): support i2s on esp32p4 2023-09-28 15:03:27 +08:00
zlq
b221f87e00 feat(volt): chip auto adjust volt for esp32c6 & esp32h2 2023-09-28 05:55:42 +00:00
alanmaxwell
503299fb32 fix(phy): Fix PHY enabled enter WiFi RX state default 2023-09-26 16:23:58 +08:00
Ivan Grokhotkov
2ac972e2c7
fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency 2023-09-22 16:13:41 +02:00
Planck (Lu Zeyu)
255d499884 fix(ll): fix cpp compile error 
Merges https://github.com/espressif/esp-idf/pull/12093

fix(ll): remove FLAG_ATTR macro

Such kind of operator overload will not work because C++ thinks such overload is ambiguous and it still prefer the built-in one which accepts and returns integer. Manually force type conversion seems to be unavoidable.
 2023-09-14 14:48:12 +08:00
Konstantin Kondrashov
054d4943c5 Merge branch 'feature/esp32p4_update_systimer' into 'master' 
feat(esp_timer): Support systimer for ESP32P4

Closes IDF-7486 and IDF-7487

See merge request espressif/esp-idf!25688
 2023-09-13 19:13:39 +08:00
Konstantin Kondrashov
cbdb799b6f feat(esp_timer): Support systimer for ESP32P4 2023-09-13 19:13:38 +08:00
Marius Vikhammer
573404b328 Merge branch 'bugfix/use_xtal_for_c3_wdt' into 'master' 
fix(wdt): changed ESP32-C3 WDT to use XTAL as clock

Closes IDF-6729

See merge request espressif/esp-idf!25867
 2023-09-13 10:44:38 +08:00
Marius Vikhammer
7a71454930 fix(wdt): changed WDT clock source to XTAL for C6/H2 
Previously it used PLL, but PLL could potentially be powered down by power-management
when CPU frequency changed.
 2023-09-12 09:41:24 +08:00