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feat(i2s): support i2s on esp32p4

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This commit is contained in:
laokaiyao 2023-06-16 15:15:23 +08:00
parent 492c819357
commit cf889f3c6d
21 changed files with 1568 additions and 372 deletions
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4
components/driver/deprecated/i2s_legacy.c
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@ -654,12 +654,12 @@ static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint3
/* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
return real_freq;
}
return I2S_LL_DEFAULT_PLL_CLK_FREQ;
return I2S_LL_DEFAULT_CLK_FREQ;
#else
if (use_apll) {
ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source");
}
return I2S_LL_DEFAULT_PLL_CLK_FREQ;
return I2S_LL_DEFAULT_CLK_FREQ;
#endif
}

24
components/driver/i2s/include/driver/i2s_pdm.h
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@ -48,6 +48,24 @@ extern "C" {
.bclk_div = 8, \
}
#if SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
/**
* @brief PDM format in 2 slots(RX)
* @param bits_per_sample i2s data bit width, only support 16 bits for PDM mode
* @param mono_or_stereo I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO
*/
#define I2S_PDM_RX_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) { \
.data_bit_width = bits_per_sample, \
.slot_bit_width = I2S_SLOT_BIT_WIDTH_AUTO, \
.slot_mode = mono_or_stereo, \
.slot_mask = (mono_or_stereo == I2S_SLOT_MODE_MONO) ? \
I2S_PDM_SLOT_LEFT : I2S_PDM_SLOT_BOTH, \
.hp_en = true, \
.hp_cut_off_freq_hz = 35.5, \
.amplify_num = 1, \ /* TODO: maybe need an enum */
}
#endif // SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
/**
* @brief I2S slot configuration for pdm rx mode
*/
@ -58,6 +76,12 @@ typedef struct {
i2s_slot_mode_t slot_mode; /*!< Set mono or stereo mode with I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO */
/* Particular fields */
i2s_pdm_slot_mask_t slot_mask; /*!< Choose the slots to activate */
#if SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool hp_en; /*!< High pass filter enable */
float hp_cut_off_freq_hz; /*!< High pass filter cut-off frequency, range 23.3Hz ~ 185Hz, see cut-off frequency sheet above */
uint32_t amplify_num; /*!< The amplification number of the final conversion result, range 1~15, default 1 */
#endif // SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
} i2s_pdm_rx_slot_config_t;
/**

2
components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c
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@ -803,7 +803,9 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
#if SOC_I2S_SUPPORTS_PLL_F160M || SOC_I2S_SUPPORTS_PLL_F96M
i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
#endif // SOC_I2S_SUPPORTS_PLL_F160M || SOC_I2S_SUPPORTS_PLL_F96M
#if SOC_I2S_SUPPORTS_XTAL
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_XTAL;
i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);

16
components/esp_hw_support/port/esp32p4/rtc_clk.c
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@ -368,6 +368,22 @@ uint32_t rtc_clk_apb_freq_get(void)
return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ;
}
void rtc_clk_apll_enable(bool enable)
{
// TODO: IDF-7526
}
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2)
{
// TODO: IDF-7526
return 0;
}
void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
{
// TODO: IDF-7526
}
void rtc_dig_clk8m_enable(void)
{
clk_ll_rc_fast_digi_enable();

2
components/hal/esp32/include/hal/i2s_ll.h
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@ -48,7 +48,7 @@ extern "C" {
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief Enable DMA descriptor owner check

2
components/hal/esp32c3/include/hal/i2s_ll.h
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@ -34,7 +34,7 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief I2S module general init, enable I2S clock.

2
components/hal/esp32c6/include/hal/i2s_ll.h
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@ -35,7 +35,7 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief I2S module general init, enable I2S clock.

2
components/hal/esp32h2/include/hal/i2s_ll.h
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@ -36,7 +36,7 @@ extern "C" {
#define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz
#define I2S_LL_PLL_F64M_CLK_FREQ (64 * 1000000) // PLL_F64M_CLK: 64MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief I2S module general init, enable I2S clock.

1244
components/hal/esp32p4/include/i2s_ll.h Normal file
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File diff suppressed because it is too large Load Diff

2
components/hal/esp32s2/include/hal/i2s_ll.h
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@ -45,7 +45,7 @@ extern "C" {
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief Enable DMA descriptor owner check

2
components/hal/esp32s3/include/hal/i2s_ll.h
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@ -35,7 +35,7 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief I2S module general init, enable I2S clock.

49
components/hal/i2s_hal.c
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@ -10,7 +10,7 @@
#include "soc/soc.h"
#include "hal/i2s_hal.h"
#if SOC_I2S_HW_VERSION_2 && SOC_I2S_SUPPORTS_PDM_TX
#if SOC_I2S_HW_VERSION_2 && (SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER)
/* PDM tx high pass filter cut-off frequency and coefficients list
* [0]: cut-off frequency; [1]: param0; [2]: param5 */
static const float cut_off_coef[21][3] = {
@ -22,6 +22,22 @@ static const float cut_off_coef[21][3] = {
{63, 4, 7}, {58, 5, 6}, {49, 5, 7},
{46, 6, 6}, {35.5, 6, 7}, {23.3, 7, 7}
};
static void s_i2s_hal_get_cut_off_coef(float freq, uint32_t *param0, uint32_t *param5)
{
uint8_t cnt = 0;
float min = 1000;
/* Find the closest cut-off frequency and its coefficients */
for (int i = 0; i < 21; i++) {
float tmp = cut_off_coef[i][0] < freq ? freq - cut_off_coef[i][0] : cut_off_coef[i][0] - freq;
if (tmp < min) {
min = tmp;
cnt = i;
}
}
*param0 = (uint32_t)cut_off_coef[cnt][1];
*param5 = (uint32_t)cut_off_coef[cnt][2];
}
#endif
/**
@ -183,20 +199,12 @@ void i2s_hal_pdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
i2s_ll_tx_set_ws_idle_pol(hal->dev, false);
/* Slot mode seems not take effect according to the test, leave it default here */
i2s_ll_tx_pdm_slot_mode(hal->dev, is_mono, false, I2S_PDM_SLOT_BOTH);
uint8_t cnt = 0;
float min = 1000;
float expt_cut_off = slot_cfg->pdm_tx.hp_cut_off_freq_hz;
/* Find the closest cut-off frequency and its coefficients */
for (int i = 0; i < 21; i++) {
float tmp = cut_off_coef[i][0] < expt_cut_off ? expt_cut_off - cut_off_coef[i][0] : cut_off_coef[i][0] - expt_cut_off;
if (tmp < min) {
min = tmp;
cnt = i;
}
}
uint32_t param0;
uint32_t param5;
s_i2s_hal_get_cut_off_coef(slot_cfg->pdm_tx.hp_cut_off_freq_hz, &param0, &param5);
i2s_ll_tx_enable_pdm_hp_filter(hal->dev, slot_cfg->pdm_tx.hp_en);
i2s_ll_tx_set_pdm_hp_filter_param0(hal->dev, cut_off_coef[cnt][1]);
i2s_ll_tx_set_pdm_hp_filter_param5(hal->dev, cut_off_coef[cnt][2]);
i2s_ll_tx_set_pdm_hp_filter_param0(hal->dev, param0);
i2s_ll_tx_set_pdm_hp_filter_param5(hal->dev, param5);
i2s_ll_tx_set_pdm_sd_dither(hal->dev, slot_cfg->pdm_tx.sd_dither);
i2s_ll_tx_set_pdm_sd_dither2(hal->dev, slot_cfg->pdm_tx.sd_dither2);
#endif
@ -233,7 +241,18 @@ void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
uint32_t slot_mask = slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ? I2S_PDM_SLOT_BOTH : slot_cfg->pdm_rx.slot_mask;
#endif // SOC_I2S_SUPPORTS_PDM_RX > 1
i2s_ll_rx_set_active_chan_mask(hal->dev, slot_mask);
#endif // SOC_I2S_SUPPORTS_PDM_RX
#endif // SOC_I2S_HW_VERSION_1
#if SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER // TODO: add this macro to soc_caps
uint32_t param0;
uint32_t param5;
s_i2s_hal_get_cut_off_coef(slot_cfg->pdm_rx.hp_cut_off_freq_hz, &param0, &param5);
i2s_ll_rx_enable_pdm_hp_filter(hal->dev, slot_cfg->pdm_rx.hp_en);
i2s_ll_rx_set_pdm_hp_filter_param0(hal->dev, param0);
i2s_ll_rx_set_pdm_hp_filter_param5(hal->dev, param5);
/* Set the amplification number, the default and the minimum value is 1. 0 will mute the channel */
i2s_ll_rx_set_pdm_amplify_num(hal->dev, slot_cfg->pdm_rx.amplify_num ? slot_cfg->pdm_rx.amplify_num : 1);
#endif // SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
}
void i2s_hal_pdm_enable_rx_channel(i2s_hal_context_t *hal)

8
components/hal/include/hal/i2s_hal.h
View File

@ -91,7 +91,13 @@ typedef struct {
/* PDM TX configurations */
struct {
i2s_pdm_slot_mask_t slot_mask; /*!< Choose the slots to activate */
} pdm_rx; /*!< Specific configurations for PDM TX mode */
#if SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool hp_en; /*!< High pass filter enable */
float hp_cut_off_freq_hz; /*!< High pass filter cut-off frequency, range 23.3Hz ~ 185Hz, see cut-off frequency sheet above */
uint32_t amplify_num; /*!< The amplification number of the final conversion result */
#endif // SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
} pdm_rx; /*!< Specific configurations for PDM RX mode */
#endif
};

124
components/soc/esp32c6/include/soc/i2s_struct.h
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@ -240,34 +240,6 @@ typedef union {
uint32_t val;
} i2s_rx_conf1_reg_t;
/** Type of rx_clkm_conf register
* I2S RX clock configure register
*/
typedef union {
struct {
/** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S clock divider value
*/
uint32_t rx_clkm_div_num:8;
uint32_t reserved_8:18;
/** rx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Rx module clock enable signal.
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
* I2S_MCLK_OUT.
*/
uint32_t mclk_sel:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_rx_clkm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
@ -609,37 +581,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_clkm_conf register
* I2S TX clock configure register
*/
typedef union {
struct {
/** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
* (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
* a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
* (n+1)-div] + y * (n+1)-div.
*/
uint32_t tx_clkm_div_num:8;
uint32_t reserved_8:18;
/** tx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Tx module clock enable signal.
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
/** clk_en : R/W; bitpos: [29]; default: 0;
* Set this bit to enable clk gate
*/
uint32_t clk_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_tx_clkm_conf_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@ -742,36 +683,6 @@ typedef union {
/** Group: RX clock and timing registers */
/** Type of rx_clkm_div_conf register
* I2S RX module clock divider configure register
*/
typedef union {
struct {
/** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_RX_CLKM_DIV_Z is (a-b).
*/
uint32_t rx_clkm_div_z:9;
/** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_RX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t rx_clkm_div_y:9;
/** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t rx_clkm_div_x:9;
/** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_RX_CLKM_DIV_YN1 is 1.
*/
uint32_t rx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_rx_clkm_div_conf_reg_t;
/** Type of rx_timing register
* I2S RX timing control register
*/
@ -813,36 +724,6 @@ typedef union {
/** Group: TX clock and timing registers */
/** Type of tx_clkm_div_conf register
* I2S TX module clock divider configure register
*/
typedef union {
struct {
/** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_TX_CLKM_DIV_Z is (a-b).
*/
uint32_t tx_clkm_div_z:9;
/** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_TX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t tx_clkm_div_y:9;
/** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t tx_clkm_div_x:9;
/** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_TX_CLKM_DIV_YN1 is 1.
*/
uint32_t tx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_tx_clkm_div_conf_reg_t;
/** Type of tx_timing register
* I2S TX timing control register
*/
@ -993,10 +874,7 @@ typedef struct i2s_dev_t {
volatile i2s_tx_conf_reg_t tx_conf;
volatile i2s_rx_conf1_reg_t rx_conf1;
volatile i2s_tx_conf1_reg_t tx_conf1;
volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf;
volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf;
volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf;
volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf;
uint32_t reserved_030[4];
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
uint32_t reserved_048[2];

124
components/soc/esp32h2/include/soc/i2s_struct.h
View File

@ -240,34 +240,6 @@ typedef union {
uint32_t val;
} i2s_rx_conf1_reg_t;
/** Type of rx_clkm_conf register
* I2S RX clock configure register
*/
typedef union {
struct {
/** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S clock divider value
*/
uint32_t rx_clkm_div_num:8;
uint32_t reserved_8:18;
/** rx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Rx module clock enable signal.
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
* I2S_MCLK_OUT.
*/
uint32_t mclk_sel:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_rx_clkm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
@ -607,37 +579,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_clkm_conf register
* I2S TX clock configure register
*/
typedef union {
struct {
/** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
* (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
* a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
* (n+1)-div] + y * (n+1)-div.
*/
uint32_t tx_clkm_div_num:8;
uint32_t reserved_8:18;
/** tx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Tx module clock enable signal.
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
/** clk_en : R/W; bitpos: [29]; default: 0;
* Set this bit to enable clk gate
*/
uint32_t clk_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_tx_clkm_conf_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@ -740,36 +681,6 @@ typedef union {
/** Group: RX clock and timing registers */
/** Type of rx_clkm_div_conf register
* I2S RX module clock divider configure register
*/
typedef union {
struct {
/** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_RX_CLKM_DIV_Z is (a-b).
*/
uint32_t rx_clkm_div_z:9;
/** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_RX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t rx_clkm_div_y:9;
/** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t rx_clkm_div_x:9;
/** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_RX_CLKM_DIV_YN1 is 1.
*/
uint32_t rx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_rx_clkm_div_conf_reg_t;
/** Type of rx_timing register
* I2S RX timing control register
*/
@ -811,36 +722,6 @@ typedef union {
/** Group: TX clock and timing registers */
/** Type of tx_clkm_div_conf register
* I2S TX module clock divider configure register
*/
typedef union {
struct {
/** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_TX_CLKM_DIV_Z is (a-b).
*/
uint32_t tx_clkm_div_z:9;
/** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_TX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t tx_clkm_div_y:9;
/** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t tx_clkm_div_x:9;
/** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_TX_CLKM_DIV_YN1 is 1.
*/
uint32_t tx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_tx_clkm_div_conf_reg_t;
/** Type of tx_timing register
* I2S TX timing control register
*/
@ -991,10 +872,7 @@ typedef struct {
volatile i2s_tx_conf_reg_t tx_conf;
volatile i2s_rx_conf1_reg_t rx_conf1;
volatile i2s_tx_conf1_reg_t tx_conf1;
volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf;
volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf;
volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf;
volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf;
uint32_t reserved_030[4];
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
uint32_t reserved_048[2];

69
components/soc/esp32p4/i2s_periph.c
View File

@ -11,4 +11,73 @@
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
[0] = {
.mck_out_sig = I2S0_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S0_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S0_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S0_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S0_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S0_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S0_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S0_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S0_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S0_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = I2S0_O_SD1_PAD_OUT_IDX,
.data_in_sigs[0] = I2S0_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = I2S0_I_SD1_PAD_IN_IDX,
.data_in_sigs[2] = I2S0_I_SD2_PAD_IN_IDX,
.data_in_sigs[3] = I2S0_I_SD3_PAD_IN_IDX,
.irq = -1,
.module = PERIPH_I2S0_MODULE,
},
[1] = {
.mck_out_sig = I2S1_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S1_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S1_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S1_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S1_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S1_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S1_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S1_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S1_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S1_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = -1,
.data_in_sigs[0] = I2S1_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = -1,
.data_in_sigs[2] = -1,
.data_in_sigs[3] = -1,
.irq = -1,
.module = PERIPH_I2S1_MODULE,
},
[2] = {
.mck_out_sig = I2S2_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S2_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S2_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S2_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S2_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S2_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S2_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S2_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S2_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S2_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = -1,
.data_in_sigs[0] = I2S2_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = -1,
.data_in_sigs[2] = -1,
.data_in_sigs[3] = -1,
.irq = -1,
.module = PERIPH_I2S2_MODULE,
},
};

36
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -71,6 +71,10 @@ config SOC_I2C_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@ -433,7 +437,7 @@ config SOC_I2C_SUPPORT_RTC
config SOC_I2S_NUM
int
default 1
default 3
config SOC_I2S_HW_VERSION_2
bool
@ -443,7 +447,7 @@ config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
config SOC_I2S_SUPPORTS_APLL
bool
default y
@ -451,10 +455,38 @@ config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_PDM_MAX_RX_LINES
int
default 4
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y

15
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@ -150,6 +150,7 @@ typedef enum {
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
@ -334,6 +335,20 @@ typedef enum {
///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**

184
components/soc/esp32p4/include/soc/i2s_struct.h
View File

@ -277,6 +277,92 @@ typedef union {
uint32_t val;
} i2s_rx_pdm2pcm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
* I2S TX PDM bypass hp filter or not. The option has been removed.
*/
uint32_t tx_pdm_hp_bypass:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of rx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@ -371,7 +457,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@ -384,7 +470,7 @@ typedef union {
uint32_t reserved_12:20;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@ -530,89 +616,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@ -845,7 +848,7 @@ typedef union {
uint32_t val;
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
/** Type of conf_single_data register
* I2S signal data register
*/
typedef union {
@ -856,7 +859,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@ -986,8 +989,8 @@ typedef struct {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
volatile i2s_fifo_cnt_reg_t fifo_cnt;
@ -996,6 +999,9 @@ typedef struct {
volatile i2s_date_reg_t date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
extern i2s_dev_t I2S2;
#ifndef __cplusplus
_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");

19
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -50,6 +50,8 @@
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 //TODO: IDF-6508
#define SOC_RMT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
@ -240,16 +242,19 @@
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
//TODO: IDF-6508
#define SOC_I2S_NUM (1U)
#define SOC_I2S_NUM (3U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (1)
#define SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER (1)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)

10
examples/peripherals/.build-test-rules.yml
View File

@ -54,15 +54,15 @@ examples/peripherals/i2c/i2c_tools:
examples/peripherals/i2s/i2s_basic/i2s_pdm:
disable:
- if: SOC_I2S_SUPPORTS_PDM != 1
- if: SOC_I2S_SUPPORTS_PDM != 1 or IDF_TARGET == "esp32p4"
examples/peripherals/i2s/i2s_basic/i2s_std:
disable:
- if: SOC_I2S_SUPPORTED != 1
- if: SOC_I2S_SUPPORTED != 1 or IDF_TARGET == "esp32p4"
examples/peripherals/i2s/i2s_basic/i2s_tdm:
disable:
- if: SOC_I2S_SUPPORTS_TDM != 1
- if: SOC_I2S_SUPPORTS_TDM != 1 or IDF_TARGET == "esp32p4"
examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm:
disable:
@ -71,10 +71,12 @@ examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm:
examples/peripherals/i2s/i2s_codec/i2s_es8311:
disable:
- if: SOC_I2S_SUPPORTED != 1 or SOC_I2C_SUPPORTED != 1
- if: (SOC_I2S_SUPPORTED != 1 or SOC_I2C_SUPPORTED != 1) or IDF_TARGET == "esp32p4"
reason: rely on I2S STD mode and I2C to config es7210
examples/peripherals/i2s/i2s_recorder:
disable:
- if: IDF_TARGET == "esp32p4"
enable:
- if: SOC_I2S_SUPPORTS_PDM_RX > 0